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From: Fabio Estevam <festevam@denx.de>
To: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Cc: u-boot@lists.denx.de, Ye Li <ye.li@nxp.com>,
	Peng Fan <peng.fan@nxp.com>, Ying-Chun Liu <paul.liu@linaro.org>,
	Marek Vasut <marex@denx.de>
Subject: Re: [PATCH] imx8m: fix reading of DDR4 MR registers [again]
Date: Thu, 06 Oct 2022 10:17:56 -0300	[thread overview]
Message-ID: <f623aec6ff75744183ce86d0a6e17a14@denx.de> (raw)
In-Reply-To: <20221006125650.1666672-1-rasmus.villemoes@prevas.dk>

Hi Rasmus,

On 06/10/2022 09:56, Rasmus Villemoes wrote:
> Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a
> private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board
> code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version
> actually seems to work in practice.
> 
> However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
> reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c,
> copied most of the rest of ddrphy_utils.c to
> drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building
> drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally
> completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused
> file)].
> 
> I assume this must have broken the imx8mm-cl-iot-gate board, at least
> those that have not had their eeprom programmed with the proper
> information. It certainly did break our out-of-tree board which always
> reads back the ID register and uses that for a sanity check.
> 
> So apply the fix from 290ffe5788 once again.
> 
> Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>

Thanks for the fix:

Reviewed-by: Fabio Estevam <festevam@denx.de>

  reply	other threads:[~2022-10-06 13:18 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-06 12:56 [PATCH] imx8m: fix reading of DDR4 MR registers [again] Rasmus Villemoes
2022-10-06 13:17 ` Fabio Estevam [this message]
2022-10-24 13:54 ` sbabic

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