* [PATCH v3 01/15] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-27 10:26 ` Roger Quadros
2025-02-25 11:48 ` [PATCH v3 02/15] arm: mach-k3: am62x: am625_init: Remove explicit probing of " Chintan Vankar
` (13 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
CPSW driver is defined as UCLASS_MISC driver which needs to be probed
explicitly. Define bind method for CPSW driver to scan and bind
ethernet-ports with UCLASS_ETH driver which will eventually probe CPSW
driver and avoids probing CPSW driver explicitly.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v2:
https://lore.kernel.org/r/20250219104831.2315464-3-c-vankar@ti.com/
Changes from v2 to v3:
- Removed if condition not required in CPSW driver as suggested by
Alexander Sverdlin.
drivers/net/ti/am65-cpsw-nuss.c | 120 ++++++++++++++++++--------------
1 file changed, 67 insertions(+), 53 deletions(-)
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index c70b42f6bcc..10513cf92f2 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -667,6 +667,59 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
return 0;
}
+static int am65_cpsw_probe_nuss(struct udevice *dev)
+{
+ struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
+ int ret, i;
+
+ cpsw_common->dev = dev;
+ cpsw_common->ss_base = dev_read_addr(dev);
+ if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
+ if (ret) {
+ dev_err(dev, "failed to get pwrdmn: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
+ if (ret) {
+ power_domain_free(&cpsw_common->pwrdmn);
+ dev_err(dev, "failed to get clock %d\n", ret);
+ return ret;
+ }
+
+ cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
+ cpsw_common->ale_base = cpsw_common->cpsw_base +
+ AM65_CPSW_CPSW_NU_ALE_BASE;
+
+ for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
+ struct am65_cpsw_port *port = &cpsw_common->ports[i];
+
+ port->port_base = cpsw_common->cpsw_base +
+ AM65_CPSW_CPSW_NU_PORTS_OFFSET +
+ (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
+ port->port_sgmii_base = cpsw_common->ss_base +
+ (i * AM65_CPSW_SGMII_BASE);
+ port->macsl_base = port->port_base +
+ AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
+ }
+
+ cpsw_common->bus_freq =
+ dev_read_u32_default(dev, "bus_freq",
+ AM65_CPSW_MDIO_BUS_FREQ_DEF);
+
+ dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u\n",
+ readl(cpsw_common->ss_base),
+ readl(cpsw_common->cpsw_base),
+ readl(cpsw_common->ale_base),
+ cpsw_common->port_num);
+
+ power_domain_free(&cpsw_common->pwrdmn);
+ return ret;
+}
+
static int am65_cpsw_port_probe(struct udevice *dev)
{
struct am65_cpsw_priv *priv = dev_get_priv(dev);
@@ -697,45 +750,30 @@ out:
return ret;
}
-static int am65_cpsw_probe_nuss(struct udevice *dev)
+static int am65_cpsw_nuss_bind(struct udevice *dev)
{
struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
- ofnode ports_np, node;
- int ret, i;
+ struct uclass_driver *drv;
struct udevice *port_dev;
+ ofnode ports_np, node;
+ int ret;
- cpsw_common->dev = dev;
- cpsw_common->ss_base = dev_read_addr(dev);
- if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
- if (ret) {
- dev_err(dev, "failed to get pwrdmn: %d\n", ret);
- return ret;
- }
-
- ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
- if (ret) {
- power_domain_free(&cpsw_common->pwrdmn);
- dev_err(dev, "failed to get clock %d\n", ret);
- return ret;
+ drv = lists_uclass_lookup(UCLASS_ETH);
+ if (!drv) {
+ puts("Cannot find eth driver");
+ return -ENOENT;
}
- cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
- cpsw_common->ale_base = cpsw_common->cpsw_base +
- AM65_CPSW_CPSW_NU_ALE_BASE;
-
+ cpsw_common->dev = dev;
ports_np = dev_read_subnode(dev, "ethernet-ports");
if (!ofnode_valid(ports_np)) {
- ret = -ENOENT;
- goto out;
+ return -ENOENT;
}
ofnode_for_each_subnode(node, ports_np) {
const char *node_name;
- u32 port_id;
bool disabled;
+ u32 port_id;
node_name = ofnode_get_name(node);
@@ -745,14 +783,13 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
if (ret) {
dev_err(dev, "%s: failed to get port_id (%d)\n",
node_name, ret);
- goto out;
+ return ret;
}
if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) {
dev_err(dev, "%s: invalid port_id (%d)\n",
node_name, port_id);
- ret = -EINVAL;
- goto out;
+ return -EINVAL;
}
cpsw_common->port_num++;
@@ -768,30 +805,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node));
}
- for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
- struct am65_cpsw_port *port = &cpsw_common->ports[i];
-
- port->port_base = cpsw_common->cpsw_base +
- AM65_CPSW_CPSW_NU_PORTS_OFFSET +
- (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
- port->port_sgmii_base = cpsw_common->ss_base +
- (i * AM65_CPSW_SGMII_BASE);
- port->macsl_base = port->port_base +
- AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
- }
-
- cpsw_common->bus_freq =
- dev_read_u32_default(dev, "bus_freq",
- AM65_CPSW_MDIO_BUS_FREQ_DEF);
-
- dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u\n",
- readl(cpsw_common->ss_base),
- readl(cpsw_common->cpsw_base),
- readl(cpsw_common->ale_base),
- cpsw_common->port_num);
-
-out:
- power_domain_free(&cpsw_common->pwrdmn);
return ret;
}
@@ -806,6 +819,7 @@ U_BOOT_DRIVER(am65_cpsw_nuss) = {
.name = "am65_cpsw_nuss",
.id = UCLASS_MISC,
.of_match = am65_cpsw_nuss_ids,
+ .bind = am65_cpsw_nuss_bind,
.probe = am65_cpsw_probe_nuss,
.priv_auto = sizeof(struct am65_cpsw_common),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 01/15] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver
2025-02-25 11:48 ` [PATCH v3 01/15] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver Chintan Vankar
@ 2025-02-27 10:26 ` Roger Quadros
2025-03-04 4:45 ` Vankar, Chintan
0 siblings, 1 reply; 22+ messages in thread
From: Roger Quadros @ 2025-02-27 10:26 UTC (permalink / raw)
To: Chintan Vankar, Michael Walle, Matthias Schiffer, MD Danish Anwar,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Wadim Egorov,
Ramon Fried, Joe Hershberger, Jayesh Choudhary, Vaishnav Achath,
Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Hi,
On 25/02/2025 13:48, Chintan Vankar wrote:
> CPSW driver is defined as UCLASS_MISC driver which needs to be probed
> explicitly. Define bind method for CPSW driver to scan and bind
> ethernet-ports with UCLASS_ETH driver which will eventually probe CPSW
> driver and avoids probing CPSW driver explicitly.
Thank you for doing this. Overall it looks good. Just some cosmetic changes
suggested below.
>
> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
> ---
>
> Link to v2:
> https://lore.kernel.org/r/20250219104831.2315464-3-c-vankar@ti.com/
>
> Changes from v2 to v3:
> - Removed if condition not required in CPSW driver as suggested by
> Alexander Sverdlin.
>
> drivers/net/ti/am65-cpsw-nuss.c | 120 ++++++++++++++++++--------------
> 1 file changed, 67 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
> index c70b42f6bcc..10513cf92f2 100644
> --- a/drivers/net/ti/am65-cpsw-nuss.c
> +++ b/drivers/net/ti/am65-cpsw-nuss.c
> @@ -667,6 +667,59 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
> return 0;
> }
>
> +static int am65_cpsw_probe_nuss(struct udevice *dev)
> +{
> + struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
> + int ret, i;
> +
> + cpsw_common->dev = dev;
> + cpsw_common->ss_base = dev_read_addr(dev);
> + if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
> + return -EINVAL;
> +
> + ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
> + if (ret) {
> + dev_err(dev, "failed to get pwrdmn: %d\n", ret);
> + return ret;
> + }
> +
> + ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
> + if (ret) {
> + power_domain_free(&cpsw_common->pwrdmn);
> + dev_err(dev, "failed to get clock %d\n", ret);
> + return ret;
> + }
> +
> + cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
> + cpsw_common->ale_base = cpsw_common->cpsw_base +
> + AM65_CPSW_CPSW_NU_ALE_BASE;
> +
> + for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
> + struct am65_cpsw_port *port = &cpsw_common->ports[i];
> +
> + port->port_base = cpsw_common->cpsw_base +
> + AM65_CPSW_CPSW_NU_PORTS_OFFSET +
> + (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
> + port->port_sgmii_base = cpsw_common->ss_base +
> + (i * AM65_CPSW_SGMII_BASE);
> + port->macsl_base = port->port_base +
> + AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
> + }
> +
> + cpsw_common->bus_freq =
> + dev_read_u32_default(dev, "bus_freq",
> + AM65_CPSW_MDIO_BUS_FREQ_DEF);
> +
> + dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u\n",
> + readl(cpsw_common->ss_base),
> + readl(cpsw_common->cpsw_base),
> + readl(cpsw_common->ale_base),
> + cpsw_common->port_num);
> +
> + power_domain_free(&cpsw_common->pwrdmn);
> + return ret;
> +}
> +
Instead of moving the am65_cpsw_probe_nuss() please leave it where it was
and add the new am65_cpsw_nuss_bind() after it.
This way it will show only what really changed in diff and is easier to review.
> static int am65_cpsw_port_probe(struct udevice *dev)
> {
> struct am65_cpsw_priv *priv = dev_get_priv(dev);
> @@ -697,45 +750,30 @@ out:
> return ret;
> }
>
> -static int am65_cpsw_probe_nuss(struct udevice *dev)
> +static int am65_cpsw_nuss_bind(struct udevice *dev)
> {
> struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
> - ofnode ports_np, node;
> - int ret, i;
> + struct uclass_driver *drv;
> struct udevice *port_dev;
> + ofnode ports_np, node;
> + int ret;
>
> - cpsw_common->dev = dev;
> - cpsw_common->ss_base = dev_read_addr(dev);
> - if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
> - return -EINVAL;
> -
> - ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
> - if (ret) {
> - dev_err(dev, "failed to get pwrdmn: %d\n", ret);
> - return ret;
> - }
> -
> - ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
> - if (ret) {
> - power_domain_free(&cpsw_common->pwrdmn);
> - dev_err(dev, "failed to get clock %d\n", ret);
> - return ret;
> + drv = lists_uclass_lookup(UCLASS_ETH);
> + if (!drv) {
> + puts("Cannot find eth driver");
> + return -ENOENT;
I'm not sure why this check is required.
drv is not used anywhere.
> }
>
> - cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
> - cpsw_common->ale_base = cpsw_common->cpsw_base +
> - AM65_CPSW_CPSW_NU_ALE_BASE;
> -
> + cpsw_common->dev = dev;
> ports_np = dev_read_subnode(dev, "ethernet-ports");
> if (!ofnode_valid(ports_np)) {
> - ret = -ENOENT;
> - goto out;
> + return -ENOENT;
> }
>
> ofnode_for_each_subnode(node, ports_np) {
> const char *node_name;
> - u32 port_id;
> bool disabled;
> + u32 port_id;
>
> node_name = ofnode_get_name(node);
>
> @@ -745,14 +783,13 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
> if (ret) {
> dev_err(dev, "%s: failed to get port_id (%d)\n",
> node_name, ret);
> - goto out;
> + return ret;
> }
>
> if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) {
> dev_err(dev, "%s: invalid port_id (%d)\n",
> node_name, port_id);
> - ret = -EINVAL;
> - goto out;
> + return -EINVAL;
> }
> cpsw_common->port_num++;
>
> @@ -768,30 +805,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
> dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node));
> }
>
> - for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
> - struct am65_cpsw_port *port = &cpsw_common->ports[i];
> -
> - port->port_base = cpsw_common->cpsw_base +
> - AM65_CPSW_CPSW_NU_PORTS_OFFSET +
> - (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
> - port->port_sgmii_base = cpsw_common->ss_base +
> - (i * AM65_CPSW_SGMII_BASE);
> - port->macsl_base = port->port_base +
> - AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
> - }
> -
> - cpsw_common->bus_freq =
> - dev_read_u32_default(dev, "bus_freq",
> - AM65_CPSW_MDIO_BUS_FREQ_DEF);
> -
> - dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u\n",
> - readl(cpsw_common->ss_base),
> - readl(cpsw_common->cpsw_base),
> - readl(cpsw_common->ale_base),
> - cpsw_common->port_num);
> -
> -out:
> - power_domain_free(&cpsw_common->pwrdmn);
> return ret;
> }
>
> @@ -806,6 +819,7 @@ U_BOOT_DRIVER(am65_cpsw_nuss) = {
> .name = "am65_cpsw_nuss",
> .id = UCLASS_MISC,
> .of_match = am65_cpsw_nuss_ids,
> + .bind = am65_cpsw_nuss_bind,
> .probe = am65_cpsw_probe_nuss,
> .priv_auto = sizeof(struct am65_cpsw_common),
> };
--
cheers,
-roger
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 01/15] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver
2025-02-27 10:26 ` Roger Quadros
@ 2025-03-04 4:45 ` Vankar, Chintan
0 siblings, 0 replies; 22+ messages in thread
From: Vankar, Chintan @ 2025-03-04 4:45 UTC (permalink / raw)
To: Roger Quadros, Michael Walle, Matthias Schiffer, MD Danish Anwar,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Wadim Egorov,
Ramon Fried, Joe Hershberger, Jayesh Choudhary, Vaishnav Achath,
Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Hello Roger,
On 2/27/2025 3:56 PM, Roger Quadros wrote:
> Hi,
>
> On 25/02/2025 13:48, Chintan Vankar wrote:
>> CPSW driver is defined as UCLASS_MISC driver which needs to be probed
>> explicitly. Define bind method for CPSW driver to scan and bind
>> ethernet-ports with UCLASS_ETH driver which will eventually probe CPSW
>> driver and avoids probing CPSW driver explicitly.
>
> Thank you for doing this. Overall it looks good. Just some cosmetic changes
> suggested below.
>
Thank you for reviewing the series, I will make the changes mentioned by
you and post next version.
Regards,
Chintan.
>>
>> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
>> ---
>>
>> Link to v2:
>> https://lore.kernel.org/r/20250219104831.2315464-3-c-vankar@ti.com/
>>
>> Changes from v2 to v3:
>> - Removed if condition not required in CPSW driver as suggested by
>> Alexander Sverdlin.
>>
>> drivers/net/ti/am65-cpsw-nuss.c | 120 ++++++++++++++++++--------------
>> 1 file changed, 67 insertions(+), 53 deletions(-)
>>
>> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
>> index c70b42f6bcc..10513cf92f2 100644
>> --- a/drivers/net/ti/am65-cpsw-nuss.c
>> +++ b/drivers/net/ti/am65-cpsw-nuss.c
>> @@ -667,6 +667,59 @@ static int am65_cpsw_ofdata_parse_phy(struct udevice *dev)
>> return 0;
>> }
>>
>> +static int am65_cpsw_probe_nuss(struct udevice *dev)
>> +{
>> + struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
>> + int ret, i;
>> +
>> + cpsw_common->dev = dev;
>> + cpsw_common->ss_base = dev_read_addr(dev);
>> + if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
>> + return -EINVAL;
>> +
>> + ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
>> + if (ret) {
>> + dev_err(dev, "failed to get pwrdmn: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
>> + if (ret) {
>> + power_domain_free(&cpsw_common->pwrdmn);
>> + dev_err(dev, "failed to get clock %d\n", ret);
>> + return ret;
>> + }
>> +
>> + cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
>> + cpsw_common->ale_base = cpsw_common->cpsw_base +
>> + AM65_CPSW_CPSW_NU_ALE_BASE;
>> +
>> + for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
>> + struct am65_cpsw_port *port = &cpsw_common->ports[i];
>> +
>> + port->port_base = cpsw_common->cpsw_base +
>> + AM65_CPSW_CPSW_NU_PORTS_OFFSET +
>> + (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
>> + port->port_sgmii_base = cpsw_common->ss_base +
>> + (i * AM65_CPSW_SGMII_BASE);
>> + port->macsl_base = port->port_base +
>> + AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
>> + }
>> +
>> + cpsw_common->bus_freq =
>> + dev_read_u32_default(dev, "bus_freq",
>> + AM65_CPSW_MDIO_BUS_FREQ_DEF);
>> +
>> + dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u\n",
>> + readl(cpsw_common->ss_base),
>> + readl(cpsw_common->cpsw_base),
>> + readl(cpsw_common->ale_base),
>> + cpsw_common->port_num);
>> +
>> + power_domain_free(&cpsw_common->pwrdmn);
>> + return ret;
>> +}
>> +
>
> Instead of moving the am65_cpsw_probe_nuss() please leave it where it was
> and add the new am65_cpsw_nuss_bind() after it.
> This way it will show only what really changed in diff and is easier to review.
>
>> static int am65_cpsw_port_probe(struct udevice *dev)
>> {
>> struct am65_cpsw_priv *priv = dev_get_priv(dev);
>> @@ -697,45 +750,30 @@ out:
>> return ret;
>> }
>>
>> -static int am65_cpsw_probe_nuss(struct udevice *dev)
>> +static int am65_cpsw_nuss_bind(struct udevice *dev)
>> {
>> struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
>> - ofnode ports_np, node;
>> - int ret, i;
>> + struct uclass_driver *drv;
>> struct udevice *port_dev;
>> + ofnode ports_np, node;
>> + int ret;
>>
>> - cpsw_common->dev = dev;
>> - cpsw_common->ss_base = dev_read_addr(dev);
>> - if (cpsw_common->ss_base == FDT_ADDR_T_NONE)
>> - return -EINVAL;
>> -
>> - ret = power_domain_get_by_index(dev, &cpsw_common->pwrdmn, 0);
>> - if (ret) {
>> - dev_err(dev, "failed to get pwrdmn: %d\n", ret);
>> - return ret;
>> - }
>> -
>> - ret = clk_get_by_name(dev, "fck", &cpsw_common->fclk);
>> - if (ret) {
>> - power_domain_free(&cpsw_common->pwrdmn);
>> - dev_err(dev, "failed to get clock %d\n", ret);
>> - return ret;
>> + drv = lists_uclass_lookup(UCLASS_ETH);
>> + if (!drv) {
>> + puts("Cannot find eth driver");
>> + return -ENOENT;
>
> I'm not sure why this check is required.
> drv is not used anywhere.
> >> }
>>
>> - cpsw_common->cpsw_base = cpsw_common->ss_base + AM65_CPSW_CPSW_NU_BASE;
>> - cpsw_common->ale_base = cpsw_common->cpsw_base +
>> - AM65_CPSW_CPSW_NU_ALE_BASE;
>> -
>> + cpsw_common->dev = dev;
>> ports_np = dev_read_subnode(dev, "ethernet-ports");
>> if (!ofnode_valid(ports_np)) {
>> - ret = -ENOENT;
>> - goto out;
>> + return -ENOENT;
>> }
>>
>> ofnode_for_each_subnode(node, ports_np) {
>> const char *node_name;
>> - u32 port_id;
>> bool disabled;
>> + u32 port_id;
>>
>> node_name = ofnode_get_name(node);
>>
>> @@ -745,14 +783,13 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
>> if (ret) {
>> dev_err(dev, "%s: failed to get port_id (%d)\n",
>> node_name, ret);
>> - goto out;
>> + return ret;
>> }
>>
>> if (port_id >= AM65_CPSW_CPSWNU_MAX_PORTS) {
>> dev_err(dev, "%s: invalid port_id (%d)\n",
>> node_name, port_id);
>> - ret = -EINVAL;
>> - goto out;
>> + return -EINVAL;
>> }
>> cpsw_common->port_num++;
>>
>> @@ -768,30 +805,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
>> dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node));
>> }
>>
>> - for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
>> - struct am65_cpsw_port *port = &cpsw_common->ports[i];
>> -
>> - port->port_base = cpsw_common->cpsw_base +
>> - AM65_CPSW_CPSW_NU_PORTS_OFFSET +
>> - (i * AM65_CPSW_CPSW_NU_PORTS_OFFSET);
>> - port->port_sgmii_base = cpsw_common->ss_base +
>> - (i * AM65_CPSW_SGMII_BASE);
>> - port->macsl_base = port->port_base +
>> - AM65_CPSW_CPSW_NU_PORT_MACSL_OFFSET;
>> - }
>> -
>> - cpsw_common->bus_freq =
>> - dev_read_u32_default(dev, "bus_freq",
>> - AM65_CPSW_MDIO_BUS_FREQ_DEF);
>> -
>> - dev_info(dev, "K3 CPSW: nuss_ver: 0x%08X cpsw_ver: 0x%08X ale_ver: 0x%08X Ports:%u\n",
>> - readl(cpsw_common->ss_base),
>> - readl(cpsw_common->cpsw_base),
>> - readl(cpsw_common->ale_base),
>> - cpsw_common->port_num);
>> -
>> -out:
>> - power_domain_free(&cpsw_common->pwrdmn);
>> return ret;
>> }
>>
>> @@ -806,6 +819,7 @@ U_BOOT_DRIVER(am65_cpsw_nuss) = {
>> .name = "am65_cpsw_nuss",
>> .id = UCLASS_MISC,
>> .of_match = am65_cpsw_nuss_ids,
>> + .bind = am65_cpsw_nuss_bind,
>> .probe = am65_cpsw_probe_nuss,
>> .priv_auto = sizeof(struct am65_cpsw_common),
>> };
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 02/15] arm: mach-k3: am62x: am625_init: Remove explicit probing of CPSW driver
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
2025-02-25 11:48 ` [PATCH v3 01/15] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-27 10:42 ` Roger Quadros
2025-02-25 11:48 ` [PATCH v3 03/15] arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot Chintan Vankar
` (12 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Bind method of am65_cpsw_nuss driver will ensure binding of it's child
driver am65_cpsw_nuss_ports, and there is no need to call CPSW driver
explicitly. Remove explicit probing of CPSW driver for AM62x.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v2:
https://lore.kernel.org/r/20250219104831.2315464-4-c-vankar@ti.com/
Changes from v2 to v3:
- Updated commit subject and commit message.
arch/arm/mach-k3/am62x/am625_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c
index 595fc391ac5..72a752d38e8 100644
--- a/arch/arm/mach-k3/am62x/am625_init.c
+++ b/arch/arm/mach-k3/am62x/am625_init.c
@@ -282,15 +282,6 @@ void board_init_f(ulong dummy)
}
spl_enable_cache();
- if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
- spl_boot_device() == BOOT_DEVICE_ETHERNET) {
- struct udevice *cpswdev;
-
- if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss),
- &cpswdev))
- printf("Failed to probe am65_cpsw_nuss driver\n");
- }
-
fixup_a53_cpu_freq_by_speed_grade();
}
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 02/15] arm: mach-k3: am62x: am625_init: Remove explicit probing of CPSW driver
2025-02-25 11:48 ` [PATCH v3 02/15] arm: mach-k3: am62x: am625_init: Remove explicit probing of " Chintan Vankar
@ 2025-02-27 10:42 ` Roger Quadros
0 siblings, 0 replies; 22+ messages in thread
From: Roger Quadros @ 2025-02-27 10:42 UTC (permalink / raw)
To: Chintan Vankar, Michael Walle, Matthias Schiffer, MD Danish Anwar,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Wadim Egorov,
Ramon Fried, Joe Hershberger, Jayesh Choudhary, Vaishnav Achath,
Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
On 25/02/2025 13:48, Chintan Vankar wrote:
> Bind method of am65_cpsw_nuss driver will ensure binding of it's child
> driver am65_cpsw_nuss_ports, and there is no need to call CPSW driver
> explicitly. Remove explicit probing of CPSW driver for AM62x.
>
> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
You should just revert commit 35bddf889652 ("arm: mach-k3: am62x: am625_init: Probe AM65 CPSW NUSS")
> ---
>
> Link to v2:
> https://lore.kernel.org/r/20250219104831.2315464-4-c-vankar@ti.com/
>
> Changes from v2 to v3:
> - Updated commit subject and commit message.
>
> arch/arm/mach-k3/am62x/am625_init.c | 9 ---------
> 1 file changed, 9 deletions(-)
>
> diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c
> index 595fc391ac5..72a752d38e8 100644
> --- a/arch/arm/mach-k3/am62x/am625_init.c
> +++ b/arch/arm/mach-k3/am62x/am625_init.c
> @@ -282,15 +282,6 @@ void board_init_f(ulong dummy)
> }
> spl_enable_cache();
>
> - if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
> - spl_boot_device() == BOOT_DEVICE_ETHERNET) {
> - struct udevice *cpswdev;
> -
> - if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss),
> - &cpswdev))
> - printf("Failed to probe am65_cpsw_nuss driver\n");
> - }
> -
> fixup_a53_cpu_freq_by_speed_grade();
> }
>
what about mach-k3/am64x/am642_init.c?
Please revert the relevant commit there as well.
and the same thing done in mach-k3/common.c?
Please revert the relevant commit there too.
It would be OK if you squash all 3 reverts into one patch.
As a separate patch you will also have to remove the part where cpsw_port2 node is
disabled in various k3-*-u-boot.dtsi files [1]. That is no longer needed as now we should
be able to support multiple ethernet ports.
[1] -
k3-am625-beagleplay-u-boot.dtsi:&cpsw_port2 {
k3-am625-phyboard-lyra-rdk-u-boot.dtsi:&cpsw_port2 {
k3-am625-sk-u-boot.dtsi:&cpsw_port2 {
k3-am642-evm-u-boot.dtsi:&cpsw_port2 {
k3-am642-sk-u-boot.dtsi:&cpsw_port2 {
--
cheers,
-roger
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 03/15] arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
2025-02-25 11:48 ` [PATCH v3 01/15] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver Chintan Vankar
2025-02-25 11:48 ` [PATCH v3 02/15] arm: mach-k3: am62x: am625_init: Remove explicit probing of " Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-26 7:43 ` Neha Malcom Francis
2025-02-25 11:48 ` [PATCH v3 04/15] arm: mach-k3: j721s2_spl: Alias Ethernet boot to CPGMAC Chintan Vankar
` (11 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Update dev-data and clk-data generated using ksswtool-autogen to include
CPSW device which is required for Ethernet Boot, also use ARRAY_SIZE()
MACRO to avoid hard-coding array size.
Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v2:
https://lore.kernel.org/r/20250219104831.2315464-5-c-vankar@ti.com/
Changes from v2 to v3:
- No changes.
arch/arm/mach-k3/r5/j721s2/clk-data.c | 58 +++++++++++++++++++++++++--
arch/arm/mach-k3/r5/j721s2/dev-data.c | 3 +-
2 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c
index 0c5c321c1eb..0130c9c4b86 100644
--- a/arch/arm/mach-k3/r5/j721s2/clk-data.c
+++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Dave Gerlach <d-gerlach@ti.com>.
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/clk-provider.h>
@@ -55,6 +55,32 @@ static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
"hsdiv4_16fft_mcu_2_hsdivout4_clk",
};
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+ "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_3_hsdivout1_clk",
+ "postdiv3_16fft_main_0_hsdivout6_clk",
+ "board_0_mcu_cpts0_rft_clk_out",
+ "board_0_cpts0_rft_clk_out",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+};
+
static const char * const mcu_usart_clksel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"postdiv3_16fft_main_1_hsdivout5_clk",
@@ -174,7 +200,11 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -199,6 +229,8 @@ static const struct clk_data clk_list[] = {
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
+ CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
+ CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0),
CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
@@ -275,6 +307,24 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(29, 3, "cpsw2g_cpts_rclk_sel_out0"),
+ DEV_CLK(29, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+ DEV_CLK(29, 5, "postdiv3_16fft_main_0_hsdivout6_clk"),
+ DEV_CLK(29, 6, "board_0_mcu_cpts0_rft_clk_out"),
+ DEV_CLK(29, 7, "board_0_cpts0_rft_clk_out"),
+ DEV_CLK(29, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(29, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(29, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+ DEV_CLK(29, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(29, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(29, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(29, 22, "board_0_mcu_rgmii1_rxc_out"),
+ DEV_CLK(29, 26, "board_0_mcu_rmii1_ref_clk_out"),
+ DEV_CLK(29, 28, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(29, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(29, 30, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(29, 32, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(29, 33, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
@@ -367,6 +417,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
+ DEV_CLK(157, 207, "cpsw_2guss_mcu_0_mdio_mdclk_o"),
DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
@@ -374,6 +425,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+ DEV_CLK(157, 244, "cpsw_2guss_mcu_0_rgmii1_txc_o"),
DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
@@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
const struct ti_k3_clk_platdata j721s2_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 105,
+ .clk_list_cnt = ARRAY_SIZE(clk_list),
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 124,
+ .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
};
diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c
index df70c5e5d7c..b78550707c5 100644
--- a/arch/arm/mach-k3/r5/j721s2/dev-data.c
+++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Dave Gerlach <d-gerlach@ti.com>.
*
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-dev.h"
@@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
};
static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(29, &soc_lpsc_list[0]),
PSC_DEV(35, &soc_lpsc_list[0]),
PSC_DEV(108, &soc_lpsc_list[0]),
PSC_DEV(109, &soc_lpsc_list[0]),
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 03/15] arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot
2025-02-25 11:48 ` [PATCH v3 03/15] arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot Chintan Vankar
@ 2025-02-26 7:43 ` Neha Malcom Francis
0 siblings, 0 replies; 22+ messages in thread
From: Neha Malcom Francis @ 2025-02-26 7:43 UTC (permalink / raw)
To: Chintan Vankar, Michael Walle, Matthias Schiffer, MD Danish Anwar,
Roger Quadros, Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Andreas Dannenberg,
Andrew Davis, Alexander Sverdlin, Joao Paulo Goncalves,
Kishon Vijay Abraham I, Wadim Egorov, Ramon Fried,
Joe Hershberger, Jayesh Choudhary, Vaishnav Achath,
Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Hi Chintan
On 25/02/25 17:18, Chintan Vankar wrote:
> Update dev-data and clk-data generated using ksswtool-autogen to include
The tool is not publicly available as of now so you can remove the name
and mention that it is auto-generated instead.
> CPSW device which is required for Ethernet Boot, also use ARRAY_SIZE()
> MACRO to avoid hard-coding array size.
>
> Reviewed-by: Bryan Brattlof <bb@ti.com>
> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
> ---
>
> Link to v2:
> https://lore.kernel.org/r/20250219104831.2315464-5-c-vankar@ti.com/
>
> Changes from v2 to v3:
> - No changes.
>
> arch/arm/mach-k3/r5/j721s2/clk-data.c | 58 +++++++++++++++++++++++++--
> arch/arm/mach-k3/r5/j721s2/dev-data.c | 3 +-
> 2 files changed, 57 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c
> index 0c5c321c1eb..0130c9c4b86 100644
> --- a/arch/arm/mach-k3/r5/j721s2/clk-data.c
> +++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c
> @@ -5,7 +5,7 @@
> * This file is auto generated. Please do not hand edit and report any issues
> * to Dave Gerlach <d-gerlach@ti.com>.
> *
> - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #include <linux/clk-provider.h>
> @@ -55,6 +55,32 @@ static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
> "hsdiv4_16fft_mcu_2_hsdivout4_clk",
> };
>
> +static const char * const wkup_gpio0_clksel_out0_parents[] = {
> + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
> + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
> + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
> + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
> +};
> +
> +static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {
> + "hsdiv4_16fft_main_3_hsdivout1_clk",
> + "postdiv3_16fft_main_0_hsdivout6_clk",
> + "board_0_mcu_cpts0_rft_clk_out",
> + "board_0_cpts0_rft_clk_out",
> + "board_0_mcu_ext_refclk0_out",
> + "board_0_ext_refclk1_out",
> + NULL,
> + NULL,
> + NULL,
> + NULL,
> + NULL,
> + NULL,
> + NULL,
> + NULL,
> + "hsdiv4_16fft_mcu_2_hsdivout1_clk",
> + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
> +};
> +
> static const char * const mcu_usart_clksel_out0_parents[] = {
> "hsdiv4_16fft_mcu_1_hsdivout3_clk",
> "postdiv3_16fft_main_1_hsdivout5_clk",
> @@ -174,7 +200,11 @@ static const struct clk_data clk_list[] = {
> CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
> CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
> CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
> + CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0),
> + CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0),
> CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
> + CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0),
> + CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0),
> CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
> CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
> CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
> @@ -199,6 +229,8 @@ static const struct clk_data clk_list[] = {
> CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
> CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
> CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
> + CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
> + CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0),
> CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
> CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
> CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
> @@ -275,6 +307,24 @@ static const struct dev_clk soc_dev_clk_data[] = {
> DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
> DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
> DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(29, 3, "cpsw2g_cpts_rclk_sel_out0"),
> + DEV_CLK(29, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"),
> + DEV_CLK(29, 5, "postdiv3_16fft_main_0_hsdivout6_clk"),
> + DEV_CLK(29, 6, "board_0_mcu_cpts0_rft_clk_out"),
> + DEV_CLK(29, 7, "board_0_cpts0_rft_clk_out"),
> + DEV_CLK(29, 8, "board_0_mcu_ext_refclk0_out"),
> + DEV_CLK(29, 9, "board_0_ext_refclk1_out"),
> + DEV_CLK(29, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
> + DEV_CLK(29, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(29, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
> + DEV_CLK(29, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
> + DEV_CLK(29, 22, "board_0_mcu_rgmii1_rxc_out"),
> + DEV_CLK(29, 26, "board_0_mcu_rmii1_ref_clk_out"),
> + DEV_CLK(29, 28, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> + DEV_CLK(29, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
> + DEV_CLK(29, 30, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
> + DEV_CLK(29, 32, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
> + DEV_CLK(29, 33, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
> DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
> DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
> DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
> @@ -367,6 +417,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
> DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
> DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
> DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
> + DEV_CLK(157, 207, "cpsw_2guss_mcu_0_mdio_mdclk_o"),
> DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
> DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
> DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
> @@ -374,6 +425,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
> DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
> DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
> DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
> + DEV_CLK(157, 244, "cpsw_2guss_mcu_0_rgmii1_txc_o"),
> DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
> DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
> DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
> @@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
>
> const struct ti_k3_clk_platdata j721s2_clk_platdata = {
> .clk_list = clk_list,
> - .clk_list_cnt = 105,
> + .clk_list_cnt = ARRAY_SIZE(clk_list),
> .soc_dev_clk_data = soc_dev_clk_data,
> - .soc_dev_clk_data_cnt = 124,
> + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
> };
> diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c
> index df70c5e5d7c..b78550707c5 100644
> --- a/arch/arm/mach-k3/r5/j721s2/dev-data.c
> +++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c
> @@ -5,7 +5,7 @@
> * This file is auto generated. Please do not hand edit and report any issues
> * to Dave Gerlach <d-gerlach@ti.com>.
> *
> - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #include "k3-dev.h"
> @@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
> };
>
> static struct ti_dev soc_dev_list[] = {
> + PSC_DEV(29, &soc_lpsc_list[0]),
> PSC_DEV(35, &soc_lpsc_list[0]),
> PSC_DEV(108, &soc_lpsc_list[0]),
> PSC_DEV(109, &soc_lpsc_list[0]),
--
Thanking You
Neha Malcom Francis
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 04/15] arm: mach-k3: j721s2_spl: Alias Ethernet boot to CPGMAC
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (2 preceding siblings ...)
2025-02-25 11:48 ` [PATCH v3 03/15] arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-25 11:48 ` [PATCH v3 05/15] net: ti: Kconfig: Enable SPL_SYSCON config for CPSW Chintan Vankar
` (10 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
This is required to enable spl_net boot on AM68-SK.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v2:
https://lore.kernel.org/r/20250219104831.2315464-6-c-vankar@ti.com/
Changes from v2 to v3:
- No changes.
arch/arm/mach-k3/include/mach/j721s2_spl.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h
index d8fae2c8b45..47a61281d94 100644
--- a/arch/arm/mach-k3/include/mach/j721s2_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h
@@ -12,6 +12,7 @@
#define BOOT_DEVICE_OSPI 0x01
#define BOOT_DEVICE_QSPI 0x02
#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_CPGMAC 0x04
#define BOOT_DEVICE_ETHERNET 0x04
#define BOOT_DEVICE_I2C 0x06
#define BOOT_DEVICE_UART 0x07
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 05/15] net: ti: Kconfig: Enable SPL_SYSCON config for CPSW
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (3 preceding siblings ...)
2025-02-25 11:48 ` [PATCH v3 04/15] arm: mach-k3: j721s2_spl: Alias Ethernet boot to CPGMAC Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-25 13:39 ` Sverdlin, Alexander
2025-02-25 11:48 ` [PATCH v3 06/15] configs: am68: Add configs for enabling Ethboot in R5SPL Chintan Vankar
` (9 subsequent siblings)
14 siblings, 1 reply; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
TI's Ethernet switch needs system controllers enabled in R5SPL stage while
booting via Ethernet. Enable SPL_SYSCON config for
CONFIG_TI_AM65_CPSW_NUSS.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
This patch is new in this series.
drivers/net/ti/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index ddfa95a0b7e..3d495a56670 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -46,6 +46,7 @@ config TI_AM65_CPSW_NUSS
imply MISC
imply SYSCON
imply MDIO_TI_CPSW
+ imply SPL_SYSCON
select PHYLIB
help
This driver supports TI K3 MCU CPSW Nuss Ethernet controller
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 05/15] net: ti: Kconfig: Enable SPL_SYSCON config for CPSW
2025-02-25 11:48 ` [PATCH v3 05/15] net: ti: Kconfig: Enable SPL_SYSCON config for CPSW Chintan Vankar
@ 2025-02-25 13:39 ` Sverdlin, Alexander
0 siblings, 0 replies; 22+ messages in thread
From: Sverdlin, Alexander @ 2025-02-25 13:39 UTC (permalink / raw)
To: joao.goncalves@toradex.com, joe.hershberger@ni.com,
c-vankar@ti.com, bb@ti.com, mwalle@kernel.org, dannenberg@ti.com,
n-francis@ti.com, trini@konsulko.com, s-k6@ti.com, afd@ti.com,
j-choudhary@ti.com, hnagalla@ti.com, m-chawdhry@ti.com,
danishanwar@ti.com, j-humphreys@ti.com, w.egorov@phytec.de,
ilias.apalodimas@linaro.org, kishon@ti.com, vaishnav.a@ti.com,
matthias.schiffer@ew.tq-group.com, rogerq@kernel.org,
rfried.dev@gmail.com, vigneshr@ti.com
Cc: s-vadapalli@ti.com, u-boot@lists.denx.de
On Tue, 2025-02-25 at 17:18 +0530, Chintan Vankar wrote:
> TI's Ethernet switch needs system controllers enabled in R5SPL stage while
> booting via Ethernet. Enable SPL_SYSCON config for
> CONFIG_TI_AM65_CPSW_NUSS.
>
> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
> ---
>
> This patch is new in this series.
>
> drivers/net/ti/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
> index ddfa95a0b7e..3d495a56670 100644
> --- a/drivers/net/ti/Kconfig
> +++ b/drivers/net/ti/Kconfig
> @@ -46,6 +46,7 @@ config TI_AM65_CPSW_NUSS
> imply MISC
> imply SYSCON
> imply MDIO_TI_CPSW
> + imply SPL_SYSCON
> select PHYLIB
> help
> This driver supports TI K3 MCU CPSW Nuss Ethernet controller
--
Alexander Sverdlin
Siemens AG
www.siemens.com
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 06/15] configs: am68: Add configs for enabling Ethboot in R5SPL
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (4 preceding siblings ...)
2025-02-25 11:48 ` [PATCH v3 05/15] net: ti: Kconfig: Enable SPL_SYSCON config for CPSW Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-25 11:48 ` [PATCH v3 07/15] configs: am68: Enable configs required for Ethernet boot Chintan Vankar
` (8 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Add configs for enabling Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v2:
https://lore.kernel.org/r/20250219104831.2315464-7-c-vankar@ti.com/
Changes from v2 to v3:
- Removed not required config options from the file as suggested by
Andrew Davis.
configs/am68_sk_r5_ethboot_defconfig | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 configs/am68_sk_r5_ethboot_defconfig
diff --git a/configs/am68_sk_r5_ethboot_defconfig b/configs/am68_sk_r5_ethboot_defconfig
new file mode 100644
index 00000000000..f0815b781d5
--- /dev/null
+++ b/configs/am68_sk_r5_ethboot_defconfig
@@ -0,0 +1,23 @@
+#include <configs/am68_sk_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_R5_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM68 U-Boot R5 SPL"
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_SPI=n
+CONFIG_SPL_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_MTD=n
+CONFIG_SPL_MTD=n
+CONFIG_SPL_NAND_SPI_SUPPORT=n
+CONFIG_NOR_SUPPORT=n
+CONFIG_SPL_NOR_SUPPORT=n
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 07/15] configs: am68: Enable configs required for Ethernet boot
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (5 preceding siblings ...)
2025-02-25 11:48 ` [PATCH v3 06/15] configs: am68: Add configs for enabling Ethboot in R5SPL Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-25 11:48 ` [PATCH v3 08/15] arm: mach-k3: am62p: Update SoC auto-gen data to enable CPSW boot Chintan Vankar
` (7 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Enable config options needed to support Ethernet boot on AM68-SK.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v2:
https://lore.kernel.org/r/20250219104831.2315464-8-c-vankar@ti.com/
Changes from v2 to v3:
- No changes.
configs/am68_sk_a72_ethboot_defconfig | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 configs/am68_sk_a72_ethboot_defconfig
diff --git a/configs/am68_sk_a72_ethboot_defconfig b/configs/am68_sk_a72_ethboot_defconfig
new file mode 100644
index 00000000000..d9d6ca6088e
--- /dev/null
+++ b/configs/am68_sk_a72_ethboot_defconfig
@@ -0,0 +1,14 @@
+#include <configs/am68_sk_a72_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_A72_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am68-sk-base-board"
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM68 U-Boot A72 SPL"
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 08/15] arm: mach-k3: am62p: Update SoC auto-gen data to enable CPSW boot
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (6 preceding siblings ...)
2025-02-25 11:48 ` [PATCH v3 07/15] configs: am68: Enable configs required for Ethernet boot Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-25 11:48 ` [PATCH v3 09/15] board: ti: am62px: evm: Enable cache for AM62p Chintan Vankar
` (6 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
From: Andreas Dannenberg <dannenberg@ti.com>
Update dev-data and clk-data for AM62p to enable Ethernet boot using CPSW.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v2:
https://lore.kernel.org/r/20250219104831.2315464-10-c-vankar@ti.com/
Changes from v2 to v3:
- No changes.
arch/arm/mach-k3/r5/am62px/clk-data.c | 44 +++++++++++++++++++++++++--
arch/arm/mach-k3/r5/am62px/dev-data.c | 24 ++++++++-------
2 files changed, 54 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c
index 4b9892fe051..24e912f2e25 100644
--- a/arch/arm/mach-k3/r5/am62px/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62px/clk-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
- * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/clk-provider.h>
@@ -62,6 +62,17 @@ static const char * const clkout0_ctrl_out0_parents[] = {
"hsdiv4_16fft_main_2_hsdivout1_clk",
};
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
"postdiv4_16ff_main_0_hsdivout5_clk",
"hsdiv4_16fft_main_2_hsdivout2_clk",
@@ -99,8 +110,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
"board_0_cp_gemac_cpts0_rft_clk_out",
"hsdiv4_16fft_main_1_hsdivout3_clk",
"postdiv4_16ff_main_2_hsdivout6_clk",
- NULL,
- NULL,
+ "cpsw_3guss_am67_main_0_cpts_genf0",
+ "cpsw_3guss_am67_main_0_cpts_genf1",
NULL,
NULL,
NULL,
@@ -148,7 +159,12 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -200,6 +216,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+ CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
@@ -215,6 +232,24 @@ static const struct clk_data clk_list[] = {
};
static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+ DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
+ DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -239,6 +274,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
+ DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
+ DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
@@ -285,6 +322,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 54, "mshsi2c_main_0_porscl"),
DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+ DEV_CLK(157, 96, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
diff --git a/arch/arm/mach-k3/r5/am62px/dev-data.c b/arch/arm/mach-k3/r5/am62px/dev-data.c
index 3cc211ea202..63e6beb4d57 100644
--- a/arch/arm/mach-k3/r5/am62px/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62px/dev-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
- * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-dev.h"
@@ -31,11 +31,12 @@ static struct ti_lpsc soc_lpsc_list[] = {
[6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
[7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
[8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
- [9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
- [10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]),
- [11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
- [12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
- [13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+ [9] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
+ [10] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
+ [11] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[10]),
+ [12] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
+ [13] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+ [14] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[13]),
};
static struct ti_dev soc_dev_list[] = {
@@ -52,11 +53,12 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(36, &soc_lpsc_list[8]),
PSC_DEV(102, &soc_lpsc_list[8]),
PSC_DEV(146, &soc_lpsc_list[8]),
- PSC_DEV(166, &soc_lpsc_list[9]),
- PSC_DEV(135, &soc_lpsc_list[10]),
- PSC_DEV(170, &soc_lpsc_list[11]),
- PSC_DEV(177, &soc_lpsc_list[12]),
- PSC_DEV(55, &soc_lpsc_list[13]),
+ PSC_DEV(13, &soc_lpsc_list[9]),
+ PSC_DEV(166, &soc_lpsc_list[10]),
+ PSC_DEV(135, &soc_lpsc_list[11]),
+ PSC_DEV(170, &soc_lpsc_list[12]),
+ PSC_DEV(177, &soc_lpsc_list[13]),
+ PSC_DEV(55, &soc_lpsc_list[14]),
};
const struct ti_k3_pd_platdata am62px_pd_platdata = {
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 09/15] board: ti: am62px: evm: Enable cache for AM62p
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (7 preceding siblings ...)
2025-02-25 11:48 ` [PATCH v3 08/15] arm: mach-k3: am62p: Update SoC auto-gen data to enable CPSW boot Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-25 11:48 ` [PATCH v3 10/15] configs: am62p: Add configs for enabling ETHBOOT in R5SPL Chintan Vankar
` (5 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
From: Andreas Dannenberg <dannenberg@ti.com>
Enable cache for AM62p to optimize performance of CPU to access data from
memory.
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v2:
https://lore.kernel.org/r/20250219104831.2315464-11-c-vankar@ti.com/
Changes from v2 to v3:
- No changes in the patch, collected Reviewed-by tag from Alexander
Sverdlin.
board/ti/am62px/evm.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c
index 75359fa1614..0be9817064b 100644
--- a/board/ti/am62px/evm.c
+++ b/board/ti/am62px/evm.c
@@ -9,6 +9,7 @@
#include <efi_loader.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
+#include <cpu_func.h>
#include <dm/uclass.h>
#include <env.h>
#include <fdt_support.h>
@@ -54,6 +55,13 @@ int board_init(void)
return 0;
}
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+ enable_caches();
+}
+#endif
+
#if defined(CONFIG_XPL_BUILD)
void spl_perform_fixups(struct spl_image_info *spl_image)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 10/15] configs: am62p: Add configs for enabling ETHBOOT in R5SPL
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (8 preceding siblings ...)
2025-02-25 11:48 ` [PATCH v3 09/15] board: ti: am62px: evm: Enable cache for AM62p Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-25 11:48 ` [PATCH v3 11/15] configs: am62p: Enable configs required for Ethboot Chintan Vankar
` (4 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
From: Andreas Dannenberg <dannenberg@ti.com>
Add configs for enabling ETHBOOT in R5SPL, also disable not required
configs to avoid memory limitation.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v2:
https://lore.kernel.org/r/20250219104831.2315464-12-c-vankar@ti.com/
Changes from v2 to v3:
- No changes.
configs/am62px_evm_r5_ethboot_defconfig | 29 +++++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 configs/am62px_evm_r5_ethboot_defconfig
diff --git a/configs/am62px_evm_r5_ethboot_defconfig b/configs/am62px_evm_r5_ethboot_defconfig
new file mode 100644
index 00000000000..dfd944ad7c0
--- /dev/null
+++ b/configs/am62px_evm_r5_ethboot_defconfig
@@ -0,0 +1,29 @@
+#include<configs/am62px_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM62P5=y
+CONFIG_TARGET_AM62P5_R5_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk"
+CONFIG_NET=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62PX U-Boot R5 SPL"
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_SPL_SPI=n
+CONFIG_SPL_MMC=n
+CONFIG_SPL_MTD_LOAD=n
+CONFIG_SPL_NAND_SPI_SUPPORT=n
+CONFIG_SPL_DM_DEVICE_REMOVE=n
+CONFIG_DM_MTD=n
+CONFIG_MTD_SPI_NAND=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 11/15] configs: am62p: Enable configs required for Ethboot
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (9 preceding siblings ...)
2025-02-25 11:48 ` [PATCH v3 10/15] configs: am62p: Add configs for enabling ETHBOOT in R5SPL Chintan Vankar
@ 2025-02-25 11:48 ` Chintan Vankar
2025-02-25 11:49 ` [PATCH v3 12/15] arch: arm: mach-k3: r5: j722s: Update SoC autogenerated data to enable Ethernet boot Chintan Vankar
` (3 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:48 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Enable config options needed to support Ethernet boot on AM62p SK.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
Link to v2:
https://lore.kernel.org/r/20250219104831.2315464-13-c-vankar@ti.com/
Changes from v2 to v3:
- No changes,
configs/am62px_evm_a53_ethboot_defconfig | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 configs/am62px_evm_a53_ethboot_defconfig
diff --git a/configs/am62px_evm_a53_ethboot_defconfig b/configs/am62px_evm_a53_ethboot_defconfig
new file mode 100644
index 00000000000..57da40d4b2e
--- /dev/null
+++ b/configs/am62px_evm_a53_ethboot_defconfig
@@ -0,0 +1,13 @@
+#include <configs/am62px_evm_a53_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM62P5=y
+CONFIG_TARGET_AM62P5_A53_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62p5-sk"
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62PX U-Boot A53 SPL"
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 12/15] arch: arm: mach-k3: r5: j722s: Update SoC autogenerated data to enable Ethernet boot
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (10 preceding siblings ...)
2025-02-25 11:48 ` [PATCH v3 11/15] configs: am62p: Enable configs required for Ethboot Chintan Vankar
@ 2025-02-25 11:49 ` Chintan Vankar
2025-02-25 11:49 ` [PATCH v3 13/15] board: ti: j722s: evm: Enable cache for J722s Chintan Vankar
` (2 subsequent siblings)
14 siblings, 0 replies; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:49 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
In order to enable Ethernet boot using CPSW, update dev-data and clk-data
for J722s.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
This patch is newly introduced in this series.
arch/arm/mach-k3/r5/j722s/clk-data.c | 50 ++++++++++++++++++++++------
arch/arm/mach-k3/r5/j722s/dev-data.c | 34 +++++++++----------
2 files changed, 56 insertions(+), 28 deletions(-)
diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c
index b4f27af333d..238d57d0aa0 100644
--- a/arch/arm/mach-k3/r5/j722s/clk-data.c
+++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
- * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include <linux/clk-provider.h>
@@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = {
"hsdiv4_16fft_main_2_hsdivout1_clk",
};
-static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
- "postdiv4_16ff_main_0_hsdivout5_clk",
- "hsdiv4_16fft_main_2_hsdivout2_clk",
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};
static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
@@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
"board_0_cp_gemac_cpts0_rft_clk_out",
"hsdiv4_16fft_main_1_hsdivout3_clk",
"postdiv4_16ff_main_2_hsdivout6_clk",
- NULL,
- NULL,
+ "cpsw_3guss_am67_main_0_cpts_genf0",
+ "cpsw_3guss_am67_main_0_cpts_genf1",
NULL,
NULL,
NULL,
@@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
- CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
+ CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
@@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = {
};
static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+ DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
+ DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
- DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
- DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
- DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
- DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
+ DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
@@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(157, 74, "mshsi2c_main_0_porscl"),
DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+ DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c
index 59176c98999..d6832266884 100644
--- a/arch/arm/mach-k3/r5/j722s/dev-data.c
+++ b/arch/arm/mach-k3/r5/j722s/dev-data.c
@@ -5,7 +5,7 @@
* This file is auto generated. Please do not hand edit and report any issues
* to Bryan Brattlof <bb@ti.com>.
*
- * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-dev.h"
@@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = {
static struct ti_lpsc soc_lpsc_list[] = {
[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
- [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
- [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
- [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
- [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
- [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
- [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
- [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
- [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]),
+ [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
+ [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
+ [3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+ [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+ [5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+ [6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+ [7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+ [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]),
[9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
- [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
+ [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]),
[11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]),
[12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
};
@@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(61, &soc_lpsc_list[0]),
PSC_DEV(178, &soc_lpsc_list[1]),
PSC_DEV(179, &soc_lpsc_list[2]),
- PSC_DEV(57, &soc_lpsc_list[3]),
- PSC_DEV(58, &soc_lpsc_list[4]),
- PSC_DEV(161, &soc_lpsc_list[5]),
- PSC_DEV(75, &soc_lpsc_list[6]),
- PSC_DEV(36, &soc_lpsc_list[7]),
- PSC_DEV(102, &soc_lpsc_list[7]),
- PSC_DEV(146, &soc_lpsc_list[7]),
+ PSC_DEV(58, &soc_lpsc_list[3]),
+ PSC_DEV(161, &soc_lpsc_list[4]),
+ PSC_DEV(75, &soc_lpsc_list[5]),
+ PSC_DEV(36, &soc_lpsc_list[6]),
+ PSC_DEV(102, &soc_lpsc_list[6]),
+ PSC_DEV(146, &soc_lpsc_list[6]),
+ PSC_DEV(13, &soc_lpsc_list[7]),
PSC_DEV(166, &soc_lpsc_list[8]),
PSC_DEV(135, &soc_lpsc_list[9]),
PSC_DEV(170, &soc_lpsc_list[10]),
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 13/15] board: ti: j722s: evm: Enable cache for J722s
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (11 preceding siblings ...)
2025-02-25 11:49 ` [PATCH v3 12/15] arch: arm: mach-k3: r5: j722s: Update SoC autogenerated data to enable Ethernet boot Chintan Vankar
@ 2025-02-25 11:49 ` Chintan Vankar
2025-02-25 15:43 ` Sverdlin, Alexander
2025-02-25 11:49 ` [PATCH v3 14/15] configs: j722s_evm_r5: Add configs to enable Ethboot in R5SPL Chintan Vankar
2025-02-25 11:49 ` [PATCH v3 15/15] configs: j722s_evm_a53: Enable configs required for Ethernet boot Chintan Vankar
14 siblings, 1 reply; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:49 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Enable cache for J722s to optimize performance of CPU to access data from
memory.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
This patch is newly introduced in this series.
board/ti/j722s/evm.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c
index f085ecfd37e..793c028b53c 100644
--- a/board/ti/j722s/evm.c
+++ b/board/ti/j722s/evm.c
@@ -8,6 +8,7 @@
#include <asm/arch/hardware.h>
#include <asm/io.h>
+#include <cpu_func.h>
#include <dm/uclass.h>
#include <env.h>
#include <fdt_support.h>
@@ -20,6 +21,13 @@ int board_init(void)
return 0;
}
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+ enable_caches();
+}
+#endif
+
#if defined(CONFIG_XPL_BUILD)
void spl_perform_fixups(struct spl_image_info *spl_image)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 13/15] board: ti: j722s: evm: Enable cache for J722s
2025-02-25 11:49 ` [PATCH v3 13/15] board: ti: j722s: evm: Enable cache for J722s Chintan Vankar
@ 2025-02-25 15:43 ` Sverdlin, Alexander
0 siblings, 0 replies; 22+ messages in thread
From: Sverdlin, Alexander @ 2025-02-25 15:43 UTC (permalink / raw)
To: joao.goncalves@toradex.com, joe.hershberger@ni.com,
c-vankar@ti.com, bb@ti.com, mwalle@kernel.org, dannenberg@ti.com,
n-francis@ti.com, trini@konsulko.com, s-k6@ti.com, afd@ti.com,
j-choudhary@ti.com, hnagalla@ti.com, m-chawdhry@ti.com,
danishanwar@ti.com, j-humphreys@ti.com, w.egorov@phytec.de,
ilias.apalodimas@linaro.org, kishon@ti.com, vaishnav.a@ti.com,
matthias.schiffer@ew.tq-group.com, rogerq@kernel.org,
rfried.dev@gmail.com, vigneshr@ti.com
Cc: s-vadapalli@ti.com, u-boot@lists.denx.de
On Tue, 2025-02-25 at 17:19 +0530, Chintan Vankar wrote:
> Enable cache for J722s to optimize performance of CPU to access data from
> memory.
>
> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
> ---
>
> This patch is newly introduced in this series.
>
> board/ti/j722s/evm.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c
> index f085ecfd37e..793c028b53c 100644
> --- a/board/ti/j722s/evm.c
> +++ b/board/ti/j722s/evm.c
> @@ -8,6 +8,7 @@
>
> #include <asm/arch/hardware.h>
> #include <asm/io.h>
> +#include <cpu_func.h>
> #include <dm/uclass.h>
> #include <env.h>
> #include <fdt_support.h>
> @@ -20,6 +21,13 @@ int board_init(void)
> return 0;
> }
>
> +#if IS_ENABLED(CONFIG_SPL_BUILD)
> +void spl_board_init(void)
> +{
> + enable_caches();
> +}
> +#endif
> +
> #if defined(CONFIG_XPL_BUILD)
> void spl_perform_fixups(struct spl_image_info *spl_image)
> {
--
Alexander Sverdlin
Siemens AG
www.siemens.com
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 14/15] configs: j722s_evm_r5: Add configs to enable Ethboot in R5SPL
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (12 preceding siblings ...)
2025-02-25 11:49 ` [PATCH v3 13/15] board: ti: j722s: evm: Enable cache for J722s Chintan Vankar
@ 2025-02-25 11:49 ` Chintan Vankar
2025-02-25 11:49 ` [PATCH v3 15/15] configs: j722s_evm_a53: Enable configs required for Ethernet boot Chintan Vankar
14 siblings, 0 replies; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:49 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Add configs to enable Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
This patch is newly introduced in this series.
configs/j722s_evm_r5_ethboot_defconfig | 30 ++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 configs/j722s_evm_r5_ethboot_defconfig
diff --git a/configs/j722s_evm_r5_ethboot_defconfig b/configs/j722s_evm_r5_ethboot_defconfig
new file mode 100644
index 00000000000..fd58485bff2
--- /dev/null
+++ b/configs/j722s_evm_r5_ethboot_defconfig
@@ -0,0 +1,30 @@
+#include<configs/j722s_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_R5_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j722s-r5-evm"
+CONFIG_NET=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="J722S U-Boot R5 SPL"
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_SPL_MMC=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_MTD_LOAD=n
+CONFIG_SPL_NAND_SPI_SUPPORT=n
+CONFIG_SPL_DM_DEVICE_REMOVE=n
+CONFIG_DM_MTD=n
+CONFIG_MTD_SPI_NAND=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 15/15] configs: j722s_evm_a53: Enable configs required for Ethernet boot
2025-02-25 11:48 [PATCH v3 00/15] Add support for Ethboot for AM68-SK, AM62p-SK Chintan Vankar
` (13 preceding siblings ...)
2025-02-25 11:49 ` [PATCH v3 14/15] configs: j722s_evm_r5: Add configs to enable Ethboot in R5SPL Chintan Vankar
@ 2025-02-25 11:49 ` Chintan Vankar
14 siblings, 0 replies; 22+ messages in thread
From: Chintan Vankar @ 2025-02-25 11:49 UTC (permalink / raw)
To: Michael Walle, Matthias Schiffer, MD Danish Anwar, Roger Quadros,
Hari Nagalla, Manorit Chawdhry, Jonathan Humphreys,
Santhosh Kumar K, Ilias Apalodimas, Neha Malcom Francis,
Andreas Dannenberg, Andrew Davis, Alexander Sverdlin,
Joao Paulo Goncalves, Kishon Vijay Abraham I, Chintan Vankar,
Wadim Egorov, Ramon Fried, Joe Hershberger, Jayesh Choudhary,
Vaishnav Achath, Bryan Brattlof, Vignesh Raghavendra, Tom Rini
Cc: s-vadapalli, u-boot
Enable configs required to support Ethernet boot for J722s.
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---
This patch is newly introduced in this series.
configs/j722s_evm_a53_ethboot_defconfig | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 configs/j722s_evm_a53_ethboot_defconfig
diff --git a/configs/j722s_evm_a53_ethboot_defconfig b/configs/j722s_evm_a53_ethboot_defconfig
new file mode 100644
index 00000000000..a5a2a15849c
--- /dev/null
+++ b/configs/j722s_evm_a53_ethboot_defconfig
@@ -0,0 +1,13 @@
+#include <configs/j722s_evm_a53_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_A53_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j722s-evm"
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="J722S U-Boot A53 SPL"
--
2.34.1
^ permalink raw reply related [flat|nested] 22+ messages in thread