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From: "Jingoo Han" <jingoohan1@gmail.com>
To: "'Jisheng Zhang'" <jszhang@marvell.com>,
	<Joao.Pinto@synopsys.com>, <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
Date: Tue, 18 Jul 2017 23:25:24 -0400	[thread overview]
Message-ID: <000001d3003e$a9ad0fe0$fd072fa0$@gmail.com> (raw)
In-Reply-To: <20170718064821.3668-1-jszhang@marvell.com>

On Tuesday, July 18, 2017 2:48 AM, Jisheng Zhang wrote:
> 
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable bit.
> 
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>

Acked-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han


> ---
> Since v1:
>  - Add Joao's Ack
>  - Fix typo in commit msg, thank Jingoo
> 
>  drivers/pci/dwc/pcie-designware.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-
> designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> int index, int type,
>  	 */
>  	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> {
>  		val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> -		if (val == PCIE_ATU_ENABLE)
> +		if (val & PCIE_ATU_ENABLE)
>  			return;
> 
>  		usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> --
> 2.13.2



_______________________________________________
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WARNING: multiple messages have this Message-ID (diff)
From: jingoohan1@gmail.com (Jingoo Han)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
Date: Tue, 18 Jul 2017 23:25:24 -0400	[thread overview]
Message-ID: <000001d3003e$a9ad0fe0$fd072fa0$@gmail.com> (raw)
In-Reply-To: <20170718064821.3668-1-jszhang@marvell.com>

On Tuesday, July 18, 2017 2:48 AM, Jisheng Zhang wrote:
> 
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable bit.
> 
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>

Acked-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han


> ---
> Since v1:
>  - Add Joao's Ack
>  - Fix typo in commit msg, thank Jingoo
> 
>  drivers/pci/dwc/pcie-designware.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-
> designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> int index, int type,
>  	 */
>  	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> {
>  		val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> -		if (val == PCIE_ATU_ENABLE)
> +		if (val & PCIE_ATU_ENABLE)
>  			return;
> 
>  		usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> --
> 2.13.2

WARNING: multiple messages have this Message-ID (diff)
From: "Jingoo Han" <jingoohan1@gmail.com>
To: "'Jisheng Zhang'" <jszhang@marvell.com>,
	<Joao.Pinto@synopsys.com>, <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
Date: Tue, 18 Jul 2017 23:25:24 -0400	[thread overview]
Message-ID: <000001d3003e$a9ad0fe0$fd072fa0$@gmail.com> (raw)
In-Reply-To: <20170718064821.3668-1-jszhang@marvell.com>

On Tuesday, July 18, 2017 2:48 AM, Jisheng Zhang wrote:
> 
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable bit.
> 
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>

Acked-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han


> ---
> Since v1:
>  - Add Joao's Ack
>  - Fix typo in commit msg, thank Jingoo
> 
>  drivers/pci/dwc/pcie-designware.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-
> designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> int index, int type,
>  	 */
>  	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> {
>  		val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> -		if (val == PCIE_ATU_ENABLE)
> +		if (val & PCIE_ATU_ENABLE)
>  			return;
> 
>  		usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> --
> 2.13.2

  reply	other threads:[~2017-07-19  3:25 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-18  6:48 [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not Jisheng Zhang
2017-07-18  6:48 ` Jisheng Zhang
2017-07-18  6:48 ` Jisheng Zhang
2017-07-19  3:25 ` Jingoo Han [this message]
2017-07-19  3:25   ` Jingoo Han
2017-07-19  3:25   ` Jingoo Han
2017-08-02 21:52 ` Bjorn Helgaas
2017-08-02 21:52   ` Bjorn Helgaas
2017-08-02 21:52   ` Bjorn Helgaas

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