* [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-18 6:48 ` Jisheng Zhang
0 siblings, 0 replies; 9+ messages in thread
From: Jisheng Zhang @ 2017-07-18 6:48 UTC (permalink / raw)
To: jingoohan1, Joao.Pinto, bhelgaas
Cc: Jisheng Zhang, linux-pci, linux-kernel, linux-arm-kernel
The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
may also be set. To check whether the ATU is enabled or not, we should
test the enable bit.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
---
Since v1:
- Add Joao's Ack
- Fix typo in commit msg, thank Jingoo
drivers/pci/dwc/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 0e03af279259..6bf0b409050a 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
- if (val == PCIE_ATU_ENABLE)
+ if (val & PCIE_ATU_ENABLE)
return;
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
--
2.13.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-18 6:48 ` Jisheng Zhang
0 siblings, 0 replies; 9+ messages in thread
From: Jisheng Zhang @ 2017-07-18 6:48 UTC (permalink / raw)
To: linux-arm-kernel
The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
may also be set. To check whether the ATU is enabled or not, we should
test the enable bit.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
---
Since v1:
- Add Joao's Ack
- Fix typo in commit msg, thank Jingoo
drivers/pci/dwc/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 0e03af279259..6bf0b409050a 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
- if (val == PCIE_ATU_ENABLE)
+ if (val & PCIE_ATU_ENABLE)
return;
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
--
2.13.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-18 6:48 ` Jisheng Zhang
0 siblings, 0 replies; 9+ messages in thread
From: Jisheng Zhang @ 2017-07-18 6:48 UTC (permalink / raw)
To: jingoohan1, Joao.Pinto, bhelgaas
Cc: linux-pci, linux-kernel, linux-arm-kernel, Jisheng Zhang
The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
may also be set. To check whether the ATU is enabled or not, we should
test the enable bit.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
---
Since v1:
- Add Joao's Ack
- Fix typo in commit msg, thank Jingoo
drivers/pci/dwc/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 0e03af279259..6bf0b409050a 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
*/
for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
- if (val == PCIE_ATU_ENABLE)
+ if (val & PCIE_ATU_ENABLE)
return;
usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
--
2.13.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
2017-07-18 6:48 ` Jisheng Zhang
(?)
@ 2017-07-19 3:25 ` Jingoo Han
-1 siblings, 0 replies; 9+ messages in thread
From: Jingoo Han @ 2017-07-19 3:25 UTC (permalink / raw)
To: 'Jisheng Zhang', Joao.Pinto, bhelgaas
Cc: linux-pci, linux-kernel, linux-arm-kernel
On Tuesday, July 18, 2017 2:48 AM, Jisheng Zhang wrote:
>
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable bit.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Best regards,
Jingoo Han
> ---
> Since v1:
> - Add Joao's Ack
> - Fix typo in commit msg, thank Jingoo
>
> drivers/pci/dwc/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-
> designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> int index, int type,
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> {
> val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> - if (val == PCIE_ATU_ENABLE)
> + if (val & PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> --
> 2.13.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-19 3:25 ` Jingoo Han
0 siblings, 0 replies; 9+ messages in thread
From: Jingoo Han @ 2017-07-19 3:25 UTC (permalink / raw)
To: linux-arm-kernel
On Tuesday, July 18, 2017 2:48 AM, Jisheng Zhang wrote:
>
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable bit.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Best regards,
Jingoo Han
> ---
> Since v1:
> - Add Joao's Ack
> - Fix typo in commit msg, thank Jingoo
>
> drivers/pci/dwc/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-
> designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> int index, int type,
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> {
> val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> - if (val == PCIE_ATU_ENABLE)
> + if (val & PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> --
> 2.13.2
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-07-19 3:25 ` Jingoo Han
0 siblings, 0 replies; 9+ messages in thread
From: Jingoo Han @ 2017-07-19 3:25 UTC (permalink / raw)
To: 'Jisheng Zhang', Joao.Pinto, bhelgaas
Cc: linux-pci, linux-kernel, linux-arm-kernel
On Tuesday, July 18, 2017 2:48 AM, Jisheng Zhang wrote:
>
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable bit.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Best regards,
Jingoo Han
> ---
> Since v1:
> - Add Joao's Ack
> - Fix typo in commit msg, thank Jingoo
>
> drivers/pci/dwc/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-
> designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
> int index, int type,
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++)
> {
> val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> - if (val == PCIE_ATU_ENABLE)
> + if (val & PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> --
> 2.13.2
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
2017-07-18 6:48 ` Jisheng Zhang
(?)
@ 2017-08-02 21:52 ` Bjorn Helgaas
-1 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2017-08-02 21:52 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Joao.Pinto, jingoohan1, linux-kernel, linux-pci, bhelgaas,
linux-arm-kernel
On Tue, Jul 18, 2017 at 02:48:21PM +0800, Jisheng Zhang wrote:
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable bit.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
Applied with Jingoo's ack to pci/host-designware for v4.14, thanks!
> ---
> Since v1:
> - Add Joao's Ack
> - Fix typo in commit msg, thank Jingoo
>
> drivers/pci/dwc/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> - if (val == PCIE_ATU_ENABLE)
> + if (val & PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> --
> 2.13.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-08-02 21:52 ` Bjorn Helgaas
0 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2017-08-02 21:52 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 18, 2017 at 02:48:21PM +0800, Jisheng Zhang wrote:
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable bit.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
Applied with Jingoo's ack to pci/host-designware for v4.14, thanks!
> ---
> Since v1:
> - Add Joao's Ack
> - Fix typo in commit msg, thank Jingoo
>
> drivers/pci/dwc/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> - if (val == PCIE_ATU_ENABLE)
> + if (val & PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> --
> 2.13.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not
@ 2017-08-02 21:52 ` Bjorn Helgaas
0 siblings, 0 replies; 9+ messages in thread
From: Bjorn Helgaas @ 2017-08-02 21:52 UTC (permalink / raw)
To: Jisheng Zhang
Cc: jingoohan1, Joao.Pinto, bhelgaas, linux-pci, linux-kernel,
linux-arm-kernel
On Tue, Jul 18, 2017 at 02:48:21PM +0800, Jisheng Zhang wrote:
> The ATU CTRL2 register is 32 bit, besides the enable bit, other bits
> may also be set. To check whether the ATU is enabled or not, we should
> test the enable bit.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
Applied with Jingoo's ack to pci/host-designware for v4.14, thanks!
> ---
> Since v1:
> - Add Joao's Ack
> - Fix typo in commit msg, thank Jingoo
>
> drivers/pci/dwc/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
> index 0e03af279259..6bf0b409050a 100644
> --- a/drivers/pci/dwc/pcie-designware.c
> +++ b/drivers/pci/dwc/pcie-designware.c
> @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
> */
> for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
> val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
> - if (val == PCIE_ATU_ENABLE)
> + if (val & PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> --
> 2.13.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-08-02 21:52 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-07-18 6:48 [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not Jisheng Zhang
2017-07-18 6:48 ` Jisheng Zhang
2017-07-18 6:48 ` Jisheng Zhang
2017-07-19 3:25 ` Jingoo Han
2017-07-19 3:25 ` Jingoo Han
2017-07-19 3:25 ` Jingoo Han
2017-08-02 21:52 ` Bjorn Helgaas
2017-08-02 21:52 ` Bjorn Helgaas
2017-08-02 21:52 ` Bjorn Helgaas
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