From: "Jiawen Wu" <jiawenwu@trustnetic.com>
To: "'Russell King \(Oracle\)'" <linux@armlinux.org.uk>
Cc: "'Simon Horman'" <simon.horman@corigine.com>, <kabel@kernel.org>,
<andrew@lunn.ch>, <hkallweit1@gmail.com>, <davem@davemloft.net>,
<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
<netdev@vger.kernel.org>
Subject: RE: [PATCH net] net: phy: marvell10g: fix 88x3310 power up
Date: Wed, 19 Jul 2023 15:57:30 +0800 [thread overview]
Message-ID: <01b401d9ba16$aacf75f0$006e61d0$@trustnetic.com> (raw)
In-Reply-To: <ZLeHyzsRqxAj4ZGO@shell.armlinux.org.uk>
On Wednesday, July 19, 2023 2:51 PM, Russell King (Oracle) wrote:
> On Wed, Jul 19, 2023 at 10:29:38AM +0800, Jiawen Wu wrote:
> > [59697.591809] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1, regnum=6, val=c000
> > [59697.592811] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1, regnum=5, val=9a
> > [59697.593814] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1, regnum=2, val=2b
> > [59697.594817] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1, regnum=3, val=9ab
> > [59697.595811] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=3, regnum=2, val=2b
> > [59697.596811] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=3, regnum=3, val=9ab
> > [59697.597811] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=4, regnum=2, val=141
> > [59697.598809] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=4, regnum=3, val=dab
> > [59697.599809] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=7, regnum=2, val=2b
> > [59697.600810] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=7, regnum=3, val=9ab
> > [59697.601815] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1e, regnum=8, val=0
> > [59697.602930] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1f, regnum=8, val=fffe
> > [59697.608811] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=3, regnum=d00d, val=680b
> > [59697.609823] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1, regnum=c050, val=7e
> > [59697.610814] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1, regnum=c011, val=2
> > [59697.611817] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1, regnum=c012, val=200
> > [59697.611820] mv88x3310 txgbe-400:00: Firmware version 0.2.2.0
> > [59697.612817] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1f, regnum=f001, val=803
>
> So here we can see the PHY is already in low-power mode, so presumably
> it's configured to do that from power-up?
>
> > [59697.612820] txgbe 0000:04:00.0: [W]phy_addr=0, devnum=1f, regnum=f08c, val=9600
> > [59697.613819] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1f, regnum=f08a, val=cd9a
> > [59697.613822] txgbe 0000:04:00.0: [W]phy_addr=0, devnum=1f, regnum=f08a, val=d9a
> > [59697.614818] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=7, regnum=1, val=9ab
> > [59697.615816] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1, regnum=8, val=9701
> > [59697.616817] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1, regnum=b, val=1a4
> > [59697.617814] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=3, regnum=14, val=e
> > [59697.618809] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1, regnum=15, val=3
> > [59697.619811] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=7, regnum=3c, val=0
> > [59697.619831] mv88x3310 txgbe-400:00: attached PHY driver (mii_bus:phy_addr=txgbe-400:00, irq=POLL)
>
> The following is where we attempt to power up the PHY:
>
> > [59697.830169] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1f, regnum=f001, val=803
> > [59697.830179] txgbe 0000:04:00.0: [W]phy_addr=0, devnum=1f, regnum=f001, val=3
>
> The above is our attempt to clear the low power bit.
>
> > [59697.830926] txgbe 0000:04:00.0: [R]phy_addr=0, devnum=1f, regnum=f001, val=803
>
> According to this read though (which is in get_mactype), the write
> didn't take effect.
>
> If you place a delay of 1ms after phy_clear_bits_mmd() in
> mv3310_power_up(), does it then work?
Yes, I just experimented, it works well.
next prev parent reply other threads:[~2023-07-19 7:59 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-12 6:26 [PATCH net] net: phy: marvell10g: fix 88x3310 power up Jiawen Wu
2023-07-13 10:26 ` Simon Horman
2023-07-13 10:35 ` Russell King (Oracle)
2023-07-13 10:45 ` Simon Horman
2023-07-13 10:53 ` Russell King (Oracle)
2023-07-13 11:30 ` Jiawen Wu
2023-07-13 11:41 ` Russell King (Oracle)
2023-07-13 11:50 ` Jiawen Wu
2023-07-17 10:51 ` Jiawen Wu
2023-07-17 12:22 ` Russell King (Oracle)
2023-07-18 9:12 ` Jiawen Wu
2023-07-18 9:49 ` Russell King (Oracle)
2023-07-18 9:58 ` Jiawen Wu
2023-07-18 11:47 ` Russell King (Oracle)
2023-07-19 2:29 ` Jiawen Wu
2023-07-19 3:53 ` Jiawen Wu
2023-07-19 6:50 ` Russell King (Oracle)
2023-07-19 7:57 ` Jiawen Wu [this message]
2023-07-19 8:27 ` Russell King (Oracle)
2023-07-19 8:38 ` Jiawen Wu
2023-07-19 8:52 ` Russell King (Oracle)
2023-07-13 12:18 ` Simon Horman
2023-07-13 10:46 ` Russell King (Oracle)
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