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From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Jiawen Wu <jiawenwu@trustnetic.com>
Cc: kabel@kernel.org, andrew@lunn.ch, hkallweit1@gmail.com,
	davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
	pabeni@redhat.com, netdev@vger.kernel.org
Subject: Re: [PATCH net] net: phy: marvell10g: fix 88x3310 power up
Date: Thu, 13 Jul 2023 11:46:08 +0100	[thread overview]
Message-ID: <ZK/V8NyFw+SWUF3V@shell.armlinux.org.uk> (raw)
In-Reply-To: <20230712062634.21288-1-jiawenwu@trustnetic.com>

On Wed, Jul 12, 2023 at 02:26:34PM +0800, Jiawen Wu wrote:
> Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY,
> it sometimes does not take effect immediately. This will cause
> mv3310_reset() to time out, which will fail the config initialization.
> So add to poll PHY power up.

Can you check how long it takes for the PWRDOWN bit to clear? The
datasheet says that hardware reset or a MDIO write to this register
can clear this bit. It doesn't say that it needs to be polled or
that it takes time to clear before reset is possible.

So, I think a little more explanation and investigation would be
useful.

Thanks.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

      parent reply	other threads:[~2023-07-13 10:46 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-12  6:26 [PATCH net] net: phy: marvell10g: fix 88x3310 power up Jiawen Wu
2023-07-13 10:26 ` Simon Horman
2023-07-13 10:35   ` Russell King (Oracle)
2023-07-13 10:45     ` Simon Horman
2023-07-13 10:53       ` Russell King (Oracle)
2023-07-13 11:30         ` Jiawen Wu
2023-07-13 11:41           ` Russell King (Oracle)
2023-07-13 11:50             ` Jiawen Wu
2023-07-17 10:51               ` Jiawen Wu
2023-07-17 12:22                 ` Russell King (Oracle)
2023-07-18  9:12                   ` Jiawen Wu
2023-07-18  9:49                     ` Russell King (Oracle)
2023-07-18  9:58                       ` Jiawen Wu
2023-07-18 11:47                         ` Russell King (Oracle)
2023-07-19  2:29                           ` Jiawen Wu
2023-07-19  3:53                             ` Jiawen Wu
2023-07-19  6:50                             ` Russell King (Oracle)
2023-07-19  7:57                               ` Jiawen Wu
2023-07-19  8:27                                 ` Russell King (Oracle)
2023-07-19  8:38                                   ` Jiawen Wu
2023-07-19  8:52                                     ` Russell King (Oracle)
2023-07-13 12:18         ` Simon Horman
2023-07-13 10:46 ` Russell King (Oracle) [this message]

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