* [PATCH v2 0/6] Introduce extension implied rules
@ 2024-06-16 2:46 frank.chang
2024-06-16 2:46 ` [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition frank.chang
` (5 more replies)
0 siblings, 6 replies; 15+ messages in thread
From: frank.chang @ 2024-06-16 2:46 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang
From: Frank Chang <frank.chang@sifive.com>
Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the
implied extensions. This also eliminates the old-fashioned ordering
requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc.,
removing the need to check the implied rules of Zvksg before Zvks.
The idea [1] and the implied rules [2] are referenced from LLVM.
[1] https://github.com/llvm/llvm-project/blob/main/llvm/lib/TargetParser/RISCVISAInfo.cpp#L875
[2] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVFeatures.td
Changelog:
v2:
- Remove enabled bitmask from user-mode QEMU as there's no good way
(e.g. mhartid) to distinguish the SMP cores in user-mode QEMU.
- Use qatomic API to access the enabled bitmask to prevent the
potential enabled bit from being cleared by another hart.
Frank Chang (6):
target/riscv: Introduce extension implied rules definition
target/riscv: Introduce extension implied rule helpers
target/riscv: Add MISA implied rules
target/riscv: Add standard extension implied rules
target/riscv: Add Zc extension implied rule
target/riscv: Remove extension auto-update check statements
target/riscv/cpu.c | 396 +++++++++++++++++++++++++++++++++++++
target/riscv/cpu.h | 25 +++
target/riscv/tcg/tcg-cpu.c | 244 ++++++++++++-----------
3 files changed, 546 insertions(+), 119 deletions(-)
--
2.43.2
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition
2024-06-16 2:46 [PATCH v2 0/6] Introduce extension implied rules frank.chang
@ 2024-06-16 2:46 ` frank.chang
2024-06-20 19:51 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers frank.chang
` (4 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: frank.chang @ 2024-06-16 2:46 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang, Jerry Zhang Jian, Max Chou
From: Frank Chang <frank.chang@sifive.com>
RISCVCPUImpliedExtsRule is created to store the implied rules.
'is_misa' flag is used to distinguish whether the rule is derived
from the MISA or other extensions.
'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
the offset of the extension defined in RISCVCPUConfig. 'ext' will also
serve as the key of the hash tables to look up the rule in the following
commit.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 8 ++++++++
target/riscv/cpu.h | 25 +++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4760cb2cc1..bacbb32120 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2250,6 +2250,14 @@ RISCVCPUProfile *riscv_profiles[] = {
NULL,
};
+RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
+ NULL
+};
+
+RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
+ NULL
+};
+
static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 90b8f1b08f..6b31731fa8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -124,6 +124,31 @@ typedef enum {
EXT_STATUS_DIRTY,
} RISCVExtStatus;
+typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule;
+
+struct riscv_cpu_implied_exts_rule {
+#ifndef CONFIG_USER_ONLY
+ /*
+ * Bitmask indicates the rule enabled status for the harts.
+ * This enhancement is only available in system-mode QEMU,
+ * as we don't have a good way (e.g. mhartid) to distinguish
+ * the SMP cores in user-mode QEMU.
+ */
+ uint64_t enabled;
+#endif
+ /* True if this is a MISA implied rule. */
+ bool is_misa;
+ /* ext is MISA bit if is_misa flag is true, else extension offset. */
+ const uint32_t ext;
+ const uint32_t implied_misas;
+ const uint32_t implied_exts[];
+};
+
+extern RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[];
+extern RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[];
+
+#define RISCV_IMPLIED_EXTS_RULE_END -1
+
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
--
2.43.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers
2024-06-16 2:46 [PATCH v2 0/6] Introduce extension implied rules frank.chang
2024-06-16 2:46 ` [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition frank.chang
@ 2024-06-16 2:46 ` frank.chang
2024-06-20 19:52 ` Daniel Henrique Barboza
2024-06-21 4:14 ` Alistair Francis
2024-06-16 2:46 ` [PATCH v2 3/6] target/riscv: Add MISA implied rules frank.chang
` (3 subsequent siblings)
5 siblings, 2 replies; 15+ messages in thread
From: frank.chang @ 2024-06-16 2:46 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang, Jerry Zhang Jian, Max Chou
From: Frank Chang <frank.chang@sifive.com>
Introduce helpers to enable the extensions based on the implied rules.
The implied extensions are enabled recursively, so we don't have to
expand all of them manually. This also eliminates the old-fashioned
ordering requirement. For example, Zvksg implies Zvks, Zvks implies
Zvksed, etc., removing the need to check the implied rules of Zvksg
before Zvks.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
---
target/riscv/tcg/tcg-cpu.c | 91 ++++++++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index eb6f7b9d12..f8d6371764 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -36,6 +36,9 @@
static GHashTable *multi_ext_user_opts;
static GHashTable *misa_ext_user_opts;
+static GHashTable *misa_implied_rules;
+static GHashTable *ext_implied_rules;
+
static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
{
return g_hash_table_contains(multi_ext_user_opts,
@@ -836,11 +839,97 @@ static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
}
}
+static void riscv_cpu_init_implied_exts_rules(void)
+{
+ RISCVCPUImpliedExtsRule *rule;
+ int i;
+
+ for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
+ g_hash_table_insert(misa_implied_rules, GUINT_TO_POINTER(rule->ext),
+ (gpointer)rule);
+ }
+
+ for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
+ g_hash_table_insert(ext_implied_rules, GUINT_TO_POINTER(rule->ext),
+ (gpointer)rule);
+ }
+}
+
+static void cpu_enable_implied_rule(RISCVCPU *cpu,
+ RISCVCPUImpliedExtsRule *rule)
+{
+ CPURISCVState *env = &cpu->env;
+ RISCVCPUImpliedExtsRule *ir;
+ bool enabled = false;
+ int i;
+
+#ifndef CONFIG_USER_ONLY
+ enabled = qatomic_read(&rule->enabled) & BIT_ULL(cpu->env.mhartid);
+#endif
+
+ if (!enabled) {
+ /* Enable the implied MISAs. */
+ if (rule->implied_misas) {
+ riscv_cpu_set_misa_ext(env, env->misa_ext | rule->implied_misas);
+
+ for (i = 0; misa_bits[i] != 0; i++) {
+ if (rule->implied_misas & misa_bits[i]) {
+ ir = g_hash_table_lookup(misa_implied_rules,
+ GUINT_TO_POINTER(misa_bits[i]));
+
+ if (ir) {
+ cpu_enable_implied_rule(cpu, ir);
+ }
+ }
+ }
+ }
+
+ /* Enable the implied extensions. */
+ for (i = 0; rule->implied_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) {
+ cpu_cfg_ext_auto_update(cpu, rule->implied_exts[i], true);
+
+ ir = g_hash_table_lookup(ext_implied_rules,
+ GUINT_TO_POINTER(rule->implied_exts[i]));
+
+ if (ir) {
+ cpu_enable_implied_rule(cpu, ir);
+ }
+ }
+
+#ifndef CONFIG_USER_ONLY
+ qatomic_or(&rule->enabled, BIT_ULL(cpu->env.mhartid));
+#endif
+ }
+}
+
+static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
+{
+ RISCVCPUImpliedExtsRule *rule;
+ int i;
+
+ /* Enable the implied MISAs. */
+ for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
+ if (riscv_has_ext(&cpu->env, rule->ext)) {
+ cpu_enable_implied_rule(cpu, rule);
+ }
+ }
+
+ /* Enable the implied extensions. */
+ for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
+ if (isa_ext_is_enabled(cpu, rule->ext)) {
+ cpu_enable_implied_rule(cpu, rule);
+ }
+ }
+}
+
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
{
CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
+ riscv_cpu_init_implied_exts_rules();
+ riscv_cpu_enable_implied_rules(cpu);
+
riscv_cpu_validate_misa_priv(env, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
@@ -1346,6 +1435,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs)
misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
+ misa_implied_rules = g_hash_table_new(NULL, g_direct_equal);
+ ext_implied_rules = g_hash_table_new(NULL, g_direct_equal);
riscv_cpu_add_user_properties(obj);
if (riscv_cpu_has_max_extensions(obj)) {
--
2.43.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 3/6] target/riscv: Add MISA implied rules
2024-06-16 2:46 [PATCH v2 0/6] Introduce extension implied rules frank.chang
2024-06-16 2:46 ` [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition frank.chang
2024-06-16 2:46 ` [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers frank.chang
@ 2024-06-16 2:46 ` frank.chang
2024-06-20 19:53 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 4/6] target/riscv: Add standard extension " frank.chang
` (2 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: frank.chang @ 2024-06-16 2:46 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang, Jerry Zhang Jian, Max Chou
From: Frank Chang <frank.chang@sifive.com>
Add MISA extension implied rules to enable the implied extensions
of MISA recursively.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bacbb32120..d09b5e9e62 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2250,8 +2250,56 @@ RISCVCPUProfile *riscv_profiles[] = {
NULL,
};
+static RISCVCPUImpliedExtsRule RVA_IMPLIED = {
+ .is_misa = true,
+ .ext = RVA,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule RVD_IMPLIED = {
+ .is_misa = true,
+ .ext = RVD,
+ .implied_misas = RVF,
+ .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
+};
+
+static RISCVCPUImpliedExtsRule RVF_IMPLIED = {
+ .is_misa = true,
+ .ext = RVF,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule RVM_IMPLIED = {
+ .is_misa = true,
+ .ext = RVM,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zmmul),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
+ .is_misa = true,
+ .ext = RVV,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve64d),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
- NULL
+ &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
+ &RVM_IMPLIED, &RVV_IMPLIED, NULL
};
RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
--
2.43.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 4/6] target/riscv: Add standard extension implied rules
2024-06-16 2:46 [PATCH v2 0/6] Introduce extension implied rules frank.chang
` (2 preceding siblings ...)
2024-06-16 2:46 ` [PATCH v2 3/6] target/riscv: Add MISA implied rules frank.chang
@ 2024-06-16 2:46 ` frank.chang
2024-06-20 19:53 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 5/6] target/riscv: Add Zc extension implied rule frank.chang
2024-06-16 2:46 ` [PATCH v2 6/6] target/riscv: Remove extension auto-update check statements frank.chang
5 siblings, 1 reply; 15+ messages in thread
From: frank.chang @ 2024-06-16 2:46 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang, Jerry Zhang Jian, Max Chou
From: Frank Chang <frank.chang@sifive.com>
Add standard extension implied rules to enable the implied extensions of
the standard extension recursively.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 340 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 340 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d09b5e9e62..1a3b1387e1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2297,12 +2297,352 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
},
};
+static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zcb),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zca),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZCD_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zcd),
+ .implied_misas = RVD,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zca),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZCE_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zce),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zcb), CPU_CFG_OFFSET(ext_zcmp),
+ CPU_CFG_OFFSET(ext_zcmt),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZCF_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zcf),
+ .implied_misas = RVF,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zca),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZCMP_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zcmp),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zca),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZCMT_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zcmt),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zca), CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZDINX_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zdinx),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zfinx),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZFA_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zfa),
+ .implied_misas = RVF,
+ .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
+};
+
+static RISCVCPUImpliedExtsRule ZFBFMIN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zfbfmin),
+ .implied_misas = RVF,
+ .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
+};
+
+static RISCVCPUImpliedExtsRule ZFH_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zfh),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zfhmin),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZFHMIN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zfhmin),
+ .implied_misas = RVF,
+ .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
+};
+
+static RISCVCPUImpliedExtsRule ZFINX_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zfinx),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZHINX_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zhinx),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zhinxmin),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZHINXMIN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zhinxmin),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zfinx),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZICNTR_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zicntr),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZIHPM_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zihpm),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZK_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zk),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zkn), CPU_CFG_OFFSET(ext_zkr),
+ CPU_CFG_OFFSET(ext_zkt),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZKN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zkn),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
+ CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zkne),
+ CPU_CFG_OFFSET(ext_zknd), CPU_CFG_OFFSET(ext_zknh),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZKS_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zks),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
+ CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zksed),
+ CPU_CFG_OFFSET(ext_zksh),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVBB_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvbb),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvkb),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVE32F_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zve32f),
+ .implied_misas = RVF,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve32x),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVE32X_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zve32x),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVE64D_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zve64d),
+ .implied_misas = RVD,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve64f),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVE64F_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zve64f),
+ .implied_misas = RVF,
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zve64x),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVE64X_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zve64x),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve32x),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVFBFMIN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvfbfmin),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve32f),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVFBFWMA_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvfbfwma),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvfbfmin), CPU_CFG_OFFSET(ext_zfbfmin),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVFH_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvfh),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zfhmin),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvfhmin),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve32f),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvkn),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvkned), CPU_CFG_OFFSET(ext_zvknhb),
+ CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKNC_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvknc),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvbc),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvkng),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvkg),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvknhb),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zve64x),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKS_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvks),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvksed), CPU_CFG_OFFSET(ext_zvksh),
+ CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKSC_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvksc),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvbc),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
+static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = {
+ .ext = CPU_CFG_OFFSET(ext_zvksg),
+ .implied_exts = {
+ CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvkg),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
&RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
&RVM_IMPLIED, &RVV_IMPLIED, NULL
};
RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
+ &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED,
+ &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED,
+ &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED,
+ &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED,
+ &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED,
+ &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED,
+ &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED,
+ &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED,
+ &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
+ &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
+ &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
+ &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED,
NULL
};
--
2.43.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 5/6] target/riscv: Add Zc extension implied rule
2024-06-16 2:46 [PATCH v2 0/6] Introduce extension implied rules frank.chang
` (3 preceding siblings ...)
2024-06-16 2:46 ` [PATCH v2 4/6] target/riscv: Add standard extension " frank.chang
@ 2024-06-16 2:46 ` frank.chang
2024-06-20 19:53 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 6/6] target/riscv: Remove extension auto-update check statements frank.chang
5 siblings, 1 reply; 15+ messages in thread
From: frank.chang @ 2024-06-16 2:46 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang, Jerry Zhang Jian, Max Chou
From: Frank Chang <frank.chang@sifive.com>
Zc extension has special implied rules that need to be handled separately.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
---
target/riscv/tcg/tcg-cpu.c | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f8d6371764..fe84d4402e 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -902,11 +902,45 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu,
}
}
+/* Zc extension has special implied rules that need to be handled separately. */
+static void cpu_enable_zc_implied_rules(RISCVCPU *cpu)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ CPURISCVState *env = &cpu->env;
+
+ if (cpu->cfg.ext_zce) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
+
+ if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+ }
+ }
+
+ /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */
+ if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
+
+ if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
+ }
+
+ if (riscv_has_ext(env, RVD)) {
+ cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
+ }
+ }
+}
+
static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
{
RISCVCPUImpliedExtsRule *rule;
int i;
+ /* Enable the implied extensions for Zc. */
+ cpu_enable_zc_implied_rules(cpu);
+
/* Enable the implied MISAs. */
for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
if (riscv_has_ext(&cpu->env, rule->ext)) {
--
2.43.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v2 6/6] target/riscv: Remove extension auto-update check statements
2024-06-16 2:46 [PATCH v2 0/6] Introduce extension implied rules frank.chang
` (4 preceding siblings ...)
2024-06-16 2:46 ` [PATCH v2 5/6] target/riscv: Add Zc extension implied rule frank.chang
@ 2024-06-16 2:46 ` frank.chang
2024-06-20 19:54 ` Daniel Henrique Barboza
5 siblings, 1 reply; 15+ messages in thread
From: frank.chang @ 2024-06-16 2:46 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang, Jerry Zhang Jian, Max Chou
From: Frank Chang <frank.chang@sifive.com>
Remove the old-fashioned extension auto-update check statements as
they are replaced by the extension implied rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Tested-by: Max Chou <max.chou@sifive.com>
---
target/riscv/tcg/tcg-cpu.c | 119 -------------------------------------
1 file changed, 119 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index fe84d4402e..94875c8ec9 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -468,10 +468,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_zfh) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
- }
-
if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
error_setg(errp, "Zfh/Zfhmin extensions require F extension");
return;
@@ -493,9 +489,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
error_propagate(errp, local_err);
return;
}
-
- /* The V vector extension depends on the Zve64d extension */
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
}
/* The Zve64d extension depends on the Zve64f extension */
@@ -504,18 +497,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
error_setg(errp, "Zve64d/V extensions require D extension");
return;
}
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
- }
-
- /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
- if (cpu->cfg.ext_zve64f) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
- }
-
- /* The Zve64x extension depends on the Zve32x extension */
- if (cpu->cfg.ext_zve64x) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
}
/* The Zve32f extension depends on the Zve32x extension */
@@ -524,11 +505,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
error_setg(errp, "Zve32f/Zve64f extensions require F extension");
return;
}
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
- }
-
- if (cpu->cfg.ext_zvfh) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
}
if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
@@ -551,11 +527,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- /* Set the ISA extensions, checks should have happened above */
- if (cpu->cfg.ext_zhinx) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- }
-
if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
return;
@@ -573,27 +544,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
}
- if (cpu->cfg.ext_zce) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
- if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
- }
- }
-
- /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
- if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
- }
- if (riscv_has_ext(env, RVD)) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
- }
- }
-
if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
error_setg(errp, "Zcf extension is only relevant to RV32");
return;
@@ -627,52 +577,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- /*
- * Shorthand vector crypto extensions
- */
- if (cpu->cfg.ext_zvknc) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
- }
-
- if (cpu->cfg.ext_zvkng) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true);
- }
-
- if (cpu->cfg.ext_zvkn) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
- }
-
- if (cpu->cfg.ext_zvksc) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
- }
-
- if (cpu->cfg.ext_zvksg) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true);
- }
-
- if (cpu->cfg.ext_zvks) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
- }
-
- if (cpu->cfg.ext_zvkt) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
- }
-
- if (cpu->cfg.ext_zvbb) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
- }
-
if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
@@ -688,29 +592,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if (cpu->cfg.ext_zk) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
- }
-
- if (cpu->cfg.ext_zkn) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
- }
-
- if (cpu->cfg.ext_zks) {
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
- cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
- }
-
if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) {
if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) {
error_setg(errp, "zicntr requires zicsr");
--
2.43.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition
2024-06-16 2:46 ` [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition frank.chang
@ 2024-06-20 19:51 ` Daniel Henrique Barboza
0 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2024-06-20 19:51 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs, Jerry Zhang Jian, Max Chou
On 6/15/24 11:46 PM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> RISCVCPUImpliedExtsRule is created to store the implied rules.
> 'is_misa' flag is used to distinguish whether the rule is derived
> from the MISA or other extensions.
> 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores
> the offset of the extension defined in RISCVCPUConfig. 'ext' will also
> serve as the key of the hash tables to look up the rule in the following
> commit.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> Tested-by: Max Chou <max.chou@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 8 ++++++++
> target/riscv/cpu.h | 25 +++++++++++++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 4760cb2cc1..bacbb32120 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2250,6 +2250,14 @@ RISCVCPUProfile *riscv_profiles[] = {
> NULL,
> };
>
> +RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
> + NULL
> +};
> +
> +RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
> + NULL
> +};
> +
> static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 90b8f1b08f..6b31731fa8 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -124,6 +124,31 @@ typedef enum {
> EXT_STATUS_DIRTY,
> } RISCVExtStatus;
>
> +typedef struct riscv_cpu_implied_exts_rule RISCVCPUImpliedExtsRule;
> +
> +struct riscv_cpu_implied_exts_rule {
> +#ifndef CONFIG_USER_ONLY
> + /*
> + * Bitmask indicates the rule enabled status for the harts.
> + * This enhancement is only available in system-mode QEMU,
> + * as we don't have a good way (e.g. mhartid) to distinguish
> + * the SMP cores in user-mode QEMU.
> + */
> + uint64_t enabled;
> +#endif
> + /* True if this is a MISA implied rule. */
> + bool is_misa;
> + /* ext is MISA bit if is_misa flag is true, else extension offset. */
> + const uint32_t ext;
> + const uint32_t implied_misas;
> + const uint32_t implied_exts[];
> +};
> +
> +extern RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[];
> +extern RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[];
> +
> +#define RISCV_IMPLIED_EXTS_RULE_END -1
> +
> #define MMU_USER_IDX 3
>
> #define MAX_RISCV_PMPS (16)
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers
2024-06-16 2:46 ` [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers frank.chang
@ 2024-06-20 19:52 ` Daniel Henrique Barboza
2024-06-21 4:14 ` Alistair Francis
1 sibling, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2024-06-20 19:52 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs, Jerry Zhang Jian, Max Chou
On 6/15/24 11:46 PM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Introduce helpers to enable the extensions based on the implied rules.
> The implied extensions are enabled recursively, so we don't have to
> expand all of them manually. This also eliminates the old-fashioned
> ordering requirement. For example, Zvksg implies Zvks, Zvks implies
> Zvksed, etc., removing the need to check the implied rules of Zvksg
> before Zvks.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> Tested-by: Max Chou <max.chou@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/tcg/tcg-cpu.c | 91 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index eb6f7b9d12..f8d6371764 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -36,6 +36,9 @@
> static GHashTable *multi_ext_user_opts;
> static GHashTable *misa_ext_user_opts;
>
> +static GHashTable *misa_implied_rules;
> +static GHashTable *ext_implied_rules;
> +
> static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> {
> return g_hash_table_contains(multi_ext_user_opts,
> @@ -836,11 +839,97 @@ static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
> }
> }
>
> +static void riscv_cpu_init_implied_exts_rules(void)
> +{
> + RISCVCPUImpliedExtsRule *rule;
> + int i;
> +
> + for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
> + g_hash_table_insert(misa_implied_rules, GUINT_TO_POINTER(rule->ext),
> + (gpointer)rule);
> + }
> +
> + for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
> + g_hash_table_insert(ext_implied_rules, GUINT_TO_POINTER(rule->ext),
> + (gpointer)rule);
> + }
> +}
> +
> +static void cpu_enable_implied_rule(RISCVCPU *cpu,
> + RISCVCPUImpliedExtsRule *rule)
> +{
> + CPURISCVState *env = &cpu->env;
> + RISCVCPUImpliedExtsRule *ir;
> + bool enabled = false;
> + int i;
> +
> +#ifndef CONFIG_USER_ONLY
> + enabled = qatomic_read(&rule->enabled) & BIT_ULL(cpu->env.mhartid);
> +#endif
> +
> + if (!enabled) {
> + /* Enable the implied MISAs. */
> + if (rule->implied_misas) {
> + riscv_cpu_set_misa_ext(env, env->misa_ext | rule->implied_misas);
> +
> + for (i = 0; misa_bits[i] != 0; i++) {
> + if (rule->implied_misas & misa_bits[i]) {
> + ir = g_hash_table_lookup(misa_implied_rules,
> + GUINT_TO_POINTER(misa_bits[i]));
> +
> + if (ir) {
> + cpu_enable_implied_rule(cpu, ir);
> + }
> + }
> + }
> + }
> +
> + /* Enable the implied extensions. */
> + for (i = 0; rule->implied_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) {
> + cpu_cfg_ext_auto_update(cpu, rule->implied_exts[i], true);
> +
> + ir = g_hash_table_lookup(ext_implied_rules,
> + GUINT_TO_POINTER(rule->implied_exts[i]));
> +
> + if (ir) {
> + cpu_enable_implied_rule(cpu, ir);
> + }
> + }
> +
> +#ifndef CONFIG_USER_ONLY
> + qatomic_or(&rule->enabled, BIT_ULL(cpu->env.mhartid));
> +#endif
> + }
> +}
> +
> +static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
> +{
> + RISCVCPUImpliedExtsRule *rule;
> + int i;
> +
> + /* Enable the implied MISAs. */
> + for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
> + if (riscv_has_ext(&cpu->env, rule->ext)) {
> + cpu_enable_implied_rule(cpu, rule);
> + }
> + }
> +
> + /* Enable the implied extensions. */
> + for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
> + if (isa_ext_is_enabled(cpu, rule->ext)) {
> + cpu_enable_implied_rule(cpu, rule);
> + }
> + }
> +}
> +
> void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
> {
> CPURISCVState *env = &cpu->env;
> Error *local_err = NULL;
>
> + riscv_cpu_init_implied_exts_rules();
> + riscv_cpu_enable_implied_rules(cpu);
> +
> riscv_cpu_validate_misa_priv(env, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> @@ -1346,6 +1435,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs)
>
> misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> + misa_implied_rules = g_hash_table_new(NULL, g_direct_equal);
> + ext_implied_rules = g_hash_table_new(NULL, g_direct_equal);
> riscv_cpu_add_user_properties(obj);
>
> if (riscv_cpu_has_max_extensions(obj)) {
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 3/6] target/riscv: Add MISA implied rules
2024-06-16 2:46 ` [PATCH v2 3/6] target/riscv: Add MISA implied rules frank.chang
@ 2024-06-20 19:53 ` Daniel Henrique Barboza
0 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2024-06-20 19:53 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs, Jerry Zhang Jian, Max Chou
On 6/15/24 11:46 PM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Add MISA extension implied rules to enable the implied extensions
> of MISA recursively.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> Tested-by: Max Chou <max.chou@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index bacbb32120..d09b5e9e62 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2250,8 +2250,56 @@ RISCVCPUProfile *riscv_profiles[] = {
> NULL,
> };
>
> +static RISCVCPUImpliedExtsRule RVA_IMPLIED = {
> + .is_misa = true,
> + .ext = RVA,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVD_IMPLIED = {
> + .is_misa = true,
> + .ext = RVD,
> + .implied_misas = RVF,
> + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVF_IMPLIED = {
> + .is_misa = true,
> + .ext = RVF,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVM_IMPLIED = {
> + .is_misa = true,
> + .ext = RVM,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zmmul),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
> + .is_misa = true,
> + .ext = RVV,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve64d),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
> - NULL
> + &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> + &RVM_IMPLIED, &RVV_IMPLIED, NULL
> };
>
> RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 4/6] target/riscv: Add standard extension implied rules
2024-06-16 2:46 ` [PATCH v2 4/6] target/riscv: Add standard extension " frank.chang
@ 2024-06-20 19:53 ` Daniel Henrique Barboza
0 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2024-06-20 19:53 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs, Jerry Zhang Jian, Max Chou
On 6/15/24 11:46 PM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Add standard extension implied rules to enable the implied extensions of
> the standard extension recursively.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> Tested-by: Max Chou <max.chou@sifive.com>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 340 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 340 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d09b5e9e62..1a3b1387e1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2297,12 +2297,352 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
> },
> };
>
> +static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zcb),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zca),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZCD_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zcd),
> + .implied_misas = RVD,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zca),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZCE_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zce),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zcb), CPU_CFG_OFFSET(ext_zcmp),
> + CPU_CFG_OFFSET(ext_zcmt),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZCF_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zcf),
> + .implied_misas = RVF,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zca),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZCMP_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zcmp),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zca),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZCMT_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zcmt),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zca), CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZDINX_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zdinx),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zfinx),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZFA_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zfa),
> + .implied_misas = RVF,
> + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZFBFMIN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zfbfmin),
> + .implied_misas = RVF,
> + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZFH_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zfh),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zfhmin),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZFHMIN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zfhmin),
> + .implied_misas = RVF,
> + .implied_exts = { RISCV_IMPLIED_EXTS_RULE_END },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZFINX_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zfinx),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZHINX_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zhinx),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zhinxmin),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZHINXMIN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zhinxmin),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zfinx),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZICNTR_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zicntr),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZIHPM_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zihpm),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZK_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zk),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zkn), CPU_CFG_OFFSET(ext_zkr),
> + CPU_CFG_OFFSET(ext_zkt),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZKN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zkn),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
> + CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zkne),
> + CPU_CFG_OFFSET(ext_zknd), CPU_CFG_OFFSET(ext_zknh),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZKS_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zks),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
> + CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zksed),
> + CPU_CFG_OFFSET(ext_zksh),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVBB_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvbb),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvkb),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVE32F_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zve32f),
> + .implied_misas = RVF,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve32x),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVE32X_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zve32x),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVE64D_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zve64d),
> + .implied_misas = RVD,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve64f),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVE64F_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zve64f),
> + .implied_misas = RVF,
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zve64x),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVE64X_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zve64x),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve32x),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVFBFMIN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvfbfmin),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve32f),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVFBFWMA_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvfbfwma),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvfbfmin), CPU_CFG_OFFSET(ext_zfbfmin),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVFH_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvfh),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zfhmin),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvfhmin),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve32f),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvkn),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvkned), CPU_CFG_OFFSET(ext_zvknhb),
> + CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKNC_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvknc),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvbc),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvkng),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvkg),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvknhb),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zve64x),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKS_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvks),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvksed), CPU_CFG_OFFSET(ext_zvksh),
> + CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKSC_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvksc),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvbc),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> +static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = {
> + .ext = CPU_CFG_OFFSET(ext_zvksg),
> + .implied_exts = {
> + CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvkg),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> RISCVCPUImpliedExtsRule *riscv_misa_implied_rules[] = {
> &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> &RVM_IMPLIED, &RVV_IMPLIED, NULL
> };
>
> RISCVCPUImpliedExtsRule *riscv_ext_implied_rules[] = {
> + &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED,
> + &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED,
> + &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED,
> + &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED,
> + &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED,
> + &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED,
> + &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED,
> + &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED,
> + &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
> + &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
> + &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
> + &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED,
> NULL
> };
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 5/6] target/riscv: Add Zc extension implied rule
2024-06-16 2:46 ` [PATCH v2 5/6] target/riscv: Add Zc extension implied rule frank.chang
@ 2024-06-20 19:53 ` Daniel Henrique Barboza
0 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2024-06-20 19:53 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs, Jerry Zhang Jian, Max Chou
On 6/15/24 11:46 PM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Zc extension has special implied rules that need to be handled separately.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> Tested-by: Max Chou <max.chou@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/tcg/tcg-cpu.c | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index f8d6371764..fe84d4402e 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -902,11 +902,45 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu,
> }
> }
>
> +/* Zc extension has special implied rules that need to be handled separately. */
> +static void cpu_enable_zc_implied_rules(RISCVCPU *cpu)
> +{
> + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> + CPURISCVState *env = &cpu->env;
> +
> + if (cpu->cfg.ext_zce) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
> +
> + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> + }
> + }
> +
> + /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */
> + if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> +
> + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> + }
> +
> + if (riscv_has_ext(env, RVD)) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
> + }
> + }
> +}
> +
> static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
> {
> RISCVCPUImpliedExtsRule *rule;
> int i;
>
> + /* Enable the implied extensions for Zc. */
> + cpu_enable_zc_implied_rules(cpu);
> +
> /* Enable the implied MISAs. */
> for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
> if (riscv_has_ext(&cpu->env, rule->ext)) {
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 6/6] target/riscv: Remove extension auto-update check statements
2024-06-16 2:46 ` [PATCH v2 6/6] target/riscv: Remove extension auto-update check statements frank.chang
@ 2024-06-20 19:54 ` Daniel Henrique Barboza
0 siblings, 0 replies; 15+ messages in thread
From: Daniel Henrique Barboza @ 2024-06-20 19:54 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs, Jerry Zhang Jian, Max Chou
On 6/15/24 11:46 PM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Remove the old-fashioned extension auto-update check statements as
> they are replaced by the extension implied rules.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> Tested-by: Max Chou <max.chou@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/tcg/tcg-cpu.c | 119 -------------------------------------
> 1 file changed, 119 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index fe84d4402e..94875c8ec9 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -468,10 +468,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> - if (cpu->cfg.ext_zfh) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true);
> - }
> -
> if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
> error_setg(errp, "Zfh/Zfhmin extensions require F extension");
> return;
> @@ -493,9 +489,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> error_propagate(errp, local_err);
> return;
> }
> -
> - /* The V vector extension depends on the Zve64d extension */
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true);
> }
>
> /* The Zve64d extension depends on the Zve64f extension */
> @@ -504,18 +497,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> error_setg(errp, "Zve64d/V extensions require D extension");
> return;
> }
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true);
> - }
> -
> - /* The Zve64f extension depends on the Zve64x and Zve32f extensions */
> - if (cpu->cfg.ext_zve64f) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64x), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true);
> - }
> -
> - /* The Zve64x extension depends on the Zve32x extension */
> - if (cpu->cfg.ext_zve64x) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
> }
>
> /* The Zve32f extension depends on the Zve32x extension */
> @@ -524,11 +505,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> error_setg(errp, "Zve32f/Zve64f extensions require F extension");
> return;
> }
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32x), true);
> - }
> -
> - if (cpu->cfg.ext_zvfh) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true);
> }
>
> if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
> @@ -551,11 +527,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> - /* Set the ISA extensions, checks should have happened above */
> - if (cpu->cfg.ext_zhinx) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> - }
> -
> if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
> error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
> return;
> @@ -573,27 +544,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> }
> }
>
> - if (cpu->cfg.ext_zce) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
> - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> - }
> - }
> -
> - /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
> - if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> - if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> - }
> - if (riscv_has_ext(env, RVD)) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
> - }
> - }
> -
> if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
> error_setg(errp, "Zcf extension is only relevant to RV32");
> return;
> @@ -627,52 +577,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> - /*
> - * Shorthand vector crypto extensions
> - */
> - if (cpu->cfg.ext_zvknc) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
> - }
> -
> - if (cpu->cfg.ext_zvkng) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkn), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true);
> - }
> -
> - if (cpu->cfg.ext_zvkn) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkned), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvknhb), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
> - }
> -
> - if (cpu->cfg.ext_zvksc) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
> - }
> -
> - if (cpu->cfg.ext_zvksg) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvks), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkg), true);
> - }
> -
> - if (cpu->cfg.ext_zvks) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksed), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvksh), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkt), true);
> - }
> -
> - if (cpu->cfg.ext_zvkt) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbb), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
> - }
> -
> - if (cpu->cfg.ext_zvbb) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
> - }
> -
> if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg ||
> cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed ||
> cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) {
> @@ -688,29 +592,6 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> - if (cpu->cfg.ext_zk) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true);
> - }
> -
> - if (cpu->cfg.ext_zkn) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true);
> - }
> -
> - if (cpu->cfg.ext_zks) {
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true);
> - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);
> - }
> -
> if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) {
> if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zicntr))) {
> error_setg(errp, "zicntr requires zicsr");
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers
2024-06-16 2:46 ` [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers frank.chang
2024-06-20 19:52 ` Daniel Henrique Barboza
@ 2024-06-21 4:14 ` Alistair Francis
2024-06-21 6:50 ` Frank Chang
1 sibling, 1 reply; 15+ messages in thread
From: Alistair Francis @ 2024-06-21 4:14 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Jerry Zhang Jian, Max Chou
On Sun, Jun 16, 2024 at 12:48 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Introduce helpers to enable the extensions based on the implied rules.
> The implied extensions are enabled recursively, so we don't have to
> expand all of them manually. This also eliminates the old-fashioned
> ordering requirement. For example, Zvksg implies Zvks, Zvks implies
> Zvksed, etc., removing the need to check the implied rules of Zvksg
> before Zvks.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> Tested-by: Max Chou <max.chou@sifive.com>
> ---
> target/riscv/tcg/tcg-cpu.c | 91 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index eb6f7b9d12..f8d6371764 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -36,6 +36,9 @@
> static GHashTable *multi_ext_user_opts;
> static GHashTable *misa_ext_user_opts;
>
> +static GHashTable *misa_implied_rules;
> +static GHashTable *ext_implied_rules;
> +
> static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> {
> return g_hash_table_contains(multi_ext_user_opts,
> @@ -836,11 +839,97 @@ static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
> }
> }
>
> +static void riscv_cpu_init_implied_exts_rules(void)
> +{
> + RISCVCPUImpliedExtsRule *rule;
> + int i;
> +
> + for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
> + g_hash_table_insert(misa_implied_rules, GUINT_TO_POINTER(rule->ext),
> + (gpointer)rule);
> + }
> +
> + for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
> + g_hash_table_insert(ext_implied_rules, GUINT_TO_POINTER(rule->ext),
> + (gpointer)rule);
> + }
> +}
> +
> +static void cpu_enable_implied_rule(RISCVCPU *cpu,
> + RISCVCPUImpliedExtsRule *rule)
> +{
> + CPURISCVState *env = &cpu->env;
> + RISCVCPUImpliedExtsRule *ir;
> + bool enabled = false;
> + int i;
> +
> +#ifndef CONFIG_USER_ONLY
> + enabled = qatomic_read(&rule->enabled) & BIT_ULL(cpu->env.mhartid);
enabled is a uint64_t, so this limits us to 64 harts right?
The virt machine currently has a limit of 512, so this won't work right?
Alistair
> +#endif
> +
> + if (!enabled) {
> + /* Enable the implied MISAs. */
> + if (rule->implied_misas) {
> + riscv_cpu_set_misa_ext(env, env->misa_ext | rule->implied_misas);
> +
> + for (i = 0; misa_bits[i] != 0; i++) {
> + if (rule->implied_misas & misa_bits[i]) {
> + ir = g_hash_table_lookup(misa_implied_rules,
> + GUINT_TO_POINTER(misa_bits[i]));
> +
> + if (ir) {
> + cpu_enable_implied_rule(cpu, ir);
> + }
> + }
> + }
> + }
> +
> + /* Enable the implied extensions. */
> + for (i = 0; rule->implied_exts[i] != RISCV_IMPLIED_EXTS_RULE_END; i++) {
> + cpu_cfg_ext_auto_update(cpu, rule->implied_exts[i], true);
> +
> + ir = g_hash_table_lookup(ext_implied_rules,
> + GUINT_TO_POINTER(rule->implied_exts[i]));
> +
> + if (ir) {
> + cpu_enable_implied_rule(cpu, ir);
> + }
> + }
> +
> +#ifndef CONFIG_USER_ONLY
> + qatomic_or(&rule->enabled, BIT_ULL(cpu->env.mhartid));
> +#endif
> + }
> +}
> +
> +static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
> +{
> + RISCVCPUImpliedExtsRule *rule;
> + int i;
> +
> + /* Enable the implied MISAs. */
> + for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
> + if (riscv_has_ext(&cpu->env, rule->ext)) {
> + cpu_enable_implied_rule(cpu, rule);
> + }
> + }
> +
> + /* Enable the implied extensions. */
> + for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
> + if (isa_ext_is_enabled(cpu, rule->ext)) {
> + cpu_enable_implied_rule(cpu, rule);
> + }
> + }
> +}
> +
> void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
> {
> CPURISCVState *env = &cpu->env;
> Error *local_err = NULL;
>
> + riscv_cpu_init_implied_exts_rules();
> + riscv_cpu_enable_implied_rules(cpu);
> +
> riscv_cpu_validate_misa_priv(env, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> @@ -1346,6 +1435,8 @@ static void riscv_tcg_cpu_instance_init(CPUState *cs)
>
> misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> + misa_implied_rules = g_hash_table_new(NULL, g_direct_equal);
> + ext_implied_rules = g_hash_table_new(NULL, g_direct_equal);
> riscv_cpu_add_user_properties(obj);
>
> if (riscv_cpu_has_max_extensions(obj)) {
> --
> 2.43.2
>
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers
2024-06-21 4:14 ` Alistair Francis
@ 2024-06-21 6:50 ` Frank Chang
0 siblings, 0 replies; 15+ messages in thread
From: Frank Chang @ 2024-06-21 6:50 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Jerry Zhang Jian, Max Chou
[-- Attachment #1: Type: text/plain, Size: 5768 bytes --]
On Fri, Jun 21, 2024 at 12:15 PM Alistair Francis <alistair23@gmail.com>
wrote:
> On Sun, Jun 16, 2024 at 12:48 PM <frank.chang@sifive.com> wrote:
> >
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > Introduce helpers to enable the extensions based on the implied rules.
> > The implied extensions are enabled recursively, so we don't have to
> > expand all of them manually. This also eliminates the old-fashioned
> > ordering requirement. For example, Zvksg implies Zvks, Zvks implies
> > Zvksed, etc., removing the need to check the implied rules of Zvksg
> > before Zvks.
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> > Tested-by: Max Chou <max.chou@sifive.com>
> > ---
> > target/riscv/tcg/tcg-cpu.c | 91 ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 91 insertions(+)
> >
> > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> > index eb6f7b9d12..f8d6371764 100644
> > --- a/target/riscv/tcg/tcg-cpu.c
> > +++ b/target/riscv/tcg/tcg-cpu.c
> > @@ -36,6 +36,9 @@
> > static GHashTable *multi_ext_user_opts;
> > static GHashTable *misa_ext_user_opts;
> >
> > +static GHashTable *misa_implied_rules;
> > +static GHashTable *ext_implied_rules;
> > +
> > static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
> > {
> > return g_hash_table_contains(multi_ext_user_opts,
> > @@ -836,11 +839,97 @@ static void riscv_cpu_validate_profiles(RISCVCPU
> *cpu)
> > }
> > }
> >
> > +static void riscv_cpu_init_implied_exts_rules(void)
> > +{
> > + RISCVCPUImpliedExtsRule *rule;
> > + int i;
> > +
> > + for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
> > + g_hash_table_insert(misa_implied_rules,
> GUINT_TO_POINTER(rule->ext),
> > + (gpointer)rule);
> > + }
> > +
> > + for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
> > + g_hash_table_insert(ext_implied_rules,
> GUINT_TO_POINTER(rule->ext),
> > + (gpointer)rule);
> > + }
> > +}
> > +
> > +static void cpu_enable_implied_rule(RISCVCPU *cpu,
> > + RISCVCPUImpliedExtsRule *rule)
> > +{
> > + CPURISCVState *env = &cpu->env;
> > + RISCVCPUImpliedExtsRule *ir;
> > + bool enabled = false;
> > + int i;
> > +
> > +#ifndef CONFIG_USER_ONLY
> > + enabled = qatomic_read(&rule->enabled) & BIT_ULL(cpu->env.mhartid);
>
> enabled is a uint64_t, so this limits us to 64 harts right?
>
> The virt machine currently has a limit of 512, so this won't work right?
>
> Alistair
>
Yes, that's true.
Though it wouldn't impact the result as this is just the optimization
of not iterating the rules that have been applied already.
Maybe I can replace it with the dynamic hart bitmask.
Regards,
Frank Chang
>
> > +#endif
> > +
> > + if (!enabled) {
> > + /* Enable the implied MISAs. */
> > + if (rule->implied_misas) {
> > + riscv_cpu_set_misa_ext(env, env->misa_ext |
> rule->implied_misas);
> > +
> > + for (i = 0; misa_bits[i] != 0; i++) {
> > + if (rule->implied_misas & misa_bits[i]) {
> > + ir = g_hash_table_lookup(misa_implied_rules,
> > +
> GUINT_TO_POINTER(misa_bits[i]));
> > +
> > + if (ir) {
> > + cpu_enable_implied_rule(cpu, ir);
> > + }
> > + }
> > + }
> > + }
> > +
> > + /* Enable the implied extensions. */
> > + for (i = 0; rule->implied_exts[i] !=
> RISCV_IMPLIED_EXTS_RULE_END; i++) {
> > + cpu_cfg_ext_auto_update(cpu, rule->implied_exts[i], true);
> > +
> > + ir = g_hash_table_lookup(ext_implied_rules,
> > +
> GUINT_TO_POINTER(rule->implied_exts[i]));
> > +
> > + if (ir) {
> > + cpu_enable_implied_rule(cpu, ir);
> > + }
> > + }
> > +
> > +#ifndef CONFIG_USER_ONLY
> > + qatomic_or(&rule->enabled, BIT_ULL(cpu->env.mhartid));
> > +#endif
> > + }
> > +}
> > +
> > +static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
> > +{
> > + RISCVCPUImpliedExtsRule *rule;
> > + int i;
> > +
> > + /* Enable the implied MISAs. */
> > + for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
> > + if (riscv_has_ext(&cpu->env, rule->ext)) {
> > + cpu_enable_implied_rule(cpu, rule);
> > + }
> > + }
> > +
> > + /* Enable the implied extensions. */
> > + for (i = 0; (rule = riscv_ext_implied_rules[i]); i++) {
> > + if (isa_ext_is_enabled(cpu, rule->ext)) {
> > + cpu_enable_implied_rule(cpu, rule);
> > + }
> > + }
> > +}
> > +
> > void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
> > {
> > CPURISCVState *env = &cpu->env;
> > Error *local_err = NULL;
> >
> > + riscv_cpu_init_implied_exts_rules();
> > + riscv_cpu_enable_implied_rules(cpu);
> > +
> > riscv_cpu_validate_misa_priv(env, &local_err);
> > if (local_err != NULL) {
> > error_propagate(errp, local_err);
> > @@ -1346,6 +1435,8 @@ static void riscv_tcg_cpu_instance_init(CPUState
> *cs)
> >
> > misa_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> > multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal);
> > + misa_implied_rules = g_hash_table_new(NULL, g_direct_equal);
> > + ext_implied_rules = g_hash_table_new(NULL, g_direct_equal);
> > riscv_cpu_add_user_properties(obj);
> >
> > if (riscv_cpu_has_max_extensions(obj)) {
> > --
> > 2.43.2
> >
> >
>
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^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2024-06-21 6:51 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-06-16 2:46 [PATCH v2 0/6] Introduce extension implied rules frank.chang
2024-06-16 2:46 ` [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition frank.chang
2024-06-20 19:51 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers frank.chang
2024-06-20 19:52 ` Daniel Henrique Barboza
2024-06-21 4:14 ` Alistair Francis
2024-06-21 6:50 ` Frank Chang
2024-06-16 2:46 ` [PATCH v2 3/6] target/riscv: Add MISA implied rules frank.chang
2024-06-20 19:53 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 4/6] target/riscv: Add standard extension " frank.chang
2024-06-20 19:53 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 5/6] target/riscv: Add Zc extension implied rule frank.chang
2024-06-20 19:53 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 6/6] target/riscv: Remove extension auto-update check statements frank.chang
2024-06-20 19:54 ` Daniel Henrique Barboza
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