From: Michael Walle <michael@walle.cc>
To: Tudor.Ambarus@microchip.com
Cc: vigneshr@ti.com, richard@nod.at, linux-kernel@vger.kernel.org,
linux-mtd@lists.infradead.org, miquel.raynal@bootlin.com,
liew.s.piaw@gmail.com
Subject: Re: [PATCH v2] mtd: spi-nor: macronix: enable 4-bit BP support for MX25L6405D
Date: Sat, 23 Jan 2021 14:04:19 +0100 [thread overview]
Message-ID: <0fb41db8c9495e2dcca9f2da48670555@walle.cc> (raw)
In-Reply-To: <93b7f8e8-cdf4-5b09-da17-636d8fcaf0ee@microchip.com>
Am 2021-01-23 13:18, schrieb Tudor.Ambarus@microchip.com:
> Hi, Sieng,
>
> On 12/8/20 3:57 AM, Sieng Piaw Liew wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know
>> the content is safe
>>
>> Enable 4-bit Block Protect support for MX256405D and its variants
>> using
>> the same ID.
>>
>> Tested on Innacom W3400V6 router with MX25L6406E chip.
MX25L6406E?
>> https://github.com/openwrt/openwrt/pull/3501
>>
>> Signed-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com>
>> ---
>> Changes in v2:
>> - Add SPI_NOR_HAS_LOCK which SPI_NOR_4BIT_BP required.
>>
>> drivers/mtd/spi-nor/macronix.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/spi-nor/macronix.c
>> b/drivers/mtd/spi-nor/macronix.c
>> index 9203abaac229..033ede381673 100644
>> --- a/drivers/mtd/spi-nor/macronix.c
>> +++ b/drivers/mtd/spi-nor/macronix.c
>> @@ -42,7 +42,9 @@ static const struct flash_info macronix_parts[] = {
>> { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
>> { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
>> { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
>> - { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
>> + { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128,
>> + SECT_4K | SPI_NOR_HAS_LOCK |
>> + SPI_NOR_4BIT_BP) },
>
> I've read again the datasheet[1], and to me it looks like we
> don't support the locking scheme for this flash.
> What mx25l6405d calls BP3, we refer to as Top/Bottom support (TB bit).
> The problem that I see is that mx25l6405d uses some kind of twisted
> TB bit.
>
> For example, for BP3=1, BP2=0, BP1=0, BP0=1, the flash's datasheet
> states that the lower half blocks are protected (0th-63th), while in
> our code we would expect that just the lower first two blocks to be
> protected (0th and 1st). We need new support for this flash.
I double checked that and we don't support this. BP3 is indeed some
kind of TB bit. But not the TB bit which is currently supported. I
guess with the current code, protection scheme can be supported iff
BP3 == 0.
-michael
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Michael Walle <michael@walle.cc>
To: Tudor.Ambarus@microchip.com
Cc: liew.s.piaw@gmail.com, miquel.raynal@bootlin.com, richard@nod.at,
vigneshr@ti.com, linux-mtd@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] mtd: spi-nor: macronix: enable 4-bit BP support for MX25L6405D
Date: Sat, 23 Jan 2021 14:04:19 +0100 [thread overview]
Message-ID: <0fb41db8c9495e2dcca9f2da48670555@walle.cc> (raw)
In-Reply-To: <93b7f8e8-cdf4-5b09-da17-636d8fcaf0ee@microchip.com>
Am 2021-01-23 13:18, schrieb Tudor.Ambarus@microchip.com:
> Hi, Sieng,
>
> On 12/8/20 3:57 AM, Sieng Piaw Liew wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know
>> the content is safe
>>
>> Enable 4-bit Block Protect support for MX256405D and its variants
>> using
>> the same ID.
>>
>> Tested on Innacom W3400V6 router with MX25L6406E chip.
MX25L6406E?
>> https://github.com/openwrt/openwrt/pull/3501
>>
>> Signed-off-by: Sieng Piaw Liew <liew.s.piaw@gmail.com>
>> ---
>> Changes in v2:
>> - Add SPI_NOR_HAS_LOCK which SPI_NOR_4BIT_BP required.
>>
>> drivers/mtd/spi-nor/macronix.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/spi-nor/macronix.c
>> b/drivers/mtd/spi-nor/macronix.c
>> index 9203abaac229..033ede381673 100644
>> --- a/drivers/mtd/spi-nor/macronix.c
>> +++ b/drivers/mtd/spi-nor/macronix.c
>> @@ -42,7 +42,9 @@ static const struct flash_info macronix_parts[] = {
>> { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
>> { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
>> { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
>> - { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
>> + { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128,
>> + SECT_4K | SPI_NOR_HAS_LOCK |
>> + SPI_NOR_4BIT_BP) },
>
> I've read again the datasheet[1], and to me it looks like we
> don't support the locking scheme for this flash.
> What mx25l6405d calls BP3, we refer to as Top/Bottom support (TB bit).
> The problem that I see is that mx25l6405d uses some kind of twisted
> TB bit.
>
> For example, for BP3=1, BP2=0, BP1=0, BP0=1, the flash's datasheet
> states that the lower half blocks are protected (0th-63th), while in
> our code we would expect that just the lower first two blocks to be
> protected (0th and 1st). We need new support for this flash.
I double checked that and we don't support this. BP3 is indeed some
kind of TB bit. But not the TB bit which is currently supported. I
guess with the current code, protection scheme can be supported iff
BP3 == 0.
-michael
next prev parent reply other threads:[~2021-01-23 13:05 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-07 2:46 [PATCH] mtd: spi-nor: macronix: enable 4-bit BP support for MX25L6405D Sieng Piaw Liew
2020-12-07 2:46 ` Sieng Piaw Liew
2020-12-07 17:53 ` Tudor.Ambarus
2020-12-07 17:53 ` Tudor.Ambarus
2020-12-08 1:19 ` Sieng Piaw Liew
2020-12-08 1:19 ` Sieng Piaw Liew
2020-12-08 1:57 ` [PATCH v2] " Sieng Piaw Liew
2020-12-08 1:57 ` Sieng Piaw Liew
2021-01-23 12:18 ` Tudor.Ambarus
2021-01-23 12:18 ` Tudor.Ambarus
2021-01-23 13:04 ` Michael Walle [this message]
2021-01-23 13:04 ` Michael Walle
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0fb41db8c9495e2dcca9f2da48670555@walle.cc \
--to=michael@walle.cc \
--cc=Tudor.Ambarus@microchip.com \
--cc=liew.s.piaw@gmail.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=miquel.raynal@bootlin.com \
--cc=richard@nod.at \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.