[U-Boot] [PATCH v2 3/4] mx5: Optimize lowlevel_init for TO 3

["Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>]

The mx5 lowlevel_init.S contains code that detects the silicon revision at
runtime, and that behaves differently if a silicon revision older than TO 3 is
detected. This code is useless for recently designed boards that may not be
fitted with older silicon revisions. Hence, this patch adds an option to
optimize away this revision-specific code from lowlevel_init.S.

Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
 - Make patch description more detailed.

 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |    4 ++--
 .../doc/README.imx5                                |    7 ++++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 529e35b..d0f75fa 100644
--- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -42,7 +42,7 @@
 	         1 << 23 |		/* disable write allocate combine */ \
 	         1 << 22		/* disable write allocate */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3)
 	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10
 
@@ -244,7 +244,7 @@ setup_pll_func:
 
 	ldr r0, =CCM_BASE_ADDR
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3)
 	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
 	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10
diff --git u-boot-4d3c95f.orig/doc/README.imx5 u-boot-4d3c95f/doc/README.imx5
index f7eab7d..938d3da 100644
--- u-boot-4d3c95f.orig/doc/README.imx5
+++ u-boot-4d3c95f/doc/README.imx5
@@ -6,7 +6,12 @@ i.MX5x SoCs.
 1. CONFIGURATION OPTIONS/SETTINGS
 ---------------------------------
 
-1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
+1.1 CONFIG_MX51_TO_3: i.MX51 silicon revision 3 or higher.
+    This option can be enabled for these i.MX51 silicon revisions to optimize
+    away some specific behavior triggered by the detection of older silicon
+    revisions at runtime.
+
+1.2 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
     This option should be enabled by all boards using the i.MX51 silicon
     version up until (including) 3.0 running@800MHz.
     The PLL's in the i.MX51 processor can go out of lock due to a metastable