From: Stefano Babic <sbabic@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 2/4] mx5: Optimize lowlevel_init code size
Date: Sun, 30 Sep 2012 14:47:24 +0200 [thread overview]
Message-ID: <50683F5C.8030901@denx.de> (raw)
In-Reply-To: <1558465107.2404121.1344957552151.JavaMail.root@advansee.com>
On 14/08/2012 17:19, Beno?t Th?baudeau wrote:
> Optimize mx5 lowlevel_init.S code size:
> - Compute values at compile time rather than at runtime where possible.
> - Assign r4 to hold the zero value rather than setting registers to 0 again and
> again.
> - Associate a function to setup_pll rather than expanding its large macro code
> multiple times.
> - Allocate constant values in section only if used.
>
> Signed-off-by: Beno?t Th?baudeau <benoit.thebaudeau@advansee.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v2:
> - Make patch description more detailed.
>
> .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 112 +++++++++++---------
> 1 file changed, 59 insertions(+), 53 deletions(-)
>
> diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> index a40b84f..529e35b 100644
> --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S
> @@ -24,6 +24,8 @@
> #include <generated/asm-offsets.h>
> #include <linux/linkage.h>
>
> +.section ".text.init", "x"
> +
> /*
> * L2CC Cache setup/invalidation/disable
> */
> @@ -34,15 +36,14 @@
> mcr 15, 0, r0, c1, c0, 1
>
> /* reconfigure L2 cache aux control reg */
> - mov r0, #0xC0 /* tag RAM */
> - add r0, r0, #0x4 /* data RAM */
> - orr r0, r0, #1 << 24 /* disable write allocate delay */
> - orr r0, r0, #1 << 23 /* disable write allocate combine */
> - orr r0, r0, #1 << 22 /* disable write allocate */
> + ldr r0, =0xC0 | /* tag RAM */ \
> + 0x4 | /* data RAM */ \
> + 1 << 24 | /* disable write allocate delay */ \
> + 1 << 23 | /* disable write allocate combine */ \
> + 1 << 22 /* disable write allocate */
>
> #if defined(CONFIG_MX51)
> - ldr r1, =0x0
> - ldr r3, [r1, #ROM_SI_REV]
> + ldr r3, [r4, #ROM_SI_REV]
> cmp r3, #0x10
>
> /* disable write combine for TO 2 and lower revs */
> @@ -84,8 +85,7 @@
> ldr r1, =0x00000203
> str r1, [r0, #0x40]
>
> - ldr r1, =0x0
> - str r1, [r0, #0x44]
> + str r4, [r0, #0x44]
>
> ldr r1, =0x00120125
> str r1, [r0, #0x9C]
> @@ -98,20 +98,29 @@
>
> .macro setup_pll pll, freq
> ldr r0, =\pll
> + adr r2, W_DP_\freq
> + bl setup_pll_func
> +.endm
> +
> +#define W_DP_OP 0
> +#define W_DP_MFD 4
> +#define W_DP_MFN 8
> +
> +setup_pll_func:
> ldr r1, =0x00001232
> str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
> mov r1, #0x2
> str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
>
> - ldr r1, W_DP_OP_\freq
> + ldr r1, [r2, #W_DP_OP]
> str r1, [r0, #PLL_DP_OP]
> str r1, [r0, #PLL_DP_HFS_OP]
>
> - ldr r1, W_DP_MFD_\freq
> + ldr r1, [r2, #W_DP_MFD]
> str r1, [r0, #PLL_DP_MFD]
> str r1, [r0, #PLL_DP_HFS_MFD]
>
> - ldr r1, W_DP_MFN_\freq
> + ldr r1, [r2, #W_DP_MFN]
> str r1, [r0, #PLL_DP_MFN]
> str r1, [r0, #PLL_DP_HFS_MFN]
>
> @@ -120,12 +129,13 @@
> 1: ldr r1, [r0, #PLL_DP_CTL]
> ands r1, r1, #0x1
> beq 1b
> -.endm
> +
> + /* r10 saved upper lr */
> + mov pc, lr
>
> .macro setup_pll_errata pll, freq
> ldr r2, =\pll
> - mov r1, #0x0
> - str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
> + str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
> ldr r1, =0x00001236
> str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
> 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
> @@ -158,10 +168,9 @@
> /* Gate of clocks to the peripherals first */
> ldr r1, =0x3FFFFFFF
> str r1, [r0, #CLKCTL_CCGR0]
> - ldr r1, =0x0
> - str r1, [r0, #CLKCTL_CCGR1]
> - str r1, [r0, #CLKCTL_CCGR2]
> - str r1, [r0, #CLKCTL_CCGR3]
> + str r4, [r0, #CLKCTL_CCGR1]
> + str r4, [r0, #CLKCTL_CCGR2]
> + str r4, [r0, #CLKCTL_CCGR3]
>
> ldr r1, =0x00030000
> str r1, [r0, #CLKCTL_CCGR4]
> @@ -184,11 +193,10 @@
> #else
> ldr r1, =0x3FFFFFFF
> str r1, [r0, #CLKCTL_CCGR0]
> - ldr r1, =0x0
> - str r1, [r0, #CLKCTL_CCGR1]
> - str r1, [r0, #CLKCTL_CCGR2]
> - str r1, [r0, #CLKCTL_CCGR3]
> - str r1, [r0, #CLKCTL_CCGR7]
> + str r4, [r0, #CLKCTL_CCGR1]
> + str r4, [r0, #CLKCTL_CCGR2]
> + str r4, [r0, #CLKCTL_CCGR3]
> + str r4, [r0, #CLKCTL_CCGR7]
>
> ldr r1, =0x00030000
> str r1, [r0, #CLKCTL_CCGR4]
> @@ -214,8 +222,7 @@
>
> /* Switch peripheral to PLL 3 */
> ldr r0, =CCM_BASE_ADDR
> - ldr r1, =0x000010C0
> - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
> + ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
> str r1, [r0, #CLKCTL_CBCMR]
> ldr r1, =0x13239145
> str r1, [r0, #CLKCTL_CBCDR]
> @@ -225,8 +232,7 @@
> ldr r0, =CCM_BASE_ADDR
> ldr r1, =0x19239145
> str r1, [r0, #CLKCTL_CBCDR]
> - ldr r1, =0x000020C0
> - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
> + ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
> str r1, [r0, #CLKCTL_CBCMR]
> #endif
> setup_pll PLL3_BASE_ADDR, 216
> @@ -240,8 +246,7 @@
>
> #if defined(CONFIG_MX51)
> /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
> - ldr r1, =0x0
> - ldr r3, [r1, #ROM_SI_REV]
> + ldr r3, [r4, #ROM_SI_REV]
> cmp r3, #0x10
> movls r1, #0x1
> movhi r1, #0
> @@ -251,14 +256,12 @@
> str r1, [r0, #CLKCTL_CACRR]
>
> /* Switch ARM back to PLL 1 */
> - mov r1, #0
> - str r1, [r0, #CLKCTL_CCSR]
> + str r4, [r0, #CLKCTL_CCSR]
>
> #if defined(CONFIG_MX51)
> /* setup the rest */
> /* Use lp_apm (24MHz) source for perclk */
> - ldr r1, =0x000020C2
> - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
> + ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
> str r1, [r0, #CLKCTL_CBCMR]
> /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
> ldr r1, =CONFIG_SYS_CLKTL_CBCDR
> @@ -289,7 +292,6 @@
> ldr r0, =CCM_BASE_ADDR
> ldr r1, =0x00808145
> orr r1, r1, #2 << 10
> - orr r1, r1, #0 << 16
> orr r1, r1, #1 << 19
> str r1, [r0, #CLKCTL_CBCDR]
>
> @@ -310,8 +312,7 @@
> cmp r1, #0x0
> bne 1b
>
> - mov r1, #0x0
> - str r1, [r0, #CLKCTL_CCDR]
> + str r4, [r0, #CLKCTL_CCDR]
>
> /* for cko - for ARM div by 8 */
> mov r1, #0x000A0000
> @@ -325,9 +326,10 @@
> strh r1, [r0]
> .endm
>
> -.section ".text.init", "x"
> -
> ENTRY(lowlevel_init)
> + mov r10, lr
> + mov r4, #0 /* Fix R4 to 0 */
> +
> #if defined(CONFIG_MX51)
> ldr r0, =GPIO1_BASE_ADDR
> ldr r1, [r0, #0x0]
> @@ -346,21 +348,25 @@ ENTRY(lowlevel_init)
>
> init_clock
>
> - /* r12 saved upper lr*/
> - mov pc,lr
> + mov pc, r10
> ENDPROC(lowlevel_init)
>
> /* Board level setting value */
> -W_DP_OP_864: .word DP_OP_864
> -W_DP_MFD_864: .word DP_MFD_864
> -W_DP_MFN_864: .word DP_MFN_864
> +#if defined(CONFIG_MX51_PLL_ERRATA)
> +W_DP_864: .word DP_OP_864
> + .word DP_MFD_864
> + .word DP_MFN_864
> W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
> -W_DP_OP_800: .word DP_OP_800
> -W_DP_MFD_800: .word DP_MFD_800
> -W_DP_MFN_800: .word DP_MFN_800
> -W_DP_OP_665: .word DP_OP_665
> -W_DP_MFD_665: .word DP_MFD_665
> -W_DP_MFN_665: .word DP_MFN_665
> -W_DP_OP_216: .word DP_OP_216
> -W_DP_MFD_216: .word DP_MFD_216
> -W_DP_MFN_216: .word DP_MFN_216
> +#else
> +W_DP_800: .word DP_OP_800
> + .word DP_MFD_800
> + .word DP_MFN_800
> +#endif
> +#if defined(CONFIG_MX51)
> +W_DP_665: .word DP_OP_665
> + .word DP_MFD_665
> + .word DP_MFN_665
> +#endif
> +W_DP_216: .word DP_OP_216
> + .word DP_MFD_216
> + .word DP_MFN_216
>
I don't see any issue with this patch.
Tested also on mx53loco.
Tested-by: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Regards,
Stefano
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next prev parent reply other threads:[~2012-09-30 12:47 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-14 14:43 [U-Boot] [PATCH 1/4] mx5: cosmetic: Clean up lowlevel_init Benoît Thébaudeau
2012-08-14 14:44 ` [U-Boot] [PATCH 2/4] mx5: Optimize lowlevel_init code size Benoît Thébaudeau
2012-08-14 14:52 ` Otavio Salvador
2012-08-14 15:19 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
2012-09-30 12:47 ` Stefano Babic [this message]
2012-09-30 12:49 ` Stefano Babic
2012-08-14 14:44 ` [U-Boot] [PATCH 3/4] mx5: Optimize lowlevel_init for TO 3 Benoît Thébaudeau
2012-08-14 14:56 ` Otavio Salvador
2012-08-14 15:19 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
2012-08-20 8:20 ` Stefano Babic
2012-08-20 10:12 ` Benoît Thébaudeau
2012-08-14 14:44 ` [U-Boot] [PATCH 4/4] mx5: Mark lowlevel_init board-specific code Benoît Thébaudeau
2012-08-15 14:34 ` Benoît Thébaudeau
2012-11-05 20:07 ` [U-Boot] [PATCH v2] " Benoît Thébaudeau
2012-11-07 14:29 ` Stefano Babic
2012-11-16 22:42 ` Benoît Thébaudeau
2012-11-19 7:42 ` Stefano Babic
2012-11-19 7:57 ` Stefano Babic
2012-08-14 14:51 ` [U-Boot] [PATCH 1/4] mx5: cosmetic: Clean up lowlevel_init Otavio Salvador
2012-08-14 15:18 ` [U-Boot] [PATCH v2 " Benoît Thébaudeau
2012-08-17 11:41 ` Stefano Babic
2012-08-20 7:56 ` Stefano Babic
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