* [PATCH] drm/i915: HSW: allow PCH clock gating for suspend
@ 2013-04-16 11:25 Imre Deak
2013-04-16 11:35 ` Ville Syrjälä
2013-04-17 11:04 ` [PATCH v2] " Imre Deak
0 siblings, 2 replies; 9+ messages in thread
From: Imre Deak @ 2013-04-16 11:25 UTC (permalink / raw)
To: intel-gfx
For the device to enter D3 we should enable PCH clock gating.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 5 +++++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
5 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bddb9a5..e9a82f1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -521,6 +521,8 @@ static int i915_drm_freeze(struct drm_device *dev)
*/
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
dev_priv->display.crtc_disable(crtc);
+
+ intel_modeset_suspend_hw(dev);
}
i915_save_state(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5a495a..e549e6c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
+extern void intel_modeset_suspend_hw(struct drm_device *dev);
extern void intel_modeset_init(struct drm_device *dev);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 457a0a0..e9192bf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8984,6 +8984,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
mutex_unlock(&dev->struct_mutex);
}
+void intel_modeset_suspend_hw(struct drm_device *dev)
+{
+ intel_suspend_hw(dev);
+}
+
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d7bd031..8b29897 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
extern void intel_init_clock_gating(struct drm_device *dev);
+extern void intel_suspend_hw(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index baea4fc..3567881 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3735,6 +3735,18 @@ static void lpt_init_clock_gating(struct drm_device *dev)
PCH_LP_PARTITION_LEVEL_DISABLE);
}
+static void lpt_allow_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
+ uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
+
+ val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+ }
+}
+
static void haswell_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4085,6 +4097,12 @@ void intel_init_clock_gating(struct drm_device *dev)
dev_priv->display.init_clock_gating(dev);
}
+void intel_suspend_hw(struct drm_device *dev)
+{
+ if (IS_HASWELL(dev))
+ lpt_allow_clock_gating(dev);
+}
+
void intel_set_power_well(struct drm_device *dev, bool enable)
{
struct drm_i915_private *dev_priv = dev->dev_private;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: HSW: allow PCH clock gating for suspend
2013-04-16 11:25 [PATCH] drm/i915: HSW: allow PCH clock gating for suspend Imre Deak
@ 2013-04-16 11:35 ` Ville Syrjälä
2013-04-16 11:43 ` Imre Deak
2013-04-17 11:04 ` [PATCH v2] " Imre Deak
1 sibling, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2013-04-16 11:35 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote:
> For the device to enter D3 we should enable PCH clock gating.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 5 +++++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
> 5 files changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index bddb9a5..e9a82f1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -521,6 +521,8 @@ static int i915_drm_freeze(struct drm_device *dev)
> */
> list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
> dev_priv->display.crtc_disable(crtc);
> +
> + intel_modeset_suspend_hw(dev);
> }
>
> i915_save_state(dev);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b5a495a..e549e6c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
>
> /* modesetting */
> extern void intel_modeset_init_hw(struct drm_device *dev);
> +extern void intel_modeset_suspend_hw(struct drm_device *dev);
> extern void intel_modeset_init(struct drm_device *dev);
> extern void intel_modeset_gem_init(struct drm_device *dev);
> extern void intel_modeset_cleanup(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 457a0a0..e9192bf 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8984,6 +8984,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
> mutex_unlock(&dev->struct_mutex);
> }
>
> +void intel_modeset_suspend_hw(struct drm_device *dev)
> +{
> + intel_suspend_hw(dev);
> +}
> +
Why this extra level of indirection?
> void intel_modeset_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d7bd031..8b29897 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
>
> extern void intel_init_clock_gating(struct drm_device *dev);
> +extern void intel_suspend_hw(struct drm_device *dev);
> extern void intel_write_eld(struct drm_encoder *encoder,
> struct drm_display_mode *mode);
> extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index baea4fc..3567881 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3735,6 +3735,18 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> PCH_LP_PARTITION_LEVEL_DISABLE);
> }
>
> +static void lpt_allow_clock_gating(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
> +
> + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> + }
So who sets it back when we resume?
> +}
> +
> static void haswell_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4085,6 +4097,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> dev_priv->display.init_clock_gating(dev);
> }
>
> +void intel_suspend_hw(struct drm_device *dev)
> +{
> + if (IS_HASWELL(dev))
> + lpt_allow_clock_gating(dev);
Do you need the HSW check? Isn't the LPT LP check enough?
> +}
> +
> void intel_set_power_well(struct drm_device *dev, bool enable)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: HSW: allow PCH clock gating for suspend
2013-04-16 11:35 ` Ville Syrjälä
@ 2013-04-16 11:43 ` Imre Deak
2013-04-16 17:50 ` Paulo Zanoni
0 siblings, 1 reply; 9+ messages in thread
From: Imre Deak @ 2013-04-16 11:43 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, 2013-04-16 at 14:35 +0300, Ville Syrjälä wrote:
> On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote:
> > For the device to enter D3 we should enable PCH clock gating.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 2 ++
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 5 +++++
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
> > 5 files changed, 27 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index bddb9a5..e9a82f1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -521,6 +521,8 @@ static int i915_drm_freeze(struct drm_device *dev)
> > */
> > list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
> > dev_priv->display.crtc_disable(crtc);
> > +
> > + intel_modeset_suspend_hw(dev);
> > }
> >
> > i915_save_state(dev);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b5a495a..e549e6c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
> >
> > /* modesetting */
> > extern void intel_modeset_init_hw(struct drm_device *dev);
> > +extern void intel_modeset_suspend_hw(struct drm_device *dev);
> > extern void intel_modeset_init(struct drm_device *dev);
> > extern void intel_modeset_gem_init(struct drm_device *dev);
> > extern void intel_modeset_cleanup(struct drm_device *dev);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 457a0a0..e9192bf 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8984,6 +8984,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
> > mutex_unlock(&dev->struct_mutex);
> > }
> >
> > +void intel_modeset_suspend_hw(struct drm_device *dev)
> > +{
> > + intel_suspend_hw(dev);
> > +}
> > +
>
> Why this extra level of indirection?
I thought it'd be more symmetric w.r.t.
__i915_drm_thaw->intel_modeset_init_hw().
> > void intel_modeset_init(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index d7bd031..8b29897 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> > #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> >
> > extern void intel_init_clock_gating(struct drm_device *dev);
> > +extern void intel_suspend_hw(struct drm_device *dev);
> > extern void intel_write_eld(struct drm_encoder *encoder,
> > struct drm_display_mode *mode);
> > extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index baea4fc..3567881 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3735,6 +3735,18 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> > PCH_LP_PARTITION_LEVEL_DISABLE);
> > }
> >
> > +static void lpt_allow_clock_gating(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> > + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
> > +
> > + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> > + I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> > + }
>
> So who sets it back when we resume?
intel_modeset_init_hw()->intel_init_clock_gating()
>
> > +}
> > +
> > static void haswell_init_clock_gating(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -4085,6 +4097,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> > dev_priv->display.init_clock_gating(dev);
> > }
> >
> > +void intel_suspend_hw(struct drm_device *dev)
> > +{
> > + if (IS_HASWELL(dev))
> > + lpt_allow_clock_gating(dev);
>
> Do you need the HSW check? Isn't the LPT LP check enough?
Not sure. According to the spec this is a workaround for HSW/LPT.
> > +}
> > +
> > void intel_set_power_well(struct drm_device *dev, bool enable)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > --
> > 1.7.10.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: HSW: allow PCH clock gating for suspend
2013-04-16 11:43 ` Imre Deak
@ 2013-04-16 17:50 ` Paulo Zanoni
2013-04-16 19:53 ` Imre Deak
0 siblings, 1 reply; 9+ messages in thread
From: Paulo Zanoni @ 2013-04-16 17:50 UTC (permalink / raw)
To: imre.deak; +Cc: Intel Graphics Development
2013/4/16 Imre Deak <imre.deak@intel.com>:
> On Tue, 2013-04-16 at 14:35 +0300, Ville Syrjälä wrote:
>> On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote:
>> > For the device to enter D3 we should enable PCH clock gating.
>> >
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/i915_drv.c | 2 ++
>> > drivers/gpu/drm/i915/i915_drv.h | 1 +
>> > drivers/gpu/drm/i915/intel_display.c | 5 +++++
>> > drivers/gpu/drm/i915/intel_drv.h | 1 +
>> > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
>> > 5 files changed, 27 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> > index bddb9a5..e9a82f1 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.c
>> > +++ b/drivers/gpu/drm/i915/i915_drv.c
>> > @@ -521,6 +521,8 @@ static int i915_drm_freeze(struct drm_device *dev)
>> > */
>> > list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
>> > dev_priv->display.crtc_disable(crtc);
>> > +
>> > + intel_modeset_suspend_hw(dev);
>> > }
>> >
>> > i915_save_state(dev);
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> > index b5a495a..e549e6c 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
>> >
>> > /* modesetting */
>> > extern void intel_modeset_init_hw(struct drm_device *dev);
>> > +extern void intel_modeset_suspend_hw(struct drm_device *dev);
>> > extern void intel_modeset_init(struct drm_device *dev);
>> > extern void intel_modeset_gem_init(struct drm_device *dev);
>> > extern void intel_modeset_cleanup(struct drm_device *dev);
>> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> > index 457a0a0..e9192bf 100644
>> > --- a/drivers/gpu/drm/i915/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/intel_display.c
>> > @@ -8984,6 +8984,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
>> > mutex_unlock(&dev->struct_mutex);
>> > }
>> >
>> > +void intel_modeset_suspend_hw(struct drm_device *dev)
>> > +{
>> > + intel_suspend_hw(dev);
>> > +}
>> > +
>>
>> Why this extra level of indirection?
>
> I thought it'd be more symmetric w.r.t.
>
> __i915_drm_thaw->intel_modeset_init_hw().
>
>> > void intel_modeset_init(struct drm_device *dev)
>> > {
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> > index d7bd031..8b29897 100644
>> > --- a/drivers/gpu/drm/i915/intel_drv.h
>> > +++ b/drivers/gpu/drm/i915/intel_drv.h
>> > @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
>> > #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
>> >
>> > extern void intel_init_clock_gating(struct drm_device *dev);
>> > +extern void intel_suspend_hw(struct drm_device *dev);
>> > extern void intel_write_eld(struct drm_encoder *encoder,
>> > struct drm_display_mode *mode);
>> > extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
>> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> > index baea4fc..3567881 100644
>> > --- a/drivers/gpu/drm/i915/intel_pm.c
>> > +++ b/drivers/gpu/drm/i915/intel_pm.c
>> > @@ -3735,6 +3735,18 @@ static void lpt_init_clock_gating(struct drm_device *dev)
>> > PCH_LP_PARTITION_LEVEL_DISABLE);
>> > }
>> >
>> > +static void lpt_allow_clock_gating(struct drm_device *dev)
>> > +{
>> > + struct drm_i915_private *dev_priv = dev->dev_private;
>> > +
>> > + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
>> > + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
>> > +
>> > + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
>> > + I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
>> > + }
>>
>> So who sets it back when we resume?
>
> intel_modeset_init_hw()->intel_init_clock_gating()
>
>>
>> > +}
>> > +
>> > static void haswell_init_clock_gating(struct drm_device *dev)
>> > {
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> > @@ -4085,6 +4097,12 @@ void intel_init_clock_gating(struct drm_device *dev)
>> > dev_priv->display.init_clock_gating(dev);
>> > }
>> >
>> > +void intel_suspend_hw(struct drm_device *dev)
>> > +{
>> > + if (IS_HASWELL(dev))
>> > + lpt_allow_clock_gating(dev);
>>
>> Do you need the HSW check? Isn't the LPT LP check enough?
>
> Not sure. According to the spec this is a workaround for HSW/LPT.
I'd check for HAS_PCH_LPT before calling lpt_allow_clock_gating. Let's
not forget that, for example, PPT is considered the same as CPT, so
any code that's inside a "HAS_PCH_CPT" runs for both SNB and IVB.
Optional bikeshed: maybe rename "lpt_allow_clock_gating" to "lpt_suspend_hw"?
>
>> > +}
>> > +
>> > void intel_set_power_well(struct drm_device *dev, bool enable)
>> > {
>> > struct drm_i915_private *dev_priv = dev->dev_private;
>> > --
>> > 1.7.10.4
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: HSW: allow PCH clock gating for suspend
2013-04-16 17:50 ` Paulo Zanoni
@ 2013-04-16 19:53 ` Imre Deak
0 siblings, 0 replies; 9+ messages in thread
From: Imre Deak @ 2013-04-16 19:53 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: Intel Graphics Development
On Tue, 2013-04-16 at 14:50 -0300, Paulo Zanoni wrote:
> 2013/4/16 Imre Deak <imre.deak@intel.com>:
> > On Tue, 2013-04-16 at 14:35 +0300, Ville Syrjälä wrote:
> >> On Tue, Apr 16, 2013 at 02:25:16PM +0300, Imre Deak wrote:
> >> > For the device to enter D3 we should enable PCH clock gating.
> >> >
> >> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/i915_drv.c | 2 ++
> >> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> >> > drivers/gpu/drm/i915/intel_display.c | 5 +++++
> >> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> >> > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
> >> > 5 files changed, 27 insertions(+)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> >> > index bddb9a5..e9a82f1 100644
> >> > --- a/drivers/gpu/drm/i915/i915_drv.c
> >> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> >> > @@ -521,6 +521,8 @@ static int i915_drm_freeze(struct drm_device *dev)
> >> > */
> >> > list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
> >> > dev_priv->display.crtc_disable(crtc);
> >> > +
> >> > + intel_modeset_suspend_hw(dev);
> >> > }
> >> >
> >> > i915_save_state(dev);
> >> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> > index b5a495a..e549e6c 100644
> >> > --- a/drivers/gpu/drm/i915/i915_drv.h
> >> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> > @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
> >> >
> >> > /* modesetting */
> >> > extern void intel_modeset_init_hw(struct drm_device *dev);
> >> > +extern void intel_modeset_suspend_hw(struct drm_device *dev);
> >> > extern void intel_modeset_init(struct drm_device *dev);
> >> > extern void intel_modeset_gem_init(struct drm_device *dev);
> >> > extern void intel_modeset_cleanup(struct drm_device *dev);
> >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >> > index 457a0a0..e9192bf 100644
> >> > --- a/drivers/gpu/drm/i915/intel_display.c
> >> > +++ b/drivers/gpu/drm/i915/intel_display.c
> >> > @@ -8984,6 +8984,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
> >> > mutex_unlock(&dev->struct_mutex);
> >> > }
> >> >
> >> > +void intel_modeset_suspend_hw(struct drm_device *dev)
> >> > +{
> >> > + intel_suspend_hw(dev);
> >> > +}
> >> > +
> >>
> >> Why this extra level of indirection?
> >
> > I thought it'd be more symmetric w.r.t.
> >
> > __i915_drm_thaw->intel_modeset_init_hw().
> >
> >> > void intel_modeset_init(struct drm_device *dev)
> >> > {
> >> > struct drm_i915_private *dev_priv = dev->dev_private;
> >> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> >> > index d7bd031..8b29897 100644
> >> > --- a/drivers/gpu/drm/i915/intel_drv.h
> >> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> > @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> >> > #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> >> >
> >> > extern void intel_init_clock_gating(struct drm_device *dev);
> >> > +extern void intel_suspend_hw(struct drm_device *dev);
> >> > extern void intel_write_eld(struct drm_encoder *encoder,
> >> > struct drm_display_mode *mode);
> >> > extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
> >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> > index baea4fc..3567881 100644
> >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> > @@ -3735,6 +3735,18 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> >> > PCH_LP_PARTITION_LEVEL_DISABLE);
> >> > }
> >> >
> >> > +static void lpt_allow_clock_gating(struct drm_device *dev)
> >> > +{
> >> > + struct drm_i915_private *dev_priv = dev->dev_private;
> >> > +
> >> > + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> >> > + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
> >> > +
> >> > + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> >> > + I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> >> > + }
> >>
> >> So who sets it back when we resume?
> >
> > intel_modeset_init_hw()->intel_init_clock_gating()
> >
> >>
> >> > +}
> >> > +
> >> > static void haswell_init_clock_gating(struct drm_device *dev)
> >> > {
> >> > struct drm_i915_private *dev_priv = dev->dev_private;
> >> > @@ -4085,6 +4097,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> >> > dev_priv->display.init_clock_gating(dev);
> >> > }
> >> >
> >> > +void intel_suspend_hw(struct drm_device *dev)
> >> > +{
> >> > + if (IS_HASWELL(dev))
> >> > + lpt_allow_clock_gating(dev);
> >>
> >> Do you need the HSW check? Isn't the LPT LP check enough?
> >
> > Not sure. According to the spec this is a workaround for HSW/LPT.
>
> I'd check for HAS_PCH_LPT before calling lpt_allow_clock_gating. Let's
> not forget that, for example, PPT is considered the same as CPT, so
> any code that's inside a "HAS_PCH_CPT" runs for both SNB and IVB.
>
> Optional bikeshed: maybe rename "lpt_allow_clock_gating" to "lpt_suspend_hw"?
Ok, will change these.
--Imre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2] drm/i915: HSW: allow PCH clock gating for suspend
2013-04-16 11:25 [PATCH] drm/i915: HSW: allow PCH clock gating for suspend Imre Deak
2013-04-16 11:35 ` Ville Syrjälä
@ 2013-04-17 11:04 ` Imre Deak
2013-04-17 19:05 ` Paulo Zanoni
1 sibling, 1 reply; 9+ messages in thread
From: Imre Deak @ 2013-04-17 11:04 UTC (permalink / raw)
To: intel-gfx
For the device to enter D3 we should enable PCH clock gating.
v2:
- use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
- rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 5 +++++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
5 files changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9ebe895..6902219 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -525,6 +525,8 @@ static int i915_drm_freeze(struct drm_device *dev)
*/
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
dev_priv->display.crtc_disable(crtc);
+
+ intel_modeset_suspend_hw(dev);
}
i915_save_state(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b5a495a..e549e6c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
/* modesetting */
extern void intel_modeset_init_hw(struct drm_device *dev);
+extern void intel_modeset_suspend_hw(struct drm_device *dev);
extern void intel_modeset_init(struct drm_device *dev);
extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dce643c..dec9019 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9004,6 +9004,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
mutex_unlock(&dev->struct_mutex);
}
+void intel_modeset_suspend_hw(struct drm_device *dev)
+{
+ intel_suspend_hw(dev);
+}
+
void intel_modeset_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a124e05..3f31b2e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
extern void intel_init_clock_gating(struct drm_device *dev);
+extern void intel_suspend_hw(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f747cb0..8a163d4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3750,6 +3750,18 @@ static void lpt_init_clock_gating(struct drm_device *dev)
PCH_LP_PARTITION_LEVEL_DISABLE);
}
+static void lpt_suspend_hw(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
+ uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
+
+ val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
+ }
+}
+
static void haswell_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4100,6 +4112,12 @@ void intel_init_clock_gating(struct drm_device *dev)
dev_priv->display.init_clock_gating(dev);
}
+void intel_suspend_hw(struct drm_device *dev)
+{
+ if (HAS_PCH_LPT(dev))
+ lpt_suspend_hw(dev);
+}
+
/**
* We should only use the power well if we explicitly asked the hardware to
* enable it, so check if it's enabled and also check if we've requested it to
--
1.7.10.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915: HSW: allow PCH clock gating for suspend
2013-04-17 11:04 ` [PATCH v2] " Imre Deak
@ 2013-04-17 19:05 ` Paulo Zanoni
2013-04-17 20:15 ` Imre Deak
2013-05-09 21:05 ` Daniel Vetter
0 siblings, 2 replies; 9+ messages in thread
From: Paulo Zanoni @ 2013-04-17 19:05 UTC (permalink / raw)
To: Imre Deak; +Cc: Intel Graphics Development
Hi
2013/4/17 Imre Deak <imre.deak@intel.com>:
> For the device to enter D3 we should enable PCH clock gating.
>
> v2:
> - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
> - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
>
s/Paolo/Paulo/ :)
Besides this, the patch looks fine. But I can't test it right now
since suspend seems to be broken on my machine, even with nomodeset.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 5 +++++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
> 5 files changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 9ebe895..6902219 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -525,6 +525,8 @@ static int i915_drm_freeze(struct drm_device *dev)
> */
> list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
> dev_priv->display.crtc_disable(crtc);
> +
> + intel_modeset_suspend_hw(dev);
> }
>
> i915_save_state(dev);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b5a495a..e549e6c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
>
> /* modesetting */
> extern void intel_modeset_init_hw(struct drm_device *dev);
> +extern void intel_modeset_suspend_hw(struct drm_device *dev);
> extern void intel_modeset_init(struct drm_device *dev);
> extern void intel_modeset_gem_init(struct drm_device *dev);
> extern void intel_modeset_cleanup(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index dce643c..dec9019 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9004,6 +9004,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
> mutex_unlock(&dev->struct_mutex);
> }
>
> +void intel_modeset_suspend_hw(struct drm_device *dev)
> +{
> + intel_suspend_hw(dev);
> +}
> +
> void intel_modeset_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index a124e05..3f31b2e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
>
> extern void intel_init_clock_gating(struct drm_device *dev);
> +extern void intel_suspend_hw(struct drm_device *dev);
> extern void intel_write_eld(struct drm_encoder *encoder,
> struct drm_display_mode *mode);
> extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f747cb0..8a163d4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3750,6 +3750,18 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> PCH_LP_PARTITION_LEVEL_DISABLE);
> }
>
> +static void lpt_suspend_hw(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
> +
> + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> + }
> +}
> +
> static void haswell_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -4100,6 +4112,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> dev_priv->display.init_clock_gating(dev);
> }
>
> +void intel_suspend_hw(struct drm_device *dev)
> +{
> + if (HAS_PCH_LPT(dev))
> + lpt_suspend_hw(dev);
> +}
> +
> /**
> * We should only use the power well if we explicitly asked the hardware to
> * enable it, so check if it's enabled and also check if we've requested it to
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915: HSW: allow PCH clock gating for suspend
2013-04-17 19:05 ` Paulo Zanoni
@ 2013-04-17 20:15 ` Imre Deak
2013-05-09 21:05 ` Daniel Vetter
1 sibling, 0 replies; 9+ messages in thread
From: Imre Deak @ 2013-04-17 20:15 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: Intel Graphics Development
On Wed, 2013-04-17 at 16:05 -0300, Paulo Zanoni wrote:
> Hi
>
> 2013/4/17 Imre Deak <imre.deak@intel.com>:
> > For the device to enter D3 we should enable PCH clock gating.
> >
> > v2:
> > - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
> > - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
> >
>
> s/Paolo/Paulo/ :)
Ok, sorry..
> Besides this, the patch looks fine. But I can't test it right now
> since suspend seems to be broken on my machine, even with nomodeset.
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Yes, same here suspend is broken even without loading i915.
>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 2 ++
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 5 +++++
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
> > 5 files changed, 27 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 9ebe895..6902219 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -525,6 +525,8 @@ static int i915_drm_freeze(struct drm_device *dev)
> > */
> > list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
> > dev_priv->display.crtc_disable(crtc);
> > +
> > + intel_modeset_suspend_hw(dev);
> > }
> >
> > i915_save_state(dev);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b5a495a..e549e6c 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1831,6 +1831,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
> >
> > /* modesetting */
> > extern void intel_modeset_init_hw(struct drm_device *dev);
> > +extern void intel_modeset_suspend_hw(struct drm_device *dev);
> > extern void intel_modeset_init(struct drm_device *dev);
> > extern void intel_modeset_gem_init(struct drm_device *dev);
> > extern void intel_modeset_cleanup(struct drm_device *dev);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index dce643c..dec9019 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -9004,6 +9004,11 @@ void intel_modeset_init_hw(struct drm_device *dev)
> > mutex_unlock(&dev->struct_mutex);
> > }
> >
> > +void intel_modeset_suspend_hw(struct drm_device *dev)
> > +{
> > + intel_suspend_hw(dev);
> > +}
> > +
> > void intel_modeset_init(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index a124e05..3f31b2e 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -652,6 +652,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> > #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> >
> > extern void intel_init_clock_gating(struct drm_device *dev);
> > +extern void intel_suspend_hw(struct drm_device *dev);
> > extern void intel_write_eld(struct drm_encoder *encoder,
> > struct drm_display_mode *mode);
> > extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index f747cb0..8a163d4 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3750,6 +3750,18 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> > PCH_LP_PARTITION_LEVEL_DISABLE);
> > }
> >
> > +static void lpt_suspend_hw(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = dev->dev_private;
> > +
> > + if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
> > + uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
> > +
> > + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> > + I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> > + }
> > +}
> > +
> > static void haswell_init_clock_gating(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -4100,6 +4112,12 @@ void intel_init_clock_gating(struct drm_device *dev)
> > dev_priv->display.init_clock_gating(dev);
> > }
> >
> > +void intel_suspend_hw(struct drm_device *dev)
> > +{
> > + if (HAS_PCH_LPT(dev))
> > + lpt_suspend_hw(dev);
> > +}
> > +
> > /**
> > * We should only use the power well if we explicitly asked the hardware to
> > * enable it, so check if it's enabled and also check if we've requested it to
> > --
> > 1.7.10.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Paulo Zanoni
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] drm/i915: HSW: allow PCH clock gating for suspend
2013-04-17 19:05 ` Paulo Zanoni
2013-04-17 20:15 ` Imre Deak
@ 2013-05-09 21:05 ` Daniel Vetter
1 sibling, 0 replies; 9+ messages in thread
From: Daniel Vetter @ 2013-05-09 21:05 UTC (permalink / raw)
To: Paulo Zanoni; +Cc: Intel Graphics Development
On Wed, Apr 17, 2013 at 04:05:10PM -0300, Paulo Zanoni wrote:
> Hi
>
> 2013/4/17 Imre Deak <imre.deak@intel.com>:
> > For the device to enter D3 we should enable PCH clock gating.
> >
> > v2:
> > - use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
> > - rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
> >
>
> s/Paolo/Paulo/ :)
> Besides this, the patch looks fine. But I can't test it right now
> since suspend seems to be broken on my machine, even with nomodeset.
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Paulo poked me about this on irc, so queued for -next, thanks for the
patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-05-09 21:02 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-04-16 11:25 [PATCH] drm/i915: HSW: allow PCH clock gating for suspend Imre Deak
2013-04-16 11:35 ` Ville Syrjälä
2013-04-16 11:43 ` Imre Deak
2013-04-16 17:50 ` Paulo Zanoni
2013-04-16 19:53 ` Imre Deak
2013-04-17 11:04 ` [PATCH v2] " Imre Deak
2013-04-17 19:05 ` Paulo Zanoni
2013-04-17 20:15 ` Imre Deak
2013-05-09 21:05 ` Daniel Vetter
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