From: joe@perches.com (Joe Perches)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb
Date: Mon, 11 Jan 2016 23:11:23 -0800 [thread overview]
Message-ID: <1452582683.7773.102.camel@perches.com> (raw)
In-Reply-To: <1452580473-10073-1-git-send-email-andi.shyti@samsung.com>
On Tue, 2016-01-12 at 15:34 +0900, Andi Shyti wrote:
> In some architectures the L2 cache controller is integrated in the
> processor's block itself and it doesn't use any external cache
> controller. This means that an entry in the board's dtb related
> to the l2c is not necessary.
>
> Distinguish between error codes and print just an information in
> case of -ENODEV.
trivia:
> diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
[]
> @@ -95,7 +95,9 @@ void __init init_IRQ(void)
> ? outer_cache.write_sec = machine_desc->l2c_write_sec;
> ? ret = l2x0_of_init(machine_desc->l2c_aux_val,
> ? ???machine_desc->l2c_aux_mask);
> - if (ret)
> + if (ret == -ENODEV)
> + pr_info("no L2C controller entry found in the dtb\n");
Perhaps this would be more consistent if it was
pr_info("L2C: no controller entry found in the dtb\n");
>
> + else if (ret)
> ? pr_err("L2C: failed to init: %d\n", ret);
> ? }
> ?
WARNING: multiple messages have this Message-ID (diff)
From: Joe Perches <joe@perches.com>
To: Andi Shyti <andi.shyti@samsung.com>,
linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk, tony@atomide.com, robh@kernel.org,
tglx@linutronix.de, olof@lixom.net, tomasz.figa@gmail.com,
jiang.liu@linux.intel.com, yamada.masahiro@socionext.com,
linux-kernel@vger.kernel.org, k.kozlowski@samsung.com,
m.szyprowski@samsung.com, andi@etezian.org
Subject: Re: [PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb
Date: Mon, 11 Jan 2016 23:11:23 -0800 [thread overview]
Message-ID: <1452582683.7773.102.camel@perches.com> (raw)
In-Reply-To: <1452580473-10073-1-git-send-email-andi.shyti@samsung.com>
On Tue, 2016-01-12 at 15:34 +0900, Andi Shyti wrote:
> In some architectures the L2 cache controller is integrated in the
> processor's block itself and it doesn't use any external cache
> controller. This means that an entry in the board's dtb related
> to the l2c is not necessary.
>
> Distinguish between error codes and print just an information in
> case of -ENODEV.
trivia:
> diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
[]
> @@ -95,7 +95,9 @@ void __init init_IRQ(void)
> outer_cache.write_sec = machine_desc->l2c_write_sec;
> ret = l2x0_of_init(machine_desc->l2c_aux_val,
> machine_desc->l2c_aux_mask);
> - if (ret)
> + if (ret == -ENODEV)
> + pr_info("no L2C controller entry found in the dtb\n");
Perhaps this would be more consistent if it was
pr_info("L2C: no controller entry found in the dtb\n");
>
> + else if (ret)
> pr_err("L2C: failed to init: %d\n", ret);
> }
>
next prev parent reply other threads:[~2016-01-12 7:11 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-12 6:34 [PATCH] arm: irq: l2c: do not print error in case of missing l2c from dtb Andi Shyti
2016-01-12 6:34 ` Andi Shyti
2016-01-12 7:11 ` Joe Perches [this message]
2016-01-12 7:11 ` Joe Perches
2016-01-12 7:24 ` [PATCH v2] " Andi Shyti
2016-01-12 7:24 ` Andi Shyti
2016-01-12 8:28 ` Krzysztof Kozlowski
2016-01-12 8:28 ` Krzysztof Kozlowski
2016-01-12 8:35 ` [PATCH] " Marek Szyprowski
2016-01-12 8:35 ` Marek Szyprowski
2016-01-12 10:11 ` [PATCH v3] " Andi Shyti
2016-01-12 10:11 ` Andi Shyti
2016-01-12 23:55 ` Krzysztof Kozlowski
2016-01-12 23:55 ` Krzysztof Kozlowski
2016-01-20 18:02 ` Javier Martinez Canillas
2016-01-20 18:02 ` Javier Martinez Canillas
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