From: Meng Yi <meng.yi@nxp.com>
To: stefan@agner.ch, airlied@linux.ie
Cc: Meng Yi <meng.yi@nxp.com>,
dri-devel@lists.freedesktop.org,
alexander.stein@systec-electronic.com
Subject: [PATCH] drm/fsl-dcu: Fix endian issue when using clk_register_divider
Date: Thu, 11 Aug 2016 14:54:40 +0800 [thread overview]
Message-ID: <1470898480-3538-1-git-send-email-meng.yi@nxp.com> (raw)
While clk_register_divider will write register as little endian,
Modified the param "shift" from 0 to 24 since DCU is big endian.
Or reg "DCU_DIV_RATIO" will be seted as a incorrect value which
will cause vblank timing issue etc.
Signed-off-by: Meng Yi <meng.yi@nxp.com>
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 7882387..2c1e2f9 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -386,7 +386,7 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
pix_clk_in_name, 0, base + DCU_DIV_RATIO,
- 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
+ 24, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
if (IS_ERR(fsl_dev->pix_clk)) {
dev_err(dev, "failed to register pix clk\n");
ret = PTR_ERR(fsl_dev->pix_clk);
--
2.1.0.27.g96db324
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next reply other threads:[~2016-08-11 7:22 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-11 6:54 Meng Yi [this message]
2016-08-22 7:13 ` [PATCH] drm/fsl-dcu: Fix endian issue when using clk_register_divider Meng Yi
2016-08-22 16:44 ` Stefan Agner
2016-08-23 10:16 ` Meng Yi
-- strict thread matches above, loose matches on Subject: below --
2016-09-02 19:07 [PATCH] drm/fsl-dcu: fix " Stefan Agner
2016-09-02 19:07 ` Stefan Agner
2016-09-05 8:46 ` Meng Yi
2016-09-05 8:46 ` Meng Yi
2016-09-05 19:24 ` Stefan Agner
2016-09-05 19:24 ` Stefan Agner
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