From: Stefan Agner <stefan@agner.ch>
To: dri-devel@lists.freedesktop.org
Cc: jianwei.wang.chn@gmail.com, meng.yi@nxp.com,
alison.wang@freescale.com, linux-kernel@vger.kernel.org,
stable@vger.kernel.org
Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
Date: Fri, 2 Sep 2016 12:07:53 -0700 [thread overview]
Message-ID: <20160902190753.27736-1-stefan@agner.ch> (raw)
Since using clk_register_divider to setup the pixel clock, regmap
is no longer used. Regmap did take care of DCU using different
endianness. Check endianness using the device-tree property
"big-endian" to determine the location of DIV_RATIO.
Cc: stable@vger.kernel.org
Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel clock divider")
Reported-by: Meng Yi <meng.yi@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 7882387..8dd042e 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -330,6 +330,7 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
const char *pix_clk_in_name;
const struct of_device_id *id;
int ret;
+ u8 div_ratio_shift = 0;
fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
if (!fsl_dev)
@@ -382,11 +383,15 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
pix_clk_in = fsl_dev->clk;
}
+ if (of_property_read_bool(dev->of_node, "big-endian"))
+ div_ratio_shift = 24;
+
+
pix_clk_in_name = __clk_get_name(pix_clk_in);
snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
pix_clk_in_name, 0, base + DCU_DIV_RATIO,
- 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
+ div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
if (IS_ERR(fsl_dev->pix_clk)) {
dev_err(dev, "failed to register pix clk\n");
ret = PTR_ERR(fsl_dev->pix_clk);
--
2.9.0
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WARNING: multiple messages have this Message-ID (diff)
From: Stefan Agner <stefan@agner.ch>
To: dri-devel@lists.freedesktop.org
Cc: meng.yi@nxp.com, alison.wang@freescale.com,
jianwei.wang.chn@gmail.com, linux-kernel@vger.kernel.org,
Stefan Agner <stefan@agner.ch>,
stable@vger.kernel.org
Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
Date: Fri, 2 Sep 2016 12:07:53 -0700 [thread overview]
Message-ID: <20160902190753.27736-1-stefan@agner.ch> (raw)
Since using clk_register_divider to setup the pixel clock, regmap
is no longer used. Regmap did take care of DCU using different
endianness. Check endianness using the device-tree property
"big-endian" to determine the location of DIV_RATIO.
Cc: stable@vger.kernel.org
Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel clock divider")
Reported-by: Meng Yi <meng.yi@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
index 7882387..8dd042e 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
@@ -330,6 +330,7 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
const char *pix_clk_in_name;
const struct of_device_id *id;
int ret;
+ u8 div_ratio_shift = 0;
fsl_dev = devm_kzalloc(dev, sizeof(*fsl_dev), GFP_KERNEL);
if (!fsl_dev)
@@ -382,11 +383,15 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
pix_clk_in = fsl_dev->clk;
}
+ if (of_property_read_bool(dev->of_node, "big-endian"))
+ div_ratio_shift = 24;
+
+
pix_clk_in_name = __clk_get_name(pix_clk_in);
snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix", pix_clk_in_name);
fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
pix_clk_in_name, 0, base + DCU_DIV_RATIO,
- 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
+ div_ratio_shift, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
if (IS_ERR(fsl_dev->pix_clk)) {
dev_err(dev, "failed to register pix clk\n");
ret = PTR_ERR(fsl_dev->pix_clk);
--
2.9.0
next reply other threads:[~2016-09-02 19:08 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-02 19:07 Stefan Agner [this message]
2016-09-02 19:07 ` [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider Stefan Agner
2016-09-05 8:46 ` Meng Yi
2016-09-05 8:46 ` Meng Yi
2016-09-05 19:24 ` Stefan Agner
2016-09-05 19:24 ` Stefan Agner
-- strict thread matches above, loose matches on Subject: below --
2016-08-11 6:54 [PATCH] drm/fsl-dcu: Fix " Meng Yi
2016-08-22 7:13 ` Meng Yi
2016-08-22 16:44 ` Stefan Agner
2016-08-23 10:16 ` Meng Yi
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