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From: Stefan Agner <stefan@agner.ch>
To: Meng Yi <meng.yi@nxp.com>
Cc: jianwei.wang.chn@gmail.com, stable@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	alison.wang@freescale.com
Subject: RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
Date: Mon, 05 Sep 2016 12:24:18 -0700	[thread overview]
Message-ID: <10c3b7b3a84d8406a7aa44867ea1a124@agner.ch> (raw)
In-Reply-To: <DB6PR0401MB2631D676D8D91B9E71566911ECE60@DB6PR0401MB2631.eurprd04.prod.outlook.com>

On 2016-09-05 01:46, Meng Yi wrote:
>> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
>>
>> Since using clk_register_divider to setup the pixel clock, regmap is no longer
>> used. Regmap did take care of DCU using different endianness. Check
>> endianness using the device-tree property "big-endian" to determine the
>> location of DIV_RATIO.
>>
>> Cc: stable@vger.kernel.org
>> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
>> clock divider")
>> Reported-by: Meng Yi <meng.yi@nxp.com>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>

<snip>

> 
> Tested-by: Meng Yi <meng.yi@nxp.com>
> On LS1021A-TWR board.

Thanks, applied!

--
Stefan
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: Stefan Agner <stefan@agner.ch>
To: Meng Yi <meng.yi@nxp.com>
Cc: dri-devel@lists.freedesktop.org, alison.wang@freescale.com,
	jianwei.wang.chn@gmail.com, linux-kernel@vger.kernel.org,
	stable@vger.kernel.org
Subject: RE: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
Date: Mon, 05 Sep 2016 12:24:18 -0700	[thread overview]
Message-ID: <10c3b7b3a84d8406a7aa44867ea1a124@agner.ch> (raw)
In-Reply-To: <DB6PR0401MB2631D676D8D91B9E71566911ECE60@DB6PR0401MB2631.eurprd04.prod.outlook.com>

On 2016-09-05 01:46, Meng Yi wrote:
>> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
>>
>> Since using clk_register_divider to setup the pixel clock, regmap is no longer
>> used. Regmap did take care of DCU using different endianness. Check
>> endianness using the device-tree property "big-endian" to determine the
>> location of DIV_RATIO.
>>
>> Cc: stable@vger.kernel.org
>> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
>> clock divider")
>> Reported-by: Meng Yi <meng.yi@nxp.com>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>

<snip>

> 
> Tested-by: Meng Yi <meng.yi@nxp.com>
> On LS1021A-TWR board.

Thanks, applied!

--
Stefan

  reply	other threads:[~2016-09-05 19:29 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-02 19:07 [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider Stefan Agner
2016-09-02 19:07 ` Stefan Agner
2016-09-05  8:46 ` Meng Yi
2016-09-05  8:46   ` Meng Yi
2016-09-05 19:24   ` Stefan Agner [this message]
2016-09-05 19:24     ` Stefan Agner
  -- strict thread matches above, loose matches on Subject: below --
2016-08-11  6:54 [PATCH] drm/fsl-dcu: Fix " Meng Yi
2016-08-22  7:13 ` Meng Yi
2016-08-22 16:44   ` Stefan Agner
2016-08-23 10:16     ` Meng Yi

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