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From: Stefan Agner <stefan@agner.ch>
To: Meng Yi <meng.yi@nxp.com>
Cc: dri-devel@lists.freedesktop.org, alexander.stein@systec-electronic.com
Subject: RE: [PATCH] drm/fsl-dcu: Fix endian issue when using clk_register_divider
Date: Mon, 22 Aug 2016 09:44:03 -0700	[thread overview]
Message-ID: <eb3b50555069e000b9c5d7aa44ed1fbe@agner.ch> (raw)
In-Reply-To: <DB6PR0401MB263108AED4ACD464D66501DBECE80@DB6PR0401MB2631.eurprd04.prod.outlook.com>

On 2016-08-22 00:13, Meng Yi wrote:
>>  	fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
>>  			pix_clk_in_name, 0, base + DCU_DIV_RATIO,
>> -			0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
>> +			24, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
> 
> Tested-by: Meng Yi <meng.yi@nxp.com>
> 
> On LS1021A-TWR board.

Yeah I wanted to give this a try on Vybrid, but I don't think that works
since on Vybrid the IP is little endian...

We need to come up with a solution which takes that into account.
Alternatively we can put the offset into the SoC specific structure...

--
Stefan

> 
>>  	if (IS_ERR(fsl_dev->pix_clk)) {
>>  		dev_err(dev, "failed to register pix clk\n");
>>  		ret = PTR_ERR(fsl_dev->pix_clk);
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  reply	other threads:[~2016-08-22 16:57 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-11  6:54 [PATCH] drm/fsl-dcu: Fix endian issue when using clk_register_divider Meng Yi
2016-08-22  7:13 ` Meng Yi
2016-08-22 16:44   ` Stefan Agner [this message]
2016-08-23 10:16     ` Meng Yi
  -- strict thread matches above, loose matches on Subject: below --
2016-09-02 19:07 [PATCH] drm/fsl-dcu: fix " Stefan Agner
2016-09-02 19:07 ` Stefan Agner
2016-09-05  8:46 ` Meng Yi
2016-09-05  8:46   ` Meng Yi
2016-09-05 19:24   ` Stefan Agner
2016-09-05 19:24     ` Stefan Agner

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