* [PATCH 1/5] drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0
@ 2016-11-09 7:41 Rex Zhu
[not found] ` <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Rex Zhu @ 2016-11-09 7:41 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: I99b307d2026d6fec0b5b18349455df2c38d78c6a
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 15 ---------------
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 18 ++----------------
2 files changed, 2 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 95303e2..dadb6ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -724,19 +724,6 @@ static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
}
#endif
-static void uvd_v5_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
-{
- u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
-
- if (enable)
- tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
- GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
- else
- tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
- GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
-
- WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
-}
static int uvd_v5_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
@@ -745,8 +732,6 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
static int curstate = -1;
- uvd_v5_0_set_bypass_mode(adev, enable);
-
if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index a339b5c..00fad69 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -151,6 +151,8 @@ static int uvd_v6_0_hw_init(void *handle)
uint32_t tmp;
int r;
+ amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
+
r = uvd_v6_0_start(adev);
if (r)
goto done;
@@ -935,28 +937,12 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
}
#endif
-static void uvd_v6_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
-{
- u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
-
- if (enable)
- tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
- GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
- else
- tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
- GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
-
- WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
-}
-
static int uvd_v6_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
- uvd_v6_0_set_bypass_mode(adev, enable);
-
if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
return 0;
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread[parent not found: <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>]
* [PATCH 2/5] drm/amd/powerplay: partial revert commit 01b0e7fb1. [not found] ` <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2016-11-09 7:41 ` Rex Zhu 2016-11-09 7:41 ` [PATCH 3/5] drm/amdgpu: refine uvd 5.0 clock gate feature Rex Zhu ` (2 subsequent siblings) 3 siblings, 0 replies; 7+ messages in thread From: Rex Zhu @ 2016-11-09 7:41 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu when uvd is idle, we gate uvd clock. and uvd is busy, we ungate uvd clock. Change-Id: Ic2fa6149389b0113faf36ec7aad857e77d01af33 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c index cf2ee93..a1fc4fc 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c @@ -149,7 +149,7 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) if (bgate) { cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_UNGATE); + AMD_CG_STATE_GATE); cgs_set_powergating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, AMD_PG_STATE_GATE); @@ -162,7 +162,7 @@ int smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) AMD_CG_STATE_UNGATE); cgs_set_clockgating_state(hwmgr->device, AMD_IP_BLOCK_TYPE_UVD, - AMD_CG_STATE_GATE); + AMD_CG_STATE_UNGATE); smu7_update_uvd_dpm(hwmgr, false); } -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/5] drm/amdgpu: refine uvd 5.0 clock gate feature. [not found] ` <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2016-11-09 7:41 ` [PATCH 2/5] drm/amd/powerplay: partial revert commit 01b0e7fb1 Rex Zhu @ 2016-11-09 7:41 ` Rex Zhu 2016-11-09 7:41 ` [PATCH 4/5] drm/amdgpu: refine uvd 6.0 " Rex Zhu 2016-11-09 7:41 ` [PATCH 5/5] drm/amdgpu: enable uvd mgcg for Fiji Rex Zhu 3 siblings, 0 replies; 7+ messages in thread From: Rex Zhu @ 2016-11-09 7:41 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu 1. fix uvd cg status not correct. 2. fix uvd pg can't work on tonga. 3. enable uvd mgcg. Change-Id: Ia3911f2bd0f982e2fd00a9041ec03f47ab5338ed Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> --- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 106 ++++++++++++++++++++++++++-------- 1 file changed, 83 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index dadb6ab..95cabea 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -40,7 +40,10 @@ static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v5_0_start(struct amdgpu_device *adev); static void uvd_v5_0_stop(struct amdgpu_device *adev); - +static int uvd_v5_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state); +static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, + bool enable); /** * uvd_v5_0_ring_get_rptr - get read pointer * @@ -149,9 +152,6 @@ static int uvd_v5_0_hw_init(void *handle) uint32_t tmp; int r; - /* raise clocks while booting up the VCPU */ - amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); - r = uvd_v5_0_start(adev); if (r) goto done; @@ -189,11 +189,7 @@ static int uvd_v5_0_hw_init(void *handle) amdgpu_ring_write(ring, 3); amdgpu_ring_commit(ring); - done: - /* lower clocks again */ - amdgpu_asic_set_uvd_clocks(adev, 0, 0); - if (!r) DRM_INFO("UVD initialized successfully.\n"); @@ -226,6 +222,7 @@ static int uvd_v5_0_suspend(void *handle) r = uvd_v5_0_hw_fini(adev); if (r) return r; + uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); r = amdgpu_uvd_suspend(adev); if (r) @@ -313,8 +310,9 @@ static int uvd_v5_0_start(struct amdgpu_device *adev) uvd_v5_0_mc_resume(adev); - /* disable clock gating */ - WREG32(mmUVD_CGC_GATE, 0); + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); + uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); + uvd_v5_0_enable_mgcg(adev, true); /* disable interupt */ WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); @@ -628,16 +626,12 @@ static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, return 0; } -static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) +static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) { - uint32_t data, data1, data2, suvd_flags; + uint32_t data1, data3, suvd_flags; - data = RREG32(mmUVD_CGC_CTRL); data1 = RREG32(mmUVD_SUVD_CGC_GATE); - data2 = RREG32(mmUVD_SUVD_CGC_CTRL); - - data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | - UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); + data3 = RREG32(mmUVD_CGC_GATE); suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | UVD_SUVD_CGC_GATE__SIT_MASK | @@ -645,6 +639,49 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) UVD_SUVD_CGC_GATE__SCM_MASK | UVD_SUVD_CGC_GATE__SDB_MASK; + if (enable) { + data3 |= (UVD_CGC_GATE__SYS_MASK | + UVD_CGC_GATE__UDEC_MASK | + UVD_CGC_GATE__MPEG2_MASK | + UVD_CGC_GATE__RBC_MASK | + UVD_CGC_GATE__LMI_MC_MASK | + UVD_CGC_GATE__IDCT_MASK | + UVD_CGC_GATE__MPRD_MASK | + UVD_CGC_GATE__MPC_MASK | + UVD_CGC_GATE__LBSI_MASK | + UVD_CGC_GATE__LRBBM_MASK | + UVD_CGC_GATE__UDEC_RE_MASK | + UVD_CGC_GATE__UDEC_CM_MASK | + UVD_CGC_GATE__UDEC_IT_MASK | + UVD_CGC_GATE__UDEC_DB_MASK | + UVD_CGC_GATE__UDEC_MP_MASK | + UVD_CGC_GATE__WCB_MASK | + UVD_CGC_GATE__VCPU_MASK | + UVD_CGC_GATE__JPEG_MASK | + UVD_CGC_GATE__SCPU_MASK); + data3 &= ~UVD_CGC_GATE__REGS_MASK; + data1 |= suvd_flags; + } else { + data3 = 0; + data1 = 0; + } + + WREG32(mmUVD_SUVD_CGC_GATE, data1); + WREG32(mmUVD_CGC_GATE, data3); +} + +static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data, data2; + + data = RREG32(mmUVD_CGC_CTRL); + data2 = RREG32(mmUVD_SUVD_CGC_CTRL); + + + data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | + UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); + + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); @@ -675,11 +712,8 @@ static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); - data1 |= suvd_flags; WREG32(mmUVD_CGC_CTRL, data); - WREG32(mmUVD_CGC_GATE, 0); - WREG32(mmUVD_SUVD_CGC_GATE, data1); WREG32(mmUVD_SUVD_CGC_CTRL, data2); } @@ -724,6 +758,31 @@ static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) } #endif +static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, + bool enable) +{ + u32 orig, data; + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data |= 0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); + + orig = data = RREG32(mmUVD_CGC_CTRL); + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } else { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data &= ~0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); + + orig = data = RREG32(mmUVD_CGC_CTRL); + data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } +} static int uvd_v5_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) @@ -740,17 +799,18 @@ static int uvd_v5_0_set_clockgating_state(void *handle, curstate = state; if (enable) { - /* disable HW gating and enable Sw gating */ - uvd_v5_0_set_sw_clock_gating(adev); - } else { /* wait for STATUS to clear */ if (uvd_v5_0_wait_for_idle(handle)) return -EBUSY; + uvd_v5_0_enable_clock_gating(adev, true); /* enable HW gates because UVD is idle */ /* uvd_v5_0_set_hw_clock_gating(adev); */ + } else { + uvd_v5_0_enable_clock_gating(adev, false); } + uvd_v5_0_set_sw_clock_gating(adev); return 0; } -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/5] drm/amdgpu: refine uvd 6.0 clock gate feature. [not found] ` <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2016-11-09 7:41 ` [PATCH 2/5] drm/amd/powerplay: partial revert commit 01b0e7fb1 Rex Zhu 2016-11-09 7:41 ` [PATCH 3/5] drm/amdgpu: refine uvd 5.0 clock gate feature Rex Zhu @ 2016-11-09 7:41 ` Rex Zhu [not found] ` <1478677305-12579-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2016-11-09 7:41 ` [PATCH 5/5] drm/amdgpu: enable uvd mgcg for Fiji Rex Zhu 3 siblings, 1 reply; 7+ messages in thread From: Rex Zhu @ 2016-11-09 7:41 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu Change-Id: I3b665f26689dd35750e1a6521cd5fac5456f7556 Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 112 ++++++++++++++++++++++++++++------ 1 file changed, 92 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 00fad69..c697a73 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -42,6 +42,10 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev); static int uvd_v6_0_start(struct amdgpu_device *adev); static void uvd_v6_0_stop(struct amdgpu_device *adev); static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); +static int uvd_v6_0_set_clockgating_state(void *handle, + enum amd_clockgating_state state); +static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, + bool enable); /** * uvd_v6_0_ring_get_rptr - get read pointer @@ -151,8 +155,6 @@ static int uvd_v6_0_hw_init(void *handle) uint32_t tmp; int r; - amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); - r = uvd_v6_0_start(adev); if (r) goto done; @@ -395,11 +397,11 @@ static int uvd_v6_0_start(struct amdgpu_device *adev) lmi_swap_cntl = 0; mp_swap_cntl = 0; + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); + uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); + uvd_v6_0_enable_mgcg(adev, true); uvd_v6_0_mc_resume(adev); - /* disable clock gating */ - WREG32_FIELD(UVD_CGC_CTRL, DYN_CLOCK_MODE, 0); - /* disable interupt */ WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); @@ -838,22 +840,69 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, return 0; } +static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) +{ + uint32_t data1, data3; + + data1 = RREG32(mmUVD_SUVD_CGC_GATE); + data3 = RREG32(mmUVD_CGC_GATE); + + data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | + UVD_SUVD_CGC_GATE__SIT_MASK | + UVD_SUVD_CGC_GATE__SMP_MASK | + UVD_SUVD_CGC_GATE__SCM_MASK | + UVD_SUVD_CGC_GATE__SDB_MASK | + UVD_SUVD_CGC_GATE__SRE_H264_MASK | + UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | + UVD_SUVD_CGC_GATE__SIT_H264_MASK | + UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | + UVD_SUVD_CGC_GATE__SCM_H264_MASK | + UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | + UVD_SUVD_CGC_GATE__SDB_H264_MASK | + UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; + + if (enable) { + data3 |= (UVD_CGC_GATE__SYS_MASK | + UVD_CGC_GATE__UDEC_MASK | + UVD_CGC_GATE__MPEG2_MASK | + UVD_CGC_GATE__RBC_MASK | + UVD_CGC_GATE__LMI_MC_MASK | + UVD_CGC_GATE__LMI_UMC_MASK | + UVD_CGC_GATE__IDCT_MASK | + UVD_CGC_GATE__MPRD_MASK | + UVD_CGC_GATE__MPC_MASK | + UVD_CGC_GATE__LBSI_MASK | + UVD_CGC_GATE__LRBBM_MASK | + UVD_CGC_GATE__UDEC_RE_MASK | + UVD_CGC_GATE__UDEC_CM_MASK | + UVD_CGC_GATE__UDEC_IT_MASK | + UVD_CGC_GATE__UDEC_DB_MASK | + UVD_CGC_GATE__UDEC_MP_MASK | + UVD_CGC_GATE__WCB_MASK | + UVD_CGC_GATE__VCPU_MASK | + UVD_CGC_GATE__JPEG_MASK | + UVD_CGC_GATE__SCPU_MASK | + UVD_CGC_GATE__JPEG2_MASK); + data3 &= ~UVD_CGC_GATE__REGS_MASK; + } else { + data3 = 0; + } + + WREG32(mmUVD_SUVD_CGC_GATE, data1); + WREG32(mmUVD_CGC_GATE, data3); +} + static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) { - uint32_t data, data1, data2, suvd_flags; + uint32_t data, data2; data = RREG32(mmUVD_CGC_CTRL); - data1 = RREG32(mmUVD_SUVD_CGC_GATE); data2 = RREG32(mmUVD_SUVD_CGC_CTRL); + data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); - suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | - UVD_SUVD_CGC_GATE__SIT_MASK | - UVD_SUVD_CGC_GATE__SMP_MASK | - UVD_SUVD_CGC_GATE__SCM_MASK | - UVD_SUVD_CGC_GATE__SDB_MASK; data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | @@ -886,11 +935,8 @@ static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); - data1 |= suvd_flags; WREG32(mmUVD_CGC_CTRL, data); - WREG32(mmUVD_CGC_GATE, 0); - WREG32(mmUVD_SUVD_CGC_GATE, data1); WREG32(mmUVD_SUVD_CGC_CTRL, data2); } @@ -937,6 +983,32 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev) } #endif +static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, + bool enable) +{ + u32 orig, data; + + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data |= 0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); + + orig = data = RREG32(mmUVD_CGC_CTRL); + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } else { + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); + data &= ~0xfff; + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); + + orig = data = RREG32(mmUVD_CGC_CTRL); + data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; + if (orig != data) + WREG32(mmUVD_CGC_CTRL, data); + } +} + static int uvd_v6_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { @@ -947,17 +1019,17 @@ static int uvd_v6_0_set_clockgating_state(void *handle, return 0; if (enable) { - /* disable HW gating and enable Sw gating */ - uvd_v6_0_set_sw_clock_gating(adev); - } else { /* wait for STATUS to clear */ if (uvd_v6_0_wait_for_idle(handle)) return -EBUSY; - + uvd_v6_0_enable_clock_gating(adev, true); /* enable HW gates because UVD is idle */ /* uvd_v6_0_set_hw_clock_gating(adev); */ + } else { + /* disable HW gating and enable Sw gating */ + uvd_v6_0_enable_clock_gating(adev, false); } - + uvd_v6_0_set_sw_clock_gating(adev); return 0; } -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
[parent not found: <1478677305-12579-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>]
* RE: [PATCH 4/5] drm/amdgpu: refine uvd 6.0 clock gate feature. [not found] ` <1478677305-12579-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2016-11-09 16:03 ` Deucher, Alexander [not found] ` <MWHPR12MB169470FE725F398CB38380C7F7B90-Gy0DoCVfaSW4WA4dJ5YXGAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> 0 siblings, 1 reply; 7+ messages in thread From: Deucher, Alexander @ 2016-11-09 16:03 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Zhu, Rex > -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Wednesday, November 09, 2016 2:42 AM > To: amd-gfx@lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH 4/5] drm/amdgpu: refine uvd 6.0 clock gate feature. > > Change-Id: I3b665f26689dd35750e1a6521cd5fac5456f7556 > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Can someone make sure this doesn't regress CZ and ST? As long as they are still ok, the patches 4, 5 are: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 112 > ++++++++++++++++++++++++++++------ > 1 file changed, 92 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > index 00fad69..c697a73 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > @@ -42,6 +42,10 @@ static void uvd_v6_0_set_irq_funcs(struct > amdgpu_device *adev); > static int uvd_v6_0_start(struct amdgpu_device *adev); > static void uvd_v6_0_stop(struct amdgpu_device *adev); > static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); > +static int uvd_v6_0_set_clockgating_state(void *handle, > + enum amd_clockgating_state state); > +static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, > + bool enable); > > /** > * uvd_v6_0_ring_get_rptr - get read pointer > @@ -151,8 +155,6 @@ static int uvd_v6_0_hw_init(void *handle) > uint32_t tmp; > int r; > > - amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); > - > r = uvd_v6_0_start(adev); > if (r) > goto done; > @@ -395,11 +397,11 @@ static int uvd_v6_0_start(struct amdgpu_device > *adev) > lmi_swap_cntl = 0; > mp_swap_cntl = 0; > > + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); > + uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); > + uvd_v6_0_enable_mgcg(adev, true); > uvd_v6_0_mc_resume(adev); > > - /* disable clock gating */ > - WREG32_FIELD(UVD_CGC_CTRL, DYN_CLOCK_MODE, 0); > - > /* disable interupt */ > WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); > > @@ -838,22 +840,69 @@ static int uvd_v6_0_process_interrupt(struct > amdgpu_device *adev, > return 0; > } > > +static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, > bool enable) > +{ > + uint32_t data1, data3; > + > + data1 = RREG32(mmUVD_SUVD_CGC_GATE); > + data3 = RREG32(mmUVD_CGC_GATE); > + > + data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | > + UVD_SUVD_CGC_GATE__SIT_MASK | > + UVD_SUVD_CGC_GATE__SMP_MASK | > + UVD_SUVD_CGC_GATE__SCM_MASK | > + UVD_SUVD_CGC_GATE__SDB_MASK | > + UVD_SUVD_CGC_GATE__SRE_H264_MASK | > + UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | > + UVD_SUVD_CGC_GATE__SIT_H264_MASK | > + UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | > + UVD_SUVD_CGC_GATE__SCM_H264_MASK | > + UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | > + UVD_SUVD_CGC_GATE__SDB_H264_MASK | > + UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; > + > + if (enable) { > + data3 |= (UVD_CGC_GATE__SYS_MASK | > + UVD_CGC_GATE__UDEC_MASK | > + UVD_CGC_GATE__MPEG2_MASK | > + UVD_CGC_GATE__RBC_MASK | > + UVD_CGC_GATE__LMI_MC_MASK | > + UVD_CGC_GATE__LMI_UMC_MASK | > + UVD_CGC_GATE__IDCT_MASK | > + UVD_CGC_GATE__MPRD_MASK | > + UVD_CGC_GATE__MPC_MASK | > + UVD_CGC_GATE__LBSI_MASK | > + UVD_CGC_GATE__LRBBM_MASK | > + UVD_CGC_GATE__UDEC_RE_MASK | > + UVD_CGC_GATE__UDEC_CM_MASK | > + UVD_CGC_GATE__UDEC_IT_MASK | > + UVD_CGC_GATE__UDEC_DB_MASK | > + UVD_CGC_GATE__UDEC_MP_MASK | > + UVD_CGC_GATE__WCB_MASK | > + UVD_CGC_GATE__VCPU_MASK | > + UVD_CGC_GATE__JPEG_MASK | > + UVD_CGC_GATE__SCPU_MASK | > + UVD_CGC_GATE__JPEG2_MASK); > + data3 &= ~UVD_CGC_GATE__REGS_MASK; > + } else { > + data3 = 0; > + } > + > + WREG32(mmUVD_SUVD_CGC_GATE, data1); > + WREG32(mmUVD_CGC_GATE, data3); > +} > + > static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) > { > - uint32_t data, data1, data2, suvd_flags; > + uint32_t data, data2; > > data = RREG32(mmUVD_CGC_CTRL); > - data1 = RREG32(mmUVD_SUVD_CGC_GATE); > data2 = RREG32(mmUVD_SUVD_CGC_CTRL); > > + > data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | > UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); > > - suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | > - UVD_SUVD_CGC_GATE__SIT_MASK | > - UVD_SUVD_CGC_GATE__SMP_MASK | > - UVD_SUVD_CGC_GATE__SCM_MASK | > - UVD_SUVD_CGC_GATE__SDB_MASK; > > data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | > (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, > CLK_GATE_DLY_TIMER)) | > @@ -886,11 +935,8 @@ static void uvd_v6_0_set_sw_clock_gating(struct > amdgpu_device *adev) > UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | > UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | > UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); > - data1 |= suvd_flags; > > WREG32(mmUVD_CGC_CTRL, data); > - WREG32(mmUVD_CGC_GATE, 0); > - WREG32(mmUVD_SUVD_CGC_GATE, data1); > WREG32(mmUVD_SUVD_CGC_CTRL, data2); > } > > @@ -937,6 +983,32 @@ static void uvd_v6_0_set_hw_clock_gating(struct > amdgpu_device *adev) > } > #endif > > +static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, > + bool enable) > +{ > + u32 orig, data; > + > + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) > { > + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); > + data |= 0xfff; > + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); > + > + orig = data = RREG32(mmUVD_CGC_CTRL); > + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; > + if (orig != data) > + WREG32(mmUVD_CGC_CTRL, data); > + } else { > + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); > + data &= ~0xfff; > + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); > + > + orig = data = RREG32(mmUVD_CGC_CTRL); > + data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; > + if (orig != data) > + WREG32(mmUVD_CGC_CTRL, data); > + } > +} > + > static int uvd_v6_0_set_clockgating_state(void *handle, > enum amd_clockgating_state state) > { > @@ -947,17 +1019,17 @@ static int uvd_v6_0_set_clockgating_state(void > *handle, > return 0; > > if (enable) { > - /* disable HW gating and enable Sw gating */ > - uvd_v6_0_set_sw_clock_gating(adev); > - } else { > /* wait for STATUS to clear */ > if (uvd_v6_0_wait_for_idle(handle)) > return -EBUSY; > - > + uvd_v6_0_enable_clock_gating(adev, true); > /* enable HW gates because UVD is idle */ > /* uvd_v6_0_set_hw_clock_gating(adev); */ > + } else { > + /* disable HW gating and enable Sw gating */ > + uvd_v6_0_enable_clock_gating(adev, false); > } > - > + uvd_v6_0_set_sw_clock_gating(adev); > return 0; > } > > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
[parent not found: <MWHPR12MB169470FE725F398CB38380C7F7B90-Gy0DoCVfaSW4WA4dJ5YXGAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH 4/5] drm/amdgpu: refine uvd 6.0 clock gate feature. [not found] ` <MWHPR12MB169470FE725F398CB38380C7F7B90-Gy0DoCVfaSW4WA4dJ5YXGAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> @ 2016-11-09 17:38 ` StDenis, Tom 0 siblings, 0 replies; 7+ messages in thread From: StDenis, Tom @ 2016-11-09 17:38 UTC (permalink / raw) To: Deucher, Alexander, Zhu, Rex, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org [-- Attachment #1.1: Type: text/plain, Size: 9273 bytes --] Kinda buried trying to sort out the gfx6 boot failure but if someone can just email as an attachment the 5 patches I'll test them on my Stoney system (my CZ system is being used by the Tahiti board...) Tom ________________________________ From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org> Sent: Wednesday, November 9, 2016 11:03 To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Zhu, Rex Subject: RE: [PATCH 4/5] drm/amdgpu: refine uvd 6.0 clock gate feature. > -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf > Of Rex Zhu > Sent: Wednesday, November 09, 2016 2:42 AM > To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > Cc: Zhu, Rex > Subject: [PATCH 4/5] drm/amdgpu: refine uvd 6.0 clock gate feature. > > Change-Id: I3b665f26689dd35750e1a6521cd5fac5456f7556 > Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> Can someone make sure this doesn't regress CZ and ST? As long as they are still ok, the patches 4, 5 are: Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org> > --- > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 112 > ++++++++++++++++++++++++++++------ > 1 file changed, 92 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > index 00fad69..c697a73 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > @@ -42,6 +42,10 @@ static void uvd_v6_0_set_irq_funcs(struct > amdgpu_device *adev); > static int uvd_v6_0_start(struct amdgpu_device *adev); > static void uvd_v6_0_stop(struct amdgpu_device *adev); > static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev); > +static int uvd_v6_0_set_clockgating_state(void *handle, > + enum amd_clockgating_state state); > +static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, > + bool enable); > > /** > * uvd_v6_0_ring_get_rptr - get read pointer > @@ -151,8 +155,6 @@ static int uvd_v6_0_hw_init(void *handle) > uint32_t tmp; > int r; > > - amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); > - > r = uvd_v6_0_start(adev); > if (r) > goto done; > @@ -395,11 +397,11 @@ static int uvd_v6_0_start(struct amdgpu_device > *adev) > lmi_swap_cntl = 0; > mp_swap_cntl = 0; > > + amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); > + uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); > + uvd_v6_0_enable_mgcg(adev, true); > uvd_v6_0_mc_resume(adev); > > - /* disable clock gating */ > - WREG32_FIELD(UVD_CGC_CTRL, DYN_CLOCK_MODE, 0); > - > /* disable interupt */ > WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); > > @@ -838,22 +840,69 @@ static int uvd_v6_0_process_interrupt(struct > amdgpu_device *adev, > return 0; > } > > +static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, > bool enable) > +{ > + uint32_t data1, data3; > + > + data1 = RREG32(mmUVD_SUVD_CGC_GATE); > + data3 = RREG32(mmUVD_CGC_GATE); > + > + data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | > + UVD_SUVD_CGC_GATE__SIT_MASK | > + UVD_SUVD_CGC_GATE__SMP_MASK | > + UVD_SUVD_CGC_GATE__SCM_MASK | > + UVD_SUVD_CGC_GATE__SDB_MASK | > + UVD_SUVD_CGC_GATE__SRE_H264_MASK | > + UVD_SUVD_CGC_GATE__SRE_HEVC_MASK | > + UVD_SUVD_CGC_GATE__SIT_H264_MASK | > + UVD_SUVD_CGC_GATE__SIT_HEVC_MASK | > + UVD_SUVD_CGC_GATE__SCM_H264_MASK | > + UVD_SUVD_CGC_GATE__SCM_HEVC_MASK | > + UVD_SUVD_CGC_GATE__SDB_H264_MASK | > + UVD_SUVD_CGC_GATE__SDB_HEVC_MASK; > + > + if (enable) { > + data3 |= (UVD_CGC_GATE__SYS_MASK | > + UVD_CGC_GATE__UDEC_MASK | > + UVD_CGC_GATE__MPEG2_MASK | > + UVD_CGC_GATE__RBC_MASK | > + UVD_CGC_GATE__LMI_MC_MASK | > + UVD_CGC_GATE__LMI_UMC_MASK | > + UVD_CGC_GATE__IDCT_MASK | > + UVD_CGC_GATE__MPRD_MASK | > + UVD_CGC_GATE__MPC_MASK | > + UVD_CGC_GATE__LBSI_MASK | > + UVD_CGC_GATE__LRBBM_MASK | > + UVD_CGC_GATE__UDEC_RE_MASK | > + UVD_CGC_GATE__UDEC_CM_MASK | > + UVD_CGC_GATE__UDEC_IT_MASK | > + UVD_CGC_GATE__UDEC_DB_MASK | > + UVD_CGC_GATE__UDEC_MP_MASK | > + UVD_CGC_GATE__WCB_MASK | > + UVD_CGC_GATE__VCPU_MASK | > + UVD_CGC_GATE__JPEG_MASK | > + UVD_CGC_GATE__SCPU_MASK | > + UVD_CGC_GATE__JPEG2_MASK); > + data3 &= ~UVD_CGC_GATE__REGS_MASK; > + } else { > + data3 = 0; > + } > + > + WREG32(mmUVD_SUVD_CGC_GATE, data1); > + WREG32(mmUVD_CGC_GATE, data3); > +} > + > static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev) > { > - uint32_t data, data1, data2, suvd_flags; > + uint32_t data, data2; > > data = RREG32(mmUVD_CGC_CTRL); > - data1 = RREG32(mmUVD_SUVD_CGC_GATE); > data2 = RREG32(mmUVD_SUVD_CGC_CTRL); > > + > data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | > UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); > > - suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | > - UVD_SUVD_CGC_GATE__SIT_MASK | > - UVD_SUVD_CGC_GATE__SMP_MASK | > - UVD_SUVD_CGC_GATE__SCM_MASK | > - UVD_SUVD_CGC_GATE__SDB_MASK; > > data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | > (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, > CLK_GATE_DLY_TIMER)) | > @@ -886,11 +935,8 @@ static void uvd_v6_0_set_sw_clock_gating(struct > amdgpu_device *adev) > UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | > UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | > UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); > - data1 |= suvd_flags; > > WREG32(mmUVD_CGC_CTRL, data); > - WREG32(mmUVD_CGC_GATE, 0); > - WREG32(mmUVD_SUVD_CGC_GATE, data1); > WREG32(mmUVD_SUVD_CGC_CTRL, data2); > } > > @@ -937,6 +983,32 @@ static void uvd_v6_0_set_hw_clock_gating(struct > amdgpu_device *adev) > } > #endif > > +static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev, > + bool enable) > +{ > + u32 orig, data; > + > + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) > { > + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); > + data |= 0xfff; > + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); > + > + orig = data = RREG32(mmUVD_CGC_CTRL); > + data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; > + if (orig != data) > + WREG32(mmUVD_CGC_CTRL, data); > + } else { > + data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); > + data &= ~0xfff; > + WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); > + > + orig = data = RREG32(mmUVD_CGC_CTRL); > + data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; > + if (orig != data) > + WREG32(mmUVD_CGC_CTRL, data); > + } > +} > + > static int uvd_v6_0_set_clockgating_state(void *handle, > enum amd_clockgating_state state) > { > @@ -947,17 +1019,17 @@ static int uvd_v6_0_set_clockgating_state(void > *handle, > return 0; > > if (enable) { > - /* disable HW gating and enable Sw gating */ > - uvd_v6_0_set_sw_clock_gating(adev); > - } else { > /* wait for STATUS to clear */ > if (uvd_v6_0_wait_for_idle(handle)) > return -EBUSY; > - > + uvd_v6_0_enable_clock_gating(adev, true); > /* enable HW gates because UVD is idle */ > /* uvd_v6_0_set_hw_clock_gating(adev); */ > + } else { > + /* disable HW gating and enable Sw gating */ > + uvd_v6_0_enable_clock_gating(adev, false); > } > - > + uvd_v6_0_set_sw_clock_gating(adev); > return 0; > } > > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx [-- Attachment #1.2: Type: text/html, Size: 20654 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 5/5] drm/amdgpu: enable uvd mgcg for Fiji. [not found] ` <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> ` (2 preceding siblings ...) 2016-11-09 7:41 ` [PATCH 4/5] drm/amdgpu: refine uvd 6.0 " Rex Zhu @ 2016-11-09 7:41 ` Rex Zhu 3 siblings, 0 replies; 7+ messages in thread From: Rex Zhu @ 2016-11-09 7:41 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu Change-Id: I96b937c8b97589d1f98a8351f3653b89163c84a0 Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> --- drivers/gpu/drm/amd/amdgpu/vi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index a230b39..d09c25a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -927,7 +927,8 @@ static int vi_common_early_init(void *handle) AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_ROM_MGCG | AMD_CG_SUPPORT_MC_MGCG | - AMD_CG_SUPPORT_MC_LS; + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_UVD_MGCG; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x3c; break; -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-11-09 17:38 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-11-09 7:41 [PATCH 1/5] drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0 Rex Zhu
[not found] ` <1478677305-12579-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2016-11-09 7:41 ` [PATCH 2/5] drm/amd/powerplay: partial revert commit 01b0e7fb1 Rex Zhu
2016-11-09 7:41 ` [PATCH 3/5] drm/amdgpu: refine uvd 5.0 clock gate feature Rex Zhu
2016-11-09 7:41 ` [PATCH 4/5] drm/amdgpu: refine uvd 6.0 " Rex Zhu
[not found] ` <1478677305-12579-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2016-11-09 16:03 ` Deucher, Alexander
[not found] ` <MWHPR12MB169470FE725F398CB38380C7F7B90-Gy0DoCVfaSW4WA4dJ5YXGAdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-11-09 17:38 ` StDenis, Tom
2016-11-09 7:41 ` [PATCH 5/5] drm/amdgpu: enable uvd mgcg for Fiji Rex Zhu
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.