From: Sricharan R <sricharan@codeaurora.org>
To: mark.rutland@arm.com, robh@kernel.org, sudeep.holla@arm.com,
linux@arm.linux.org.uk, ctatlor97@gmail.com, rjw@rjwysocki.net,
viresh.kumar@linaro.org, mturquette@baylibre.com,
linux-pm@vger.kernel.org, sboyd@codeaurora.org,
linux@armlinux.org.uk, thierry.escande@linaro.org,
linux-kernel@vger.kernel.org, david.brown@linaro.org,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
andy.gross@linaro.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
niklas.cassel@linaro.org
Cc: sricharan@codeaurora.org
Subject: [PATCH v12 08/14] clk: qcom: Add KPSS ACC/GCC driver
Date: Tue, 14 Aug 2018 17:42:27 +0530 [thread overview]
Message-ID: <1534248753-2440-9-git-send-email-sricharan@codeaurora.org> (raw)
In-Reply-To: <1534248753-2440-1-git-send-email-sricharan@codeaurora.org>
From: Stephen Boyd <sboyd@codeaurora.org>
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 8 +++++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/kpss-xcc.c | 87 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 96 insertions(+)
create mode 100644 drivers/clk/qcom/kpss-xcc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ada4160..7a99627 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -281,6 +281,14 @@ config QCOM_HFPLL
Say Y if you want to support CPU frequency scaling on devices
such as MSM8974, APQ8084, etc.
+config KPSS_XCC
+ tristate "KPSS Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the Krait ACC and GCC clock controllers. Say Y
+ if you want to support CPU frequency scaling on devices such
+ as MSM8960, APQ8064, etc.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 506c4cf..92310ee 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -45,4 +45,5 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c
new file mode 100644
index 0000000..8590b5e
--- /dev/null
+++ b/drivers/clk/qcom/kpss-xcc.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+
+static const char *aux_parents[] = {
+ "pll8_vote",
+ "pxo",
+};
+
+static unsigned int aux_parent_map[] = {
+ 3,
+ 0,
+};
+
+static const struct of_device_id kpss_xcc_match_table[] = {
+ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
+ { .compatible = "qcom,kpss-gcc" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
+
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *id;
+ struct clk *clk;
+ struct resource *res;
+ void __iomem *base;
+ const char *name;
+
+ id = of_match_device(kpss_xcc_match_table, &pdev->dev);
+ if (!id)
+ return -ENODEV;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (id->data) {
+ if (of_property_read_string_index(pdev->dev.of_node,
+ "clock-output-names",
+ 0, &name))
+ return -ENODEV;
+ base += 0x14;
+ } else {
+ name = "acpu_l2_aux";
+ base += 0x28;
+ }
+
+ clk = clk_register_mux_table(&pdev->dev, name, aux_parents,
+ ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
+ 0, aux_parent_map, NULL);
+
+ platform_set_drvdata(pdev, clk);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
+{
+ clk_unregister_mux(platform_get_drvdata(pdev));
+ return 0;
+}
+
+static struct platform_driver kpss_xcc_driver = {
+ .probe = kpss_xcc_driver_probe,
+ .remove = kpss_xcc_driver_remove,
+ .driver = {
+ .name = "kpss-xcc",
+ .of_match_table = kpss_xcc_match_table,
+ },
+};
+module_platform_driver(kpss_xcc_driver);
+
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:kpss-xcc");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: sricharan@codeaurora.org (Sricharan R)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v12 08/14] clk: qcom: Add KPSS ACC/GCC driver
Date: Tue, 14 Aug 2018 17:42:27 +0530 [thread overview]
Message-ID: <1534248753-2440-9-git-send-email-sricharan@codeaurora.org> (raw)
In-Reply-To: <1534248753-2440-1-git-send-email-sricharan@codeaurora.org>
From: Stephen Boyd <sboyd@codeaurora.org>
The ACC and GCC regions present in KPSSv1 contain registers to
control clocks and power to each Krait CPU and L2. For CPUfreq
purposes probe these devices and expose a mux clock that chooses
between PXO and PLL8.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 8 +++++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/kpss-xcc.c | 87 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 96 insertions(+)
create mode 100644 drivers/clk/qcom/kpss-xcc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ada4160..7a99627 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -281,6 +281,14 @@ config QCOM_HFPLL
Say Y if you want to support CPU frequency scaling on devices
such as MSM8974, APQ8084, etc.
+config KPSS_XCC
+ tristate "KPSS Clock Controller"
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the Krait ACC and GCC clock controllers. Say Y
+ if you want to support CPU frequency scaling on devices such
+ as MSM8960, APQ8064, etc.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 506c4cf..92310ee 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -45,4 +45,5 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/kpss-xcc.c b/drivers/clk/qcom/kpss-xcc.c
new file mode 100644
index 0000000..8590b5e
--- /dev/null
+++ b/drivers/clk/qcom/kpss-xcc.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+
+static const char *aux_parents[] = {
+ "pll8_vote",
+ "pxo",
+};
+
+static unsigned int aux_parent_map[] = {
+ 3,
+ 0,
+};
+
+static const struct of_device_id kpss_xcc_match_table[] = {
+ { .compatible = "qcom,kpss-acc-v1", .data = (void *)1UL },
+ { .compatible = "qcom,kpss-gcc" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, kpss_xcc_match_table);
+
+static int kpss_xcc_driver_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *id;
+ struct clk *clk;
+ struct resource *res;
+ void __iomem *base;
+ const char *name;
+
+ id = of_match_device(kpss_xcc_match_table, &pdev->dev);
+ if (!id)
+ return -ENODEV;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (id->data) {
+ if (of_property_read_string_index(pdev->dev.of_node,
+ "clock-output-names",
+ 0, &name))
+ return -ENODEV;
+ base += 0x14;
+ } else {
+ name = "acpu_l2_aux";
+ base += 0x28;
+ }
+
+ clk = clk_register_mux_table(&pdev->dev, name, aux_parents,
+ ARRAY_SIZE(aux_parents), 0, base, 0, 0x3,
+ 0, aux_parent_map, NULL);
+
+ platform_set_drvdata(pdev, clk);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int kpss_xcc_driver_remove(struct platform_device *pdev)
+{
+ clk_unregister_mux(platform_get_drvdata(pdev));
+ return 0;
+}
+
+static struct platform_driver kpss_xcc_driver = {
+ .probe = kpss_xcc_driver_probe,
+ .remove = kpss_xcc_driver_remove,
+ .driver = {
+ .name = "kpss-xcc",
+ .of_match_table = kpss_xcc_match_table,
+ },
+};
+module_platform_driver(kpss_xcc_driver);
+
+MODULE_DESCRIPTION("Krait Processor Sub System (KPSS) Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:kpss-xcc");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2018-08-14 12:12 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-14 12:12 [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 01/14] ARM: Add Krait L2 register accessor functions Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 02/14] clk: qcom: Add support for High-Frequency PLLs (HFPLLs) Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 03/14] clk: qcom: Add HFPLL driver Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 04/14] dt-bindings: clock: Document qcom,hfpll Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 05/14] clk: qcom: Add MSM8960/APQ8064's HFPLLs Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 06/14] clk: qcom: Add IPQ806X's HFPLLs Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 07/14] clk: qcom: Add support for Krait clocks Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` Sricharan R [this message]
2018-08-14 12:12 ` [PATCH v12 08/14] clk: qcom: Add KPSS ACC/GCC driver Sricharan R
2018-08-14 12:12 ` [PATCH v12 09/14] dt-bindings: arm: Document qcom,kpss-gcc Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 10/14] clk: qcom: Add Krait clock controller driver Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 11/14] dt-bindings: clock: Document qcom,krait-cc Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 12/14] clk: qcom: Add safe switch hook for krait mux clocks Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 13/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-17 15:09 ` Rob Herring
2018-08-17 15:09 ` Rob Herring
2018-08-17 15:09 ` Rob Herring
2018-08-20 12:45 ` Sricharan R
2018-08-20 12:45 ` Sricharan R
2018-08-14 12:12 ` [PATCH v12 14/14] cpufreq: qcom: Add support for krait based socs Sricharan R
2018-08-14 12:12 ` Sricharan R
2018-08-17 15:09 ` Rob Herring
2018-08-17 15:09 ` Rob Herring
2018-08-17 15:09 ` Rob Herring
2018-08-24 15:21 ` Niklas Cassel
2018-08-24 15:21 ` Niklas Cassel
2018-08-24 19:15 ` Niklas Cassel
2018-08-24 19:15 ` Niklas Cassel
2018-08-14 12:20 ` [PATCH V12 00/14] Krait clocks + Krait CPUfreq Sricharan R
2018-08-14 12:20 ` Sricharan R
2018-09-07 9:57 ` Sricharan R
2018-09-07 9:57 ` Sricharan R
2018-09-07 14:28 ` Craig Tatlor
2018-09-07 14:28 ` Craig Tatlor
2018-09-07 14:28 ` Craig Tatlor
2018-09-19 20:24 ` Craig
2018-09-19 20:24 ` Craig
2018-09-19 20:24 ` Craig
2018-09-20 13:01 ` Sricharan R
2018-09-20 13:01 ` Sricharan R
2018-09-20 14:27 ` Craig
2018-09-20 14:27 ` Craig
2018-09-20 14:27 ` Craig
2018-09-20 13:03 ` Sricharan R
2018-09-20 13:03 ` Sricharan R
2018-10-17 15:44 ` Stephen Boyd
2018-10-17 15:44 ` Stephen Boyd
2018-10-17 20:16 ` Stephen Boyd
2018-10-17 20:16 ` Stephen Boyd
2018-10-22 4:09 ` Sricharan R
2018-10-22 4:09 ` Sricharan R
2018-10-22 15:30 ` Niklas Cassel
2018-10-22 15:30 ` Niklas Cassel
2018-10-24 4:11 ` Sricharan R
2018-10-24 4:11 ` Sricharan R
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1534248753-2440-9-git-send-email-sricharan@codeaurora.org \
--to=sricharan@codeaurora.org \
--cc=andy.gross@linaro.org \
--cc=ctatlor97@gmail.com \
--cc=david.brown@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=linux-soc@vger.kernel.org \
--cc=linux@arm.linux.org.uk \
--cc=linux@armlinux.org.uk \
--cc=mark.rutland@arm.com \
--cc=mturquette@baylibre.com \
--cc=niklas.cassel@linaro.org \
--cc=rjw@rjwysocki.net \
--cc=robh@kernel.org \
--cc=sboyd@codeaurora.org \
--cc=sudeep.holla@arm.com \
--cc=thierry.escande@linaro.org \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.