Re: [PATCH 5/6] clk: rockchip: pll: fractional PLL coefficient is two's complement

[Quentin Schulz via U-Boot <u-boot@lists.u-boot-project.org>]

Hi Alexey,

On 7/13/26 8:35 PM, Alexey Charkov wrote:
> The TRM defines the fractional PLL adjustment coefficient as a signed
> two's complement number, 16 bits wide, so store it as such to avoid
> confusion.
> 

Yet...

> Signed-off-by: Alexey Charkov <alchark@flipper.net>
> ---
>   arch/arm/include/asm/arch-rockchip/clock.h | 2 +-
>   drivers/clk/rockchip/clk_pll.c             | 3 ++-
>   2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
> index 95b08bfd046f..f9bfdfb8a6a3 100644
> --- a/arch/arm/include/asm/arch-rockchip/clock.h
> +++ b/arch/arm/include/asm/arch-rockchip/clock.h
> @@ -104,7 +104,7 @@ struct rockchip_pll_rate_table {
>   	unsigned int m;
>   	unsigned int p;
>   	unsigned int s;
> -	unsigned int k;
> +	int k;

... you use int here instead of s16, any specific reason?

Cheers,
Quentin