From: Quentin Schulz via U-Boot <u-boot@lists.u-boot-project.org>
To: Alexey Charkov <alchark@flipper.net>,
u-boot@lists.denx.de, Elaine Zhang <zhangqing@rock-chips.com>,
Jagan Teki <jagan@edgeble.ai>
Cc: Lukasz Majewski <lukma@denx.de>, Simon Glass <sjg@chromium.org>,
Kever Yang <kever.yang@rock-chips.com>,
Tom Rini <trini@konsulko.com>,
Ilias Apalodimas <ilias.apalodimas@linaro.org>,
Finley Xiao <finley.xiao@rock-chips.com>,
Jonas Karlman <jonas@kwiboo.se>
Subject: Re: [PATCH 3/6] clk: rockchip: pll: fix RK3588 frac PLL result for k=-32768
Date: Tue, 21 Jul 2026 14:16:37 +0200 [thread overview]
Message-ID: <f2dc4c58-20a9-46d3-90ca-497d473519a3@cherry.de> (raw)
In-Reply-To: <20260713-rk3588-fracpll-v1-3-cdf47f2ca0b8@flipper.net>
Hi Alexey,
On 7/13/26 8:35 PM, Alexey Charkov wrote:
> Current code needlessly sets the k value to 0 when it is calculated as
> -32768, which is a valid value for the RK3588 frac PLL. This results in
> the PLL output frequency being higher than requested when the requested
> frequency is exactly halfway between two integer-multiplier PLL output
> frequencies.
>
> Negative k values can never go below -32768 either, because that case is
> handled just above this code, so the check for k > 32767 is redundant.
>
and because we add 1 to m, which is eventually multiplied by 65536 and
thus if k is >32767 before adding 1 to m, it can only be <=32768 after
adding 1 to m as we also invert the sign of k.
> What remains of the if statement is a hand-rolled two's complement
> negation of the result, so write it out as such for clarity, and return
> the true S16 type of k as specified in the TRM.
>
> Fixes: 6bfb37e70209 ("clk: rockchip: rk3588: fix up the frac pll calculation")
> Signed-off-by: Alexey Charkov <alchark@flipper.net>
> ---
> drivers/clk/rockchip/clk_pll.c | 10 +++-------
> 1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
> index 69d2d182dcb5..c6fbeb71c77a 100644
> --- a/drivers/clk/rockchip/clk_pll.c
> +++ b/drivers/clk/rockchip/clk_pll.c
> @@ -167,11 +167,11 @@ rockchip_pll_clk_set_by_auto(ulong fin_hz,
> return rate_table;
> }
>
> -static u32
> +static s16
> rockchip_rk3588_pll_k_get(u32 m, u32 p, u32 s, u64 fin_hz, u64 fvco)
> {
> u64 fref, ffrac;
> - u32 k = 0;
> + int k;
>
> fref = fin_hz / p;
> ffrac = fvco - (m * fref);
> @@ -181,11 +181,7 @@ rockchip_rk3588_pll_k_get(u32 m, u32 p, u32 s, u64 fin_hz, u64 fvco)
> /*
> * Round up to avoid overshooting requested rate for negative k
> */
> - k = DIV64_U64_ROUND_UP(ffrac * 65536, fref);
> - if (k > 32767)
> - k = 0;
> - else
> - k = ~k + 1;
> + k = -(int)DIV64_U64_ROUND_UP(ffrac * 65536, fref);
I don't like migrating k to s16 in multiple commits, especially since
there's also a mix of int/s16 in there. It's quite confusing.
It's kinda bad to store the return value of this function and then do
some additional based on its value and set the rate_table based on it.
Considering the next patch, I think it also itches you :)
I'm thinking to move the whole rate_table->X assignment within
rockchip_rk3588_pll_k_get(), also pass rate_table pointer as argument
and simply return 0 if it worked, 1 (or -EINVAL or whatever) otherwise
and have the for-loop return rate_table if rockchip_rk3588_pll_k_get()
returns 0.
Keep the current type when moving the assignments into the function,
then migrate rate_table->k to be an s16 (including the struct
definition) in another commit, then fix the k=-32768 case. I think it's
clearer that way and avoid implicit casts and a mix of signed and
unsigned types.
Cheers,
Quentin
next prev parent reply other threads:[~2026-07-21 12:16 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-13 18:35 [PATCH 0/6] clk: rockchip: pll: fixes and simplification of maths in RK3588 frac PLL Alexey Charkov
2026-07-13 18:35 ` [PATCH 1/6] clk: rockchip: pll: drop misleading fout in rockchip_rk3588_pll_k_get() Alexey Charkov
2026-07-21 10:09 ` Quentin Schulz via U-Boot
2026-07-13 18:35 ` [PATCH 2/6] clk: rockchip: pll: fix rounding of negative k in RK3588 frac PLL Alexey Charkov
2026-07-21 12:57 ` Quentin Schulz via U-Boot
2026-07-13 18:35 ` [PATCH 3/6] clk: rockchip: pll: fix RK3588 frac PLL result for k=-32768 Alexey Charkov
2026-07-21 12:16 ` Quentin Schulz via U-Boot [this message]
2026-07-21 12:51 ` Alexey Charkov via U-Boot
2026-07-13 18:35 ` [PATCH 4/6] clk: rockchip: pll: let rockchip_rk3588_pll_k_get update m directly Alexey Charkov
2026-07-21 12:19 ` Quentin Schulz via U-Boot
2026-07-21 12:47 ` Alexey Charkov via U-Boot
2026-07-13 18:35 ` [PATCH 5/6] clk: rockchip: pll: fractional PLL coefficient is two's complement Alexey Charkov
2026-07-21 12:20 ` Quentin Schulz via U-Boot
2026-07-21 12:46 ` Alexey Charkov via U-Boot
2026-07-21 14:34 ` Quentin Schulz via U-Boot
2026-07-21 15:21 ` Alexey Charkov via U-Boot
2026-07-21 16:34 ` Quentin Schulz via U-Boot
2026-07-21 17:27 ` Alexey Charkov via U-Boot
2026-07-13 18:35 ` [PATCH 6/6] clk: rockchip: pll: fix overflow and drop manual two's complement in rk3588_pll_get_rate Alexey Charkov
2026-07-21 12:56 ` Quentin Schulz via U-Boot
2026-07-21 13:34 ` Alexey Charkov via U-Boot
2026-07-21 14:05 ` Quentin Schulz via U-Boot
2026-07-21 16:02 ` Alexey Charkov via U-Boot
2026-07-23 9:23 ` Quentin Schulz
2026-07-23 12:25 ` Alexey Charkov
2026-07-23 12:33 ` Quentin Schulz
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