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From: <tony.nguyen@bt.com>
To: <qemu-devel@nongnu.org>
Cc: <peter.maydell@linaro.org>, <walling@linux.ibm.com>,
	<sagark@eecs.berkeley.edu>, <david@redhat.com>,
	<palmer@sifive.com>, <mark.cave-ayland@ilande.co.uk>,
	<Alistair.Francis@wdc.com>, <edgar.iglesias@gmail.com>,
	<arikalo@wavecomp.com>, <mst@redhat.com>, <pasic@linux.ibm.com>,
	<borntraeger@de.ibm.com>, <rth@twiddle.net>,
	<atar4qemu@gmail.com>, <ehabkost@redhat.com>,
	<alex.williamson@redhat.com>, <qemu-arm@nongnu.org>,
	<stefanha@redhat.com>, <shorne@gmail.com>,
	<david@gibson.dropbear.id.au>, <qemu-riscv@nongnu.org>,
	<qemu-s390x@nongnu.org>, <kbastian@mail.uni-paderborn.de>,
	<cohuck@redhat.com>, <laurent@vivier.eu>, <qemu-ppc@nongnu.org>,
	<amarkovic@wavecomp.com>, <pbonzini@redhat.com>,
	<aurelien@aurel32.net>
Subject: [Qemu-riscv] [Qemu-devel] [PATCH v5 09/15] cputlb: Access MemoryRegion with MemOp
Date: Fri, 26 Jul 2019 06:46:58 +0000	[thread overview]
Message-ID: <1564123618147.19868@bt.com> (raw)
In-Reply-To: <3106a3c959c4498fad13a5799c89ba7b@tpw09926dag18e.domain1.systemhost.net>

[-- Attachment #1: Type: text/plain, Size: 3883 bytes --]

No-op MEMOP_SIZE and SIZE_MEMOP macros allows us to later easily
convert memory_region_dispatch_{read|write} paramter "unsigned size"
into a size+sign+endianness encoded "MemOp op".

Being a no-op macro, this patch does not introduce any logical change.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 523be4c..5d88cec 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,

 static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
                          int mmu_idx, target_ulong addr, uintptr_t retaddr,
-                         MMUAccessType access_type, int size)
+                         MMUAccessType access_type, MemOp op)
 {
     CPUState *cpu = env_cpu(env);
     hwaddr mr_offset;
@@ -906,14 +906,13 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked = true;
     }
-    r = memory_region_dispatch_read(mr, mr_offset,
-                                    &val, size, iotlbentry->attrs);
+    r = memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry->attrs);
     if (r != MEMTX_OK) {
         hwaddr physaddr = mr_offset +
             section->offset_within_address_space -
             section->offset_within_region;

-        cpu_transaction_failed(cpu, physaddr, addr, size, access_type,
+        cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op), access_type,
                                mmu_idx, iotlbentry->attrs, r, retaddr);
     }
     if (locked) {
@@ -925,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,

 static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
                       int mmu_idx, uint64_t val, target_ulong addr,
-                      uintptr_t retaddr, int size)
+                      uintptr_t retaddr, MemOp op)
 {
     CPUState *cpu = env_cpu(env);
     hwaddr mr_offset;
@@ -947,15 +946,15 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked = true;
     }
-    r = memory_region_dispatch_write(mr, mr_offset,
-                                     val, size, iotlbentry->attrs);
+    r = memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry->attrs);
     if (r != MEMTX_OK) {
         hwaddr physaddr = mr_offset +
             section->offset_within_address_space -
             section->offset_within_region;

-        cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE,
-                               mmu_idx, iotlbentry->attrs, r, retaddr);
+        cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op),
+                               MMU_DATA_STORE, mmu_idx, iotlbentry->attrs, r,
+                               retaddr);
     }
     if (locked) {
         qemu_mutex_unlock_iothread();
@@ -1306,7 +1305,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
         }

         res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index],
-                       mmu_idx, addr, retaddr, access_type, size);
+                       mmu_idx, addr, retaddr, access_type, SIZE_MEMOP(size));
         return handle_bswap(res, size, big_endian);
     }

@@ -1555,7 +1554,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,

         io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx,
                   handle_bswap(val, size, big_endian),
-                  addr, retaddr, size);
+                  addr, retaddr, SIZE_MEMOP(size));
         return;
     }

--
1.8.3.1




[-- Attachment #2: Type: text/html, Size: 7626 bytes --]

WARNING: multiple messages have this Message-ID (diff)
From: <tony.nguyen@bt.com>
To: <qemu-devel@nongnu.org>
Cc: peter.maydell@linaro.org, walling@linux.ibm.com,
	sagark@eecs.berkeley.edu, mst@redhat.com, palmer@sifive.com,
	mark.cave-ayland@ilande.co.uk, laurent@vivier.eu,
	Alistair.Francis@wdc.com, edgar.iglesias@gmail.com,
	arikalo@wavecomp.com, david@redhat.com, pasic@linux.ibm.com,
	borntraeger@de.ibm.com, rth@twiddle.net, atar4qemu@gmail.com,
	ehabkost@redhat.com, qemu-s390x@nongnu.org, qemu-arm@nongnu.org,
	stefanha@redhat.com, shorne@gmail.com,
	david@gibson.dropbear.id.au, qemu-riscv@nongnu.org,
	kbastian@mail.uni-paderborn.de, cohuck@redhat.com,
	alex.williamson@redhat.com, qemu-ppc@nongnu.org,
	amarkovic@wavecomp.com, pbonzini@redhat.com,
	aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v5 09/15] cputlb: Access MemoryRegion with MemOp
Date: Fri, 26 Jul 2019 06:46:58 +0000	[thread overview]
Message-ID: <1564123618147.19868@bt.com> (raw)
In-Reply-To: <3106a3c959c4498fad13a5799c89ba7b@tpw09926dag18e.domain1.systemhost.net>

No-op MEMOP_SIZE and SIZE_MEMOP macros allows us to later easily
convert memory_region_dispatch_{read|write} paramter "unsigned size"
into a size+sign+endianness encoded "MemOp op".

Being a no-op macro, this patch does not introduce any logical change.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 523be4c..5d88cec 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,

 static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
                          int mmu_idx, target_ulong addr, uintptr_t retaddr,
-                         MMUAccessType access_type, int size)
+                         MMUAccessType access_type, MemOp op)
 {
     CPUState *cpu = env_cpu(env);
     hwaddr mr_offset;
@@ -906,14 +906,13 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked = true;
     }
-    r = memory_region_dispatch_read(mr, mr_offset,
-                                    &val, size, iotlbentry->attrs);
+    r = memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry->attrs);
     if (r != MEMTX_OK) {
         hwaddr physaddr = mr_offset +
             section->offset_within_address_space -
             section->offset_within_region;

-        cpu_transaction_failed(cpu, physaddr, addr, size, access_type,
+        cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op), access_type,
                                mmu_idx, iotlbentry->attrs, r, retaddr);
     }
     if (locked) {
@@ -925,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,

 static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
                       int mmu_idx, uint64_t val, target_ulong addr,
-                      uintptr_t retaddr, int size)
+                      uintptr_t retaddr, MemOp op)
 {
     CPUState *cpu = env_cpu(env);
     hwaddr mr_offset;
@@ -947,15 +946,15 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked = true;
     }
-    r = memory_region_dispatch_write(mr, mr_offset,
-                                     val, size, iotlbentry->attrs);
+    r = memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry->attrs);
     if (r != MEMTX_OK) {
         hwaddr physaddr = mr_offset +
             section->offset_within_address_space -
             section->offset_within_region;

-        cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE,
-                               mmu_idx, iotlbentry->attrs, r, retaddr);
+        cpu_transaction_failed(cpu, physaddr, addr, MEMOP_SIZE(op),
+                               MMU_DATA_STORE, mmu_idx, iotlbentry->attrs, r,
+                               retaddr);
     }
     if (locked) {
         qemu_mutex_unlock_iothread();
@@ -1306,7 +1305,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
         }

         res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index],
-                       mmu_idx, addr, retaddr, access_type, size);
+                       mmu_idx, addr, retaddr, access_type, SIZE_MEMOP(size));
         return handle_bswap(res, size, big_endian);
     }

@@ -1555,7 +1554,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,

         io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx,
                   handle_bswap(val, size, big_endian),
-                  addr, retaddr, size);
+                  addr, retaddr, SIZE_MEMOP(size));
         return;
     }

--
1.8.3.1



  parent reply	other threads:[~2019-07-26  6:47 UTC|newest]

Thread overview: 113+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-26  6:42 [Qemu-riscv] [Qemu-devel] [PATCH v5 00/15] Invert Endian bit in SPARCv9 MMU TTE tony.nguyen
2019-07-26  6:42 ` tony.nguyen
2019-07-26  6:43 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 01/15] tcg: TCGMemOp is now accelerator independent MemOp tony.nguyen
2019-07-26  6:43   ` tony.nguyen
2019-07-26  6:43   ` [Qemu-arm] " tony.nguyen
2019-07-26  7:43   ` [Qemu-riscv] " David Gibson
2019-07-26  7:43     ` David Gibson
2019-07-26  7:43     ` [Qemu-arm] " David Gibson
2019-07-26 13:27   ` [Qemu-riscv] " Richard Henderson
2019-07-26 13:27     ` Richard Henderson
2019-07-26 13:27     ` [Qemu-arm] " Richard Henderson
2019-07-26  6:43 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 02/15] memory: Access MemoryRegion with MemOp tony.nguyen
2019-07-26  6:43   ` tony.nguyen
2019-07-26  6:43   ` [Qemu-arm] " tony.nguyen
2019-07-26 13:36   ` [Qemu-riscv] " Richard Henderson
2019-07-26 13:36     ` Richard Henderson
2019-07-26 13:36     ` [Qemu-arm] " Richard Henderson
2019-07-26 14:04     ` [Qemu-riscv] " Richard Henderson
2019-07-26 14:04       ` Richard Henderson
2019-07-26 14:04       ` [Qemu-arm] " Richard Henderson
2019-07-26  6:44 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 03/15] target/mips: " tony.nguyen
2019-07-26  6:44   ` tony.nguyen
2019-07-26  6:44   ` [Qemu-arm] " tony.nguyen
2019-07-26 13:40   ` [Qemu-riscv] " Richard Henderson
2019-07-26 13:40     ` Richard Henderson
2019-07-26 13:40     ` [Qemu-arm] " Richard Henderson
2019-07-26  6:44 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 04/15] hw/s390x: " tony.nguyen
2019-07-26  6:44   ` tony.nguyen
2019-07-26  6:44   ` [Qemu-arm] " tony.nguyen
2019-07-26 13:42   ` [Qemu-riscv] " Richard Henderson
2019-07-26 13:42     ` Richard Henderson
2019-07-26  6:45 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 05/15] hw/intc/armv7m_nic: " tony.nguyen
2019-07-26  6:45   ` tony.nguyen
2019-07-26  6:45   ` [Qemu-arm] " tony.nguyen
2019-07-26 13:43   ` [Qemu-riscv] " Richard Henderson
2019-07-26 13:43     ` Richard Henderson
2019-07-26 13:43     ` [Qemu-arm] " Richard Henderson
2019-07-26  6:45 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 06/15] hw/virtio: " tony.nguyen
2019-07-26  6:45   ` tony.nguyen
2019-07-26  6:45   ` [Qemu-arm] " tony.nguyen
2019-07-26 13:43   ` [Qemu-riscv] " Richard Henderson
2019-07-26 13:43     ` Richard Henderson
2019-07-26 13:43     ` [Qemu-arm] " Richard Henderson
2019-07-26  6:46 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 07/15] hw/vfio: " tony.nguyen
2019-07-26  6:46   ` tony.nguyen
2019-07-26  6:46   ` [Qemu-arm] " tony.nguyen
2019-07-26 13:43   ` [Qemu-riscv] " Richard Henderson
2019-07-26 13:43     ` Richard Henderson
2019-07-26 13:43     ` [Qemu-arm] " Richard Henderson
2019-07-26  6:46 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 08/15] exec: " tony.nguyen
2019-07-26  6:46   ` tony.nguyen
2019-07-26  6:46   ` [Qemu-arm] " tony.nguyen
2019-07-26 13:46   ` [Qemu-riscv] " Richard Henderson
2019-07-26 13:46     ` Richard Henderson
2019-07-26 13:46     ` [Qemu-arm] " Richard Henderson
2019-07-26  6:46 ` tony.nguyen [this message]
2019-07-26  6:46   ` [Qemu-devel] [PATCH v5 09/15] cputlb: " tony.nguyen
2019-07-26 11:03   ` [Qemu-riscv] " Philippe Mathieu-Daudé
2019-07-26 11:03     ` Philippe Mathieu-Daudé
2019-07-26 11:03     ` [Qemu-arm] " Philippe Mathieu-Daudé
2019-07-26 11:16     ` [Qemu-riscv] [EXTERNAL]Re: " Aleksandar Markovic
2019-07-26 11:16       ` [Qemu-devel] [EXTERNAL]Re: " Aleksandar Markovic
2019-07-26 11:16       ` [Qemu-arm] [EXTERNAL]Re: [Qemu-devel] " Aleksandar Markovic
2019-07-26 11:23     ` [Qemu-riscv] " Aleksandar Markovic
2019-07-26 11:23       ` [Qemu-devel] [EXTERNAL]Re: " Aleksandar Markovic
2019-07-26 11:23       ` [Qemu-arm] [EXTERNAL]Re: [Qemu-devel] " Aleksandar Markovic
2019-07-26 14:14   ` [Qemu-riscv] " Richard Henderson
2019-07-26 14:14     ` Richard Henderson
2019-07-26 14:14     ` [Qemu-arm] " Richard Henderson
2019-07-26  6:47 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 10/15] memory: Access MemoryRegion with MemOp semantics tony.nguyen
2019-07-26  6:47   ` tony.nguyen
2019-07-26  6:47   ` [Qemu-arm] " tony.nguyen
2019-07-26 14:24   ` [Qemu-riscv] " Richard Henderson
2019-07-26 14:24     ` Richard Henderson
2019-07-26  6:47 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 11/15] memory: Single byte swap along the I/O path tony.nguyen
2019-07-26  6:47   ` tony.nguyen
2019-07-26  6:47   ` [Qemu-arm] " tony.nguyen
2019-07-26  9:26   ` [Qemu-riscv] " Paolo Bonzini
2019-07-26  9:26     ` Paolo Bonzini
2019-07-26  9:26     ` [Qemu-arm] " Paolo Bonzini
2019-07-26 14:29     ` [Qemu-riscv] " Richard Henderson
2019-07-26 14:29       ` Richard Henderson
2019-07-26 14:29       ` [Qemu-arm] " Richard Henderson
2019-07-26  9:39   ` [Qemu-riscv] " Paolo Bonzini
2019-07-26  9:39     ` Paolo Bonzini
2019-07-26  9:39     ` [Qemu-arm] " Paolo Bonzini
2019-07-26 14:45     ` [Qemu-riscv] " Richard Henderson
2019-07-26 14:45       ` Richard Henderson
2019-07-26 14:45       ` [Qemu-arm] " Richard Henderson
2019-07-26  6:48 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 12/15] cpu: TLB_FLAGS_MASK bit to force memory slow path tony.nguyen
2019-07-26  6:48   ` tony.nguyen
2019-07-26  6:48   ` [Qemu-arm] " tony.nguyen
2019-07-26 14:48   ` [Qemu-riscv] " Richard Henderson
2019-07-26 14:48     ` Richard Henderson
2019-07-26 14:48     ` [Qemu-arm] " Richard Henderson
2019-07-26  6:48 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 13/15] cputlb: Byte swap memory transaction attribute tony.nguyen
2019-07-26  6:48   ` tony.nguyen
2019-07-26  6:48   ` [Qemu-arm] " tony.nguyen
2019-07-26 14:52   ` [Qemu-riscv] " Richard Henderson
2019-07-26 14:52     ` Richard Henderson
2019-07-26 14:52     ` [Qemu-arm] " Richard Henderson
2019-07-26  6:48 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 14/15] target/sparc: Add TLB entry with attributes tony.nguyen
2019-07-26  6:48   ` tony.nguyen
2019-07-26  6:48   ` [Qemu-arm] " tony.nguyen
2019-07-26 14:55   ` [Qemu-riscv] " Richard Henderson
2019-07-26 14:55     ` Richard Henderson
2019-07-26 14:55     ` [Qemu-arm] " Richard Henderson
2019-07-26  6:49 ` [Qemu-riscv] [Qemu-devel] [PATCH v5 15/15] target/sparc: sun4u Invert Endian TTE bit tony.nguyen
2019-07-26  6:49   ` tony.nguyen
2019-07-26  6:49   ` [Qemu-arm] " tony.nguyen
2019-07-26 14:56   ` [Qemu-riscv] " Richard Henderson
2019-07-26 14:56     ` Richard Henderson
2019-07-26 14:56     ` [Qemu-arm] " Richard Henderson

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