From: guoren@kernel.org
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair.francis@wdc.com, palmer@sifive.com,
alistair23@gmail.com, Guo Ren <ren_guo@c-sky.com>
Subject: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
Date: Tue, 24 Sep 2019 13:00:32 +0800 [thread overview]
Message-ID: <1569301232-7128-1-git-send-email-guoren@kernel.org> (raw)
From: Guo Ren <ren_guo@c-sky.com>
Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They can not be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87dd6a6..3c5e8f6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -260,6 +260,7 @@ restart:
target_ulong pte = ldl_phys(cs->as, pte_addr);
#elif defined(TARGET_RISCV64)
target_ulong pte = ldq_phys(cs->as, pte_addr);
+ pte = pte << 10 >> 10;
#endif
hwaddr ppn = pte >> PTE_PPN_SHIFT;
--
2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com,
alistair.francis@wdc.com, Guo Ren <ren_guo@c-sky.com>
Subject: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
Date: Tue, 24 Sep 2019 13:00:32 +0800 [thread overview]
Message-ID: <1569301232-7128-1-git-send-email-guoren@kernel.org> (raw)
From: Guo Ren <ren_guo@c-sky.com>
Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They can not be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87dd6a6..3c5e8f6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -260,6 +260,7 @@ restart:
target_ulong pte = ldl_phys(cs->as, pte_addr);
#elif defined(TARGET_RISCV64)
target_ulong pte = ldq_phys(cs->as, pte_addr);
+ pte = pte << 10 >> 10;
#endif
hwaddr ppn = pte >> PTE_PPN_SHIFT;
--
2.7.4
next reply other threads:[~2019-09-24 13:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-24 5:00 guoren [this message]
2019-09-24 5:00 ` [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64 guoren
2019-09-24 5:03 ` Alistair Francis
2019-09-24 5:03 ` Alistair Francis
2019-09-24 7:43 ` Guo Ren
2019-09-24 7:43 ` Guo Ren
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1569301232-7128-1-git-send-email-guoren@kernel.org \
--to=guoren@kernel.org \
--cc=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=palmer@sifive.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=ren_guo@c-sky.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.