* [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
@ 2019-09-24 5:00 ` guoren
0 siblings, 0 replies; 6+ messages in thread
From: guoren @ 2019-09-24 5:00 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, palmer, alistair23, Guo Ren
From: Guo Ren <ren_guo@c-sky.com>
Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They can not be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87dd6a6..3c5e8f6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -260,6 +260,7 @@ restart:
target_ulong pte = ldl_phys(cs->as, pte_addr);
#elif defined(TARGET_RISCV64)
target_ulong pte = ldq_phys(cs->as, pte_addr);
+ pte = pte << 10 >> 10;
#endif
hwaddr ppn = pte >> PTE_PPN_SHIFT;
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
@ 2019-09-24 5:00 ` guoren
0 siblings, 0 replies; 6+ messages in thread
From: guoren @ 2019-09-24 5:00 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair23, palmer, alistair.francis, Guo Ren
From: Guo Ren <ren_guo@c-sky.com>
Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They can not be a part of ppn.
1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
4.4 Sv39: Page-Based 39-bit Virtual-Memory System
4.5 Sv48: Page-Based 48-bit Virtual-Memory System
Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/cpu_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87dd6a6..3c5e8f6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -260,6 +260,7 @@ restart:
target_ulong pte = ldl_phys(cs->as, pte_addr);
#elif defined(TARGET_RISCV64)
target_ulong pte = ldq_phys(cs->as, pte_addr);
+ pte = pte << 10 >> 10;
#endif
hwaddr ppn = pte >> PTE_PPN_SHIFT;
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
2019-09-24 5:00 ` guoren
@ 2019-09-24 5:03 ` Alistair Francis
-1 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2019-09-24 5:03 UTC (permalink / raw)
To: guoren
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Palmer Dabbelt, Guo Ren
On Mon, Sep 23, 2019 at 10:01 PM <guoren@kernel.org> wrote:
>
> From: Guo Ren <ren_guo@c-sky.com>
>
> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> need to ignore them. They can not be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> 4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> 4.5 Sv48: Page-Based 48-bit Virtual-Memory System
>
> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
> Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu_helper.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 87dd6a6..3c5e8f6 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -260,6 +260,7 @@ restart:
> target_ulong pte = ldl_phys(cs->as, pte_addr);
> #elif defined(TARGET_RISCV64)
> target_ulong pte = ldq_phys(cs->as, pte_addr);
> + pte = pte << 10 >> 10;
You can just AND with a mask instead of shifting both directions.
Alistair
> #endif
> hwaddr ppn = pte >> PTE_PPN_SHIFT;
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
@ 2019-09-24 5:03 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2019-09-24 5:03 UTC (permalink / raw)
To: guoren
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers, Guo Ren
On Mon, Sep 23, 2019 at 10:01 PM <guoren@kernel.org> wrote:
>
> From: Guo Ren <ren_guo@c-sky.com>
>
> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> need to ignore them. They can not be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> 4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> 4.5 Sv48: Page-Based 48-bit Virtual-Memory System
>
> Signed-off-by: Guo Ren <ren_guo@c-sky.com>
> Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
> ---
> target/riscv/cpu_helper.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 87dd6a6..3c5e8f6 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -260,6 +260,7 @@ restart:
> target_ulong pte = ldl_phys(cs->as, pte_addr);
> #elif defined(TARGET_RISCV64)
> target_ulong pte = ldq_phys(cs->as, pte_addr);
> + pte = pte << 10 >> 10;
You can just AND with a mask instead of shifting both directions.
Alistair
> #endif
> hwaddr ppn = pte >> PTE_PPN_SHIFT;
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
2019-09-24 5:03 ` Alistair Francis
@ 2019-09-24 7:43 ` Guo Ren
-1 siblings, 0 replies; 6+ messages in thread
From: Guo Ren @ 2019-09-24 7:43 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Palmer Dabbelt, Guo Ren
Ok, In fact it's wrong patch, don't try it. pte is destroyed.
Sorry for that, I'll send V2.
On Tue, Sep 24, 2019 at 1:03 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Mon, Sep 23, 2019 at 10:01 PM <guoren@kernel.org> wrote:
> >
> > From: Guo Ren <ren_guo@c-sky.com>
> >
> > Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> > need to ignore them. They can not be a part of ppn.
> >
> > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> > 4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> > 4.5 Sv48: Page-Based 48-bit Virtual-Memory System
> >
> > Signed-off-by: Guo Ren <ren_guo@c-sky.com>
> > Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
> > ---
> > target/riscv/cpu_helper.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 87dd6a6..3c5e8f6 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -260,6 +260,7 @@ restart:
> > target_ulong pte = ldl_phys(cs->as, pte_addr);
> > #elif defined(TARGET_RISCV64)
> > target_ulong pte = ldq_phys(cs->as, pte_addr);
> > + pte = pte << 10 >> 10;
>
> You can just AND with a mask instead of shifting both directions.
>
> Alistair
>
> > #endif
> > hwaddr ppn = pte >> PTE_PPN_SHIFT;
> >
> > --
> > 2.7.4
> >
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
@ 2019-09-24 7:43 ` Guo Ren
0 siblings, 0 replies; 6+ messages in thread
From: Guo Ren @ 2019-09-24 7:43 UTC (permalink / raw)
To: Alistair Francis
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers, Guo Ren
Ok, In fact it's wrong patch, don't try it. pte is destroyed.
Sorry for that, I'll send V2.
On Tue, Sep 24, 2019 at 1:03 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Mon, Sep 23, 2019 at 10:01 PM <guoren@kernel.org> wrote:
> >
> > From: Guo Ren <ren_guo@c-sky.com>
> >
> > Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> > need to ignore them. They can not be a part of ppn.
> >
> > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> > 4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> > 4.5 Sv48: Page-Based 48-bit Virtual-Memory System
> >
> > Signed-off-by: Guo Ren <ren_guo@c-sky.com>
> > Reviewed-by: Liu Zhiwei <zhiwei_liu@c-sky.com>
> > ---
> > target/riscv/cpu_helper.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index 87dd6a6..3c5e8f6 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -260,6 +260,7 @@ restart:
> > target_ulong pte = ldl_phys(cs->as, pte_addr);
> > #elif defined(TARGET_RISCV64)
> > target_ulong pte = ldq_phys(cs->as, pte_addr);
> > + pte = pte << 10 >> 10;
>
> You can just AND with a mask instead of shifting both directions.
>
> Alistair
>
> > #endif
> > hwaddr ppn = pte >> PTE_PPN_SHIFT;
> >
> > --
> > 2.7.4
> >
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-09-24 13:11 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2019-09-24 5:00 [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64 guoren
2019-09-24 5:00 ` guoren
2019-09-24 5:03 ` Alistair Francis
2019-09-24 5:03 ` Alistair Francis
2019-09-24 7:43 ` Guo Ren
2019-09-24 7:43 ` Guo Ren
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