[PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[Samuel Holland]

This series aims to improve support for NOMMU, specifically by making it
easier to test NOMMU kernels in QEMU and on various widely-available
hardware (errata permitting). After all, everything supports Svbare...

After applying this series, a NOMMU kernel based on defconfig (changing
only the three options below*) boots to userspace on QEMU when passed as
-kernel.

  # CONFIG_RISCV_M_MODE is not set
  # CONFIG_MMU is not set
  CONFIG_NONPORTABLE=y

*if you are using LLD, you must also disable BPF_SYSCALL and KALLSYMS,
because LLD bails on out-of-range references to undefined weak symbols.


Samuel Holland (4):
  riscv: Fix TASK_SIZE on 64-bit NOMMU
  riscv: Fix loading 64-bit NOMMU kernels past the start of RAM
  riscv: Remove MMU dependency from Zbb and Zicboz
  riscv: Allow NOMMU kernels to run in S-mode

 arch/riscv/Kconfig               | 17 ++++++++++-------
 arch/riscv/include/asm/page.h    |  2 +-
 arch/riscv/include/asm/pgtable.h |  2 +-
 arch/riscv/mm/init.c             |  2 +-
 4 files changed, 13 insertions(+), 10 deletions(-)

-- 
2.43.0


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[PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[Samuel Holland]

This series aims to improve support for NOMMU, specifically by making it
easier to test NOMMU kernels in QEMU and on various widely-available
hardware (errata permitting). After all, everything supports Svbare...

After applying this series, a NOMMU kernel based on defconfig (changing
only the three options below*) boots to userspace on QEMU when passed as
-kernel.

  # CONFIG_RISCV_M_MODE is not set
  # CONFIG_MMU is not set
  CONFIG_NONPORTABLE=y

*if you are using LLD, you must also disable BPF_SYSCALL and KALLSYMS,
because LLD bails on out-of-range references to undefined weak symbols.


Samuel Holland (4):
  riscv: Fix TASK_SIZE on 64-bit NOMMU
  riscv: Fix loading 64-bit NOMMU kernels past the start of RAM
  riscv: Remove MMU dependency from Zbb and Zicboz
  riscv: Allow NOMMU kernels to run in S-mode

 arch/riscv/Kconfig               | 17 ++++++++++-------
 arch/riscv/include/asm/page.h    |  2 +-
 arch/riscv/include/asm/pgtable.h |  2 +-
 arch/riscv/mm/init.c             |  2 +-
 4 files changed, 13 insertions(+), 10 deletions(-)

-- 
2.43.0

[PATCH 1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU

[Samuel Holland]

On NOMMU, userspace memory can come from anywhere in physical RAM. The
current definition of TASK_SIZE is wrong if any RAM exists above 4G,
causing spurious failures in the userspace access routines.

Fixes: 6bd33e1ece52 ("riscv: add nommu support")
Fixes: c3f896dcf1e4 ("mm: switch the test_vmalloc module to use __vmalloc_node")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 arch/riscv/include/asm/pgtable.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 0c94260b5d0c..a564a39e5676 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -882,7 +882,7 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
 #define PAGE_SHARED		__pgprot(0)
 #define PAGE_KERNEL		__pgprot(0)
 #define swapper_pg_dir		NULL
-#define TASK_SIZE		0xffffffffUL
+#define TASK_SIZE		_AC(-1, UL)
 #define VMALLOC_START		_AC(0, UL)
 #define VMALLOC_END		TASK_SIZE
 
-- 
2.43.0


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[PATCH 1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU

[Samuel Holland]

On NOMMU, userspace memory can come from anywhere in physical RAM. The
current definition of TASK_SIZE is wrong if any RAM exists above 4G,
causing spurious failures in the userspace access routines.

Fixes: 6bd33e1ece52 ("riscv: add nommu support")
Fixes: c3f896dcf1e4 ("mm: switch the test_vmalloc module to use __vmalloc_node")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 arch/riscv/include/asm/pgtable.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 0c94260b5d0c..a564a39e5676 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -882,7 +882,7 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
 #define PAGE_SHARED		__pgprot(0)
 #define PAGE_KERNEL		__pgprot(0)
 #define swapper_pg_dir		NULL
-#define TASK_SIZE		0xffffffffUL
+#define TASK_SIZE		_AC(-1, UL)
 #define VMALLOC_START		_AC(0, UL)
 #define VMALLOC_END		TASK_SIZE
 
-- 
2.43.0

Re: [PATCH 1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU

[Jisheng Zhang]

On Mon, Feb 26, 2024 at 04:34:46PM -0800, Samuel Holland wrote:
> On NOMMU, userspace memory can come from anywhere in physical RAM. The
> current definition of TASK_SIZE is wrong if any RAM exists above 4G,
> causing spurious failures in the userspace access routines.
> 
> Fixes: 6bd33e1ece52 ("riscv: add nommu support")
> Fixes: c3f896dcf1e4 ("mm: switch the test_vmalloc module to use __vmalloc_node")
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

Reviewed-by: Jisheng Zhang <jszhang@kernel.org>

> ---
> 
>  arch/riscv/include/asm/pgtable.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 0c94260b5d0c..a564a39e5676 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -882,7 +882,7 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
>  #define PAGE_SHARED		__pgprot(0)
>  #define PAGE_KERNEL		__pgprot(0)
>  #define swapper_pg_dir		NULL
> -#define TASK_SIZE		0xffffffffUL
> +#define TASK_SIZE		_AC(-1, UL)
>  #define VMALLOC_START		_AC(0, UL)
>  #define VMALLOC_END		TASK_SIZE
>  
> -- 
> 2.43.0
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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Re: [PATCH 1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU

[Jisheng Zhang]

On Mon, Feb 26, 2024 at 04:34:46PM -0800, Samuel Holland wrote:
> On NOMMU, userspace memory can come from anywhere in physical RAM. The
> current definition of TASK_SIZE is wrong if any RAM exists above 4G,
> causing spurious failures in the userspace access routines.
> 
> Fixes: 6bd33e1ece52 ("riscv: add nommu support")
> Fixes: c3f896dcf1e4 ("mm: switch the test_vmalloc module to use __vmalloc_node")
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

Reviewed-by: Jisheng Zhang <jszhang@kernel.org>

> ---
> 
>  arch/riscv/include/asm/pgtable.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 0c94260b5d0c..a564a39e5676 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -882,7 +882,7 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
>  #define PAGE_SHARED		__pgprot(0)
>  #define PAGE_KERNEL		__pgprot(0)
>  #define swapper_pg_dir		NULL
> -#define TASK_SIZE		0xffffffffUL
> +#define TASK_SIZE		_AC(-1, UL)
>  #define VMALLOC_START		_AC(0, UL)
>  #define VMALLOC_END		TASK_SIZE
>  
> -- 
> 2.43.0
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH 1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU

[Bo Gan]

On 3/27/24 12:04 AM, Jisheng Zhang wrote:
> On Mon, Feb 26, 2024 at 04:34:46PM -0800, Samuel Holland wrote:
>> On NOMMU, userspace memory can come from anywhere in physical RAM. The
>> current definition of TASK_SIZE is wrong if any RAM exists above 4G,
>> causing spurious failures in the userspace access routines.
>>
>> Fixes: 6bd33e1ece52 ("riscv: add nommu support")
>> Fixes: c3f896dcf1e4 ("mm: switch the test_vmalloc module to use __vmalloc_node")
>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> 
> Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> 

Reviewed-by: Bo Gan <ganboing@gmail.com>

Thanks for this patch! I'm doing something similar locally and it fixes the
linux nommu + musl libc build on my JH7110 S7 core.

Bo

>> ---
>>
>>   arch/riscv/include/asm/pgtable.h | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>> index 0c94260b5d0c..a564a39e5676 100644
>> --- a/arch/riscv/include/asm/pgtable.h
>> +++ b/arch/riscv/include/asm/pgtable.h
>> @@ -882,7 +882,7 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
>>   #define PAGE_SHARED		__pgprot(0)
>>   #define PAGE_KERNEL		__pgprot(0)
>>   #define swapper_pg_dir		NULL
>> -#define TASK_SIZE		0xffffffffUL
>> +#define TASK_SIZE		_AC(-1, UL)
>>   #define VMALLOC_START		_AC(0, UL)
>>   #define VMALLOC_END		TASK_SIZE
>>   
>> -- 
>> 2.43.0
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 
> _______________________________________________
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> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 


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Re: [PATCH 1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU

[Bo Gan]

On 3/27/24 12:04 AM, Jisheng Zhang wrote:
> On Mon, Feb 26, 2024 at 04:34:46PM -0800, Samuel Holland wrote:
>> On NOMMU, userspace memory can come from anywhere in physical RAM. The
>> current definition of TASK_SIZE is wrong if any RAM exists above 4G,
>> causing spurious failures in the userspace access routines.
>>
>> Fixes: 6bd33e1ece52 ("riscv: add nommu support")
>> Fixes: c3f896dcf1e4 ("mm: switch the test_vmalloc module to use __vmalloc_node")
>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> 
> Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> 

Reviewed-by: Bo Gan <ganboing@gmail.com>

Thanks for this patch! I'm doing something similar locally and it fixes the
linux nommu + musl libc build on my JH7110 S7 core.

Bo

>> ---
>>
>>   arch/riscv/include/asm/pgtable.h | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
>> index 0c94260b5d0c..a564a39e5676 100644
>> --- a/arch/riscv/include/asm/pgtable.h
>> +++ b/arch/riscv/include/asm/pgtable.h
>> @@ -882,7 +882,7 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
>>   #define PAGE_SHARED		__pgprot(0)
>>   #define PAGE_KERNEL		__pgprot(0)
>>   #define swapper_pg_dir		NULL
>> -#define TASK_SIZE		0xffffffffUL
>> +#define TASK_SIZE		_AC(-1, UL)
>>   #define VMALLOC_START		_AC(0, UL)
>>   #define VMALLOC_END		TASK_SIZE
>>   
>> -- 
>> 2.43.0
>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 
> _______________________________________________
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> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
> 

[PATCH 2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM

[Samuel Holland]

commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear
mapping") added logic to allow using RAM below the kernel load address.
However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the
kernel load address. Since that range of memory corresponds to PFNs
below ARCH_PFN_OFFSET, mm initialization runs off the beginning of
mem_map and corrupts adjacent kernel memory. Fix this by restoring the
previous behavior for NOMMU kernels.

Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 arch/riscv/include/asm/page.h | 2 +-
 arch/riscv/mm/init.c          | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index 57e887bfa34c..94b3d6930fc3 100644
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@ -89,7 +89,7 @@ typedef struct page *pgtable_t;
 #define PTE_FMT "%08lx"
 #endif
 
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) && defined(CONFIG_MMU)
 /*
  * We override this value as its generic definition uses __pa too early in
  * the boot process (before kernel_map.va_pa_offset is set).
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index fa34cf55037b..0c00efc75643 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -232,7 +232,7 @@ static void __init setup_bootmem(void)
 	 * In 64-bit, any use of __va/__pa before this point is wrong as we
 	 * did not know the start of DRAM before.
 	 */
-	if (IS_ENABLED(CONFIG_64BIT))
+	if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU))
 		kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;
 
 	/*
-- 
2.43.0


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[PATCH 2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM

[Samuel Holland]

commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear
mapping") added logic to allow using RAM below the kernel load address.
However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the
kernel load address. Since that range of memory corresponds to PFNs
below ARCH_PFN_OFFSET, mm initialization runs off the beginning of
mem_map and corrupts adjacent kernel memory. Fix this by restoring the
previous behavior for NOMMU kernels.

Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 arch/riscv/include/asm/page.h | 2 +-
 arch/riscv/mm/init.c          | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index 57e887bfa34c..94b3d6930fc3 100644
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@ -89,7 +89,7 @@ typedef struct page *pgtable_t;
 #define PTE_FMT "%08lx"
 #endif
 
-#ifdef CONFIG_64BIT
+#if defined(CONFIG_64BIT) && defined(CONFIG_MMU)
 /*
  * We override this value as its generic definition uses __pa too early in
  * the boot process (before kernel_map.va_pa_offset is set).
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index fa34cf55037b..0c00efc75643 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -232,7 +232,7 @@ static void __init setup_bootmem(void)
 	 * In 64-bit, any use of __va/__pa before this point is wrong as we
 	 * did not know the start of DRAM before.
 	 */
-	if (IS_ENABLED(CONFIG_64BIT))
+	if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU))
 		kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;
 
 	/*
-- 
2.43.0

Re: [PATCH 2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1992 bytes --]

On Mon, Feb 26, 2024 at 04:34:47PM -0800, Samuel Holland wrote:
> commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear
> mapping") added logic to allow using RAM below the kernel load address.
> However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the
> kernel load address. Since that range of memory corresponds to PFNs
> below ARCH_PFN_OFFSET, mm initialization runs off the beginning of
> mem_map and corrupts adjacent kernel memory. Fix this by restoring the
> previous behavior for NOMMU kernels.
> 
> Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping")

This commit was a year ago, why has nobody reported this as being an
issue before?

> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> 
>  arch/riscv/include/asm/page.h | 2 +-
>  arch/riscv/mm/init.c          | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
> index 57e887bfa34c..94b3d6930fc3 100644
> --- a/arch/riscv/include/asm/page.h
> +++ b/arch/riscv/include/asm/page.h
> @@ -89,7 +89,7 @@ typedef struct page *pgtable_t;
>  #define PTE_FMT "%08lx"
>  #endif
>  
> -#ifdef CONFIG_64BIT
> +#if defined(CONFIG_64BIT) && defined(CONFIG_MMU)
>  /*
>   * We override this value as its generic definition uses __pa too early in
>   * the boot process (before kernel_map.va_pa_offset is set).
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index fa34cf55037b..0c00efc75643 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -232,7 +232,7 @@ static void __init setup_bootmem(void)
>  	 * In 64-bit, any use of __va/__pa before this point is wrong as we
>  	 * did not know the start of DRAM before.
>  	 */
> -	if (IS_ENABLED(CONFIG_64BIT))
> +	if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU))
>  		kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;
>  
>  	/*
> -- 
> 2.43.0
> 

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

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Re: [PATCH 2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1992 bytes --]

On Mon, Feb 26, 2024 at 04:34:47PM -0800, Samuel Holland wrote:
> commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear
> mapping") added logic to allow using RAM below the kernel load address.
> However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the
> kernel load address. Since that range of memory corresponds to PFNs
> below ARCH_PFN_OFFSET, mm initialization runs off the beginning of
> mem_map and corrupts adjacent kernel memory. Fix this by restoring the
> previous behavior for NOMMU kernels.
> 
> Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping")

This commit was a year ago, why has nobody reported this as being an
issue before?

> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> 
>  arch/riscv/include/asm/page.h | 2 +-
>  arch/riscv/mm/init.c          | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
> index 57e887bfa34c..94b3d6930fc3 100644
> --- a/arch/riscv/include/asm/page.h
> +++ b/arch/riscv/include/asm/page.h
> @@ -89,7 +89,7 @@ typedef struct page *pgtable_t;
>  #define PTE_FMT "%08lx"
>  #endif
>  
> -#ifdef CONFIG_64BIT
> +#if defined(CONFIG_64BIT) && defined(CONFIG_MMU)
>  /*
>   * We override this value as its generic definition uses __pa too early in
>   * the boot process (before kernel_map.va_pa_offset is set).
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index fa34cf55037b..0c00efc75643 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -232,7 +232,7 @@ static void __init setup_bootmem(void)
>  	 * In 64-bit, any use of __va/__pa before this point is wrong as we
>  	 * did not know the start of DRAM before.
>  	 */
> -	if (IS_ENABLED(CONFIG_64BIT))
> +	if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU))
>  		kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;
>  
>  	/*
> -- 
> 2.43.0
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH 2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM

[Samuel Holland]

Hi Conor,

On 2024-02-27 6:18 AM, Conor Dooley wrote:
> On Mon, Feb 26, 2024 at 04:34:47PM -0800, Samuel Holland wrote:
>> commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear
>> mapping") added logic to allow using RAM below the kernel load address.
>> However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the
>> kernel load address. Since that range of memory corresponds to PFNs
>> below ARCH_PFN_OFFSET, mm initialization runs off the beginning of
>> mem_map and corrupts adjacent kernel memory. Fix this by restoring the
>> previous behavior for NOMMU kernels.
>>
>> Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping")
> 
> This commit was a year ago, why has nobody reported this as being an
> issue before?

I can think of a few reasons:
1) NOMMU users are likely to be using RV32, which is not affected.
2) Before patch 4 of this series, NOMMU implied M-mode, so there was nothing in
the way to prevent loading Linux at the very beginning of RAM. (U-Boot/SPL
relocates itself to the end of RAM, so it would not cause a problem.)
3) Platforms where RAM does not begin at exactly 0x80000000 would be affected,
there are several workarounds: change the start of RAM (for soft cores), change
PAGE_OFFSET, or change the memory ranges in the devicetree to exclude anything
below PAGE_OFFSET.

It's possible that nobody was affected, but it's still technically a regression
(a hypothetical platform with RAM from 0x40000000 to 0xc0000000 would crash
instead of only being able to use half its RAM), so I thought it still deserved
the Fixes: tag.

Regards,
Samuel

>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>> ---
>>
>>  arch/riscv/include/asm/page.h | 2 +-
>>  arch/riscv/mm/init.c          | 2 +-
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
>> index 57e887bfa34c..94b3d6930fc3 100644
>> --- a/arch/riscv/include/asm/page.h
>> +++ b/arch/riscv/include/asm/page.h
>> @@ -89,7 +89,7 @@ typedef struct page *pgtable_t;
>>  #define PTE_FMT "%08lx"
>>  #endif
>>  
>> -#ifdef CONFIG_64BIT
>> +#if defined(CONFIG_64BIT) && defined(CONFIG_MMU)
>>  /*
>>   * We override this value as its generic definition uses __pa too early in
>>   * the boot process (before kernel_map.va_pa_offset is set).
>> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
>> index fa34cf55037b..0c00efc75643 100644
>> --- a/arch/riscv/mm/init.c
>> +++ b/arch/riscv/mm/init.c
>> @@ -232,7 +232,7 @@ static void __init setup_bootmem(void)
>>  	 * In 64-bit, any use of __va/__pa before this point is wrong as we
>>  	 * did not know the start of DRAM before.
>>  	 */
>> -	if (IS_ENABLED(CONFIG_64BIT))
>> +	if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU))
>>  		kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;
>>  
>>  	/*
>> -- 
>> 2.43.0
>>


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Re: [PATCH 2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM

[Samuel Holland]

Hi Conor,

On 2024-02-27 6:18 AM, Conor Dooley wrote:
> On Mon, Feb 26, 2024 at 04:34:47PM -0800, Samuel Holland wrote:
>> commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear
>> mapping") added logic to allow using RAM below the kernel load address.
>> However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the
>> kernel load address. Since that range of memory corresponds to PFNs
>> below ARCH_PFN_OFFSET, mm initialization runs off the beginning of
>> mem_map and corrupts adjacent kernel memory. Fix this by restoring the
>> previous behavior for NOMMU kernels.
>>
>> Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping")
> 
> This commit was a year ago, why has nobody reported this as being an
> issue before?

I can think of a few reasons:
1) NOMMU users are likely to be using RV32, which is not affected.
2) Before patch 4 of this series, NOMMU implied M-mode, so there was nothing in
the way to prevent loading Linux at the very beginning of RAM. (U-Boot/SPL
relocates itself to the end of RAM, so it would not cause a problem.)
3) Platforms where RAM does not begin at exactly 0x80000000 would be affected,
there are several workarounds: change the start of RAM (for soft cores), change
PAGE_OFFSET, or change the memory ranges in the devicetree to exclude anything
below PAGE_OFFSET.

It's possible that nobody was affected, but it's still technically a regression
(a hypothetical platform with RAM from 0x40000000 to 0xc0000000 would crash
instead of only being able to use half its RAM), so I thought it still deserved
the Fixes: tag.

Regards,
Samuel

>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>> ---
>>
>>  arch/riscv/include/asm/page.h | 2 +-
>>  arch/riscv/mm/init.c          | 2 +-
>>  2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
>> index 57e887bfa34c..94b3d6930fc3 100644
>> --- a/arch/riscv/include/asm/page.h
>> +++ b/arch/riscv/include/asm/page.h
>> @@ -89,7 +89,7 @@ typedef struct page *pgtable_t;
>>  #define PTE_FMT "%08lx"
>>  #endif
>>  
>> -#ifdef CONFIG_64BIT
>> +#if defined(CONFIG_64BIT) && defined(CONFIG_MMU)
>>  /*
>>   * We override this value as its generic definition uses __pa too early in
>>   * the boot process (before kernel_map.va_pa_offset is set).
>> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
>> index fa34cf55037b..0c00efc75643 100644
>> --- a/arch/riscv/mm/init.c
>> +++ b/arch/riscv/mm/init.c
>> @@ -232,7 +232,7 @@ static void __init setup_bootmem(void)
>>  	 * In 64-bit, any use of __va/__pa before this point is wrong as we
>>  	 * did not know the start of DRAM before.
>>  	 */
>> -	if (IS_ENABLED(CONFIG_64BIT))
>> +	if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU))
>>  		kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;
>>  
>>  	/*
>> -- 
>> 2.43.0
>>

Re: [PATCH 2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1810 bytes --]

On Tue, Feb 27, 2024 at 01:22:12PM -0600, Samuel Holland wrote:
> Hi Conor,
> 
> On 2024-02-27 6:18 AM, Conor Dooley wrote:
> > On Mon, Feb 26, 2024 at 04:34:47PM -0800, Samuel Holland wrote:
> >> commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear
> >> mapping") added logic to allow using RAM below the kernel load address.
> >> However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the
> >> kernel load address. Since that range of memory corresponds to PFNs
> >> below ARCH_PFN_OFFSET, mm initialization runs off the beginning of
> >> mem_map and corrupts adjacent kernel memory. Fix this by restoring the
> >> previous behavior for NOMMU kernels.
> >>
> >> Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping")
> > 
> > This commit was a year ago, why has nobody reported this as being an
> > issue before?
> 
> I can think of a few reasons:
> 1) NOMMU users are likely to be using RV32, which is not affected.
> 2) Before patch 4 of this series, NOMMU implied M-mode, so there was nothing in
> the way to prevent loading Linux at the very beginning of RAM. (U-Boot/SPL
> relocates itself to the end of RAM, so it would not cause a problem.)
> 3) Platforms where RAM does not begin at exactly 0x80000000 would be affected,
> there are several workarounds: change the start of RAM (for soft cores), change
> PAGE_OFFSET, or change the memory ranges in the devicetree to exclude anything
> below PAGE_OFFSET.
> 
> It's possible that nobody was affected, but it's still technically a regression
> (a hypothetical platform with RAM from 0x40000000 to 0xc0000000 would crash
> instead of only being able to use half its RAM), so I thought it still deserved
> the Fixes: tag.

Right, thanks for explaining.

Cheers,
Conor.

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Re: [PATCH 2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1810 bytes --]

On Tue, Feb 27, 2024 at 01:22:12PM -0600, Samuel Holland wrote:
> Hi Conor,
> 
> On 2024-02-27 6:18 AM, Conor Dooley wrote:
> > On Mon, Feb 26, 2024 at 04:34:47PM -0800, Samuel Holland wrote:
> >> commit 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear
> >> mapping") added logic to allow using RAM below the kernel load address.
> >> However, this does not work for NOMMU, where PAGE_OFFSET is fixed to the
> >> kernel load address. Since that range of memory corresponds to PFNs
> >> below ARCH_PFN_OFFSET, mm initialization runs off the beginning of
> >> mem_map and corrupts adjacent kernel memory. Fix this by restoring the
> >> previous behavior for NOMMU kernels.
> >>
> >> Fixes: 3335068f8721 ("riscv: Use PUD/P4D/PGD pages for the linear mapping")
> > 
> > This commit was a year ago, why has nobody reported this as being an
> > issue before?
> 
> I can think of a few reasons:
> 1) NOMMU users are likely to be using RV32, which is not affected.
> 2) Before patch 4 of this series, NOMMU implied M-mode, so there was nothing in
> the way to prevent loading Linux at the very beginning of RAM. (U-Boot/SPL
> relocates itself to the end of RAM, so it would not cause a problem.)
> 3) Platforms where RAM does not begin at exactly 0x80000000 would be affected,
> there are several workarounds: change the start of RAM (for soft cores), change
> PAGE_OFFSET, or change the memory ranges in the devicetree to exclude anything
> below PAGE_OFFSET.
> 
> It's possible that nobody was affected, but it's still technically a regression
> (a hypothetical platform with RAM from 0x40000000 to 0xc0000000 would crash
> instead of only being able to use half its RAM), so I thought it still deserved
> the Fixes: tag.

Right, thanks for explaining.

Cheers,
Conor.

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[PATCH 3/4] riscv: Remove MMU dependency from Zbb and Zicboz

[Samuel Holland]

The Zbb and Zicboz ISA extensions have no dependency on an MMU and are
equally useful on NOMMU kernels.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 arch/riscv/Kconfig | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index bffbd869a068..ef53c00470d6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -581,7 +581,6 @@ config TOOLCHAIN_HAS_ZBB
 config RISCV_ISA_ZBB
 	bool "Zbb extension support for bit manipulation instructions"
 	depends on TOOLCHAIN_HAS_ZBB
-	depends on MMU
 	depends on RISCV_ALTERNATIVE
 	default y
 	help
@@ -613,7 +612,6 @@ config RISCV_ISA_ZICBOM
 
 config RISCV_ISA_ZICBOZ
 	bool "Zicboz extension support for faster zeroing of memory"
-	depends on MMU
 	depends on RISCV_ALTERNATIVE
 	default y
 	help
-- 
2.43.0


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[PATCH 3/4] riscv: Remove MMU dependency from Zbb and Zicboz

[Samuel Holland]

The Zbb and Zicboz ISA extensions have no dependency on an MMU and are
equally useful on NOMMU kernels.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 arch/riscv/Kconfig | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index bffbd869a068..ef53c00470d6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -581,7 +581,6 @@ config TOOLCHAIN_HAS_ZBB
 config RISCV_ISA_ZBB
 	bool "Zbb extension support for bit manipulation instructions"
 	depends on TOOLCHAIN_HAS_ZBB
-	depends on MMU
 	depends on RISCV_ALTERNATIVE
 	default y
 	help
@@ -613,7 +612,6 @@ config RISCV_ISA_ZICBOM
 
 config RISCV_ISA_ZICBOZ
 	bool "Zicboz extension support for faster zeroing of memory"
-	depends on MMU
 	depends on RISCV_ALTERNATIVE
 	default y
 	help
-- 
2.43.0

Re: [PATCH 3/4] riscv: Remove MMU dependency from Zbb and Zicboz

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1054 bytes --]

On Mon, Feb 26, 2024 at 04:34:48PM -0800, Samuel Holland wrote:
> The Zbb and Zicboz ISA extensions have no dependency on an MMU and are
> equally useful on NOMMU kernels.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
> 
>  arch/riscv/Kconfig | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index bffbd869a068..ef53c00470d6 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -581,7 +581,6 @@ config TOOLCHAIN_HAS_ZBB
>  config RISCV_ISA_ZBB
>  	bool "Zbb extension support for bit manipulation instructions"
>  	depends on TOOLCHAIN_HAS_ZBB
> -	depends on MMU
>  	depends on RISCV_ALTERNATIVE
>  	default y
>  	help
> @@ -613,7 +612,6 @@ config RISCV_ISA_ZICBOM
>  
>  config RISCV_ISA_ZICBOZ
>  	bool "Zicboz extension support for faster zeroing of memory"
> -	depends on MMU
>  	depends on RISCV_ALTERNATIVE
>  	default y
>  	help
> -- 
> 2.43.0
> 

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Re: [PATCH 3/4] riscv: Remove MMU dependency from Zbb and Zicboz

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1054 bytes --]

On Mon, Feb 26, 2024 at 04:34:48PM -0800, Samuel Holland wrote:
> The Zbb and Zicboz ISA extensions have no dependency on an MMU and are
> equally useful on NOMMU kernels.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> ---
> 
>  arch/riscv/Kconfig | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index bffbd869a068..ef53c00470d6 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -581,7 +581,6 @@ config TOOLCHAIN_HAS_ZBB
>  config RISCV_ISA_ZBB
>  	bool "Zbb extension support for bit manipulation instructions"
>  	depends on TOOLCHAIN_HAS_ZBB
> -	depends on MMU
>  	depends on RISCV_ALTERNATIVE
>  	default y
>  	help
> @@ -613,7 +612,6 @@ config RISCV_ISA_ZICBOM
>  
>  config RISCV_ISA_ZICBOZ
>  	bool "Zicboz extension support for faster zeroing of memory"
> -	depends on MMU
>  	depends on RISCV_ALTERNATIVE
>  	default y
>  	help
> -- 
> 2.43.0
> 

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[PATCH 4/4] riscv: Allow NOMMU kernels to run in S-mode

[Samuel Holland]

For ease of testing, it is convenient to run NOMMU kernels in supervisor
mode. The only required change is to offset the kernel load address,
since the beginning of RAM is usually reserved for M-mode firmware.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 arch/riscv/Kconfig | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ef53c00470d6..0dc09b2ac2f6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -64,7 +64,7 @@ config RISCV
 	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
 	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
 	select BUILDTIME_TABLE_SORT if MMU
-	select CLINT_TIMER if !MMU
+	select CLINT_TIMER if RISCV_M_MODE
 	select CLONE_BACKWARDS
 	select COMMON_CLK
 	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
@@ -220,8 +220,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MAX
 
 # set if we run in machine mode, cleared if we run in supervisor mode
 config RISCV_M_MODE
-	bool
-	default !MMU
+	bool "Build a kernel that runs in machine mode"
+	depends on !MMU
+	default y
+	help
+	  Select this option if you want to run the kernel in M-mode,
+	  without the assistance of any other firmware.
 
 # set if we are running in S-mode and can use SBI calls
 config RISCV_SBI
@@ -238,8 +242,9 @@ config MMU
 
 config PAGE_OFFSET
 	hex
-	default 0xC0000000 if 32BIT && MMU
-	default 0x80000000 if !MMU
+	default 0x80000000 if !MMU && RISCV_M_MODE
+	default 0x80200000 if !MMU
+	default 0xc0000000 if 32BIT
 	default 0xff60000000000000 if 64BIT
 
 config KASAN_SHADOW_OFFSET
-- 
2.43.0


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[PATCH 4/4] riscv: Allow NOMMU kernels to run in S-mode

[Samuel Holland]

For ease of testing, it is convenient to run NOMMU kernels in supervisor
mode. The only required change is to offset the kernel load address,
since the beginning of RAM is usually reserved for M-mode firmware.

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---

 arch/riscv/Kconfig | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ef53c00470d6..0dc09b2ac2f6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -64,7 +64,7 @@ config RISCV
 	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
 	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
 	select BUILDTIME_TABLE_SORT if MMU
-	select CLINT_TIMER if !MMU
+	select CLINT_TIMER if RISCV_M_MODE
 	select CLONE_BACKWARDS
 	select COMMON_CLK
 	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
@@ -220,8 +220,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MAX
 
 # set if we run in machine mode, cleared if we run in supervisor mode
 config RISCV_M_MODE
-	bool
-	default !MMU
+	bool "Build a kernel that runs in machine mode"
+	depends on !MMU
+	default y
+	help
+	  Select this option if you want to run the kernel in M-mode,
+	  without the assistance of any other firmware.
 
 # set if we are running in S-mode and can use SBI calls
 config RISCV_SBI
@@ -238,8 +242,9 @@ config MMU
 
 config PAGE_OFFSET
 	hex
-	default 0xC0000000 if 32BIT && MMU
-	default 0x80000000 if !MMU
+	default 0x80000000 if !MMU && RISCV_M_MODE
+	default 0x80200000 if !MMU
+	default 0xc0000000 if 32BIT
 	default 0xff60000000000000 if 64BIT
 
 config KASAN_SHADOW_OFFSET
-- 
2.43.0

Re: [PATCH 4/4] riscv: Allow NOMMU kernels to run in S-mode

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1884 bytes --]

On Mon, Feb 26, 2024 at 04:34:49PM -0800, Samuel Holland wrote:
> For ease of testing, it is convenient to run NOMMU kernels in supervisor
> mode. The only required change is to offset the kernel load address,
> since the beginning of RAM is usually reserved for M-mode firmware.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> 
>  arch/riscv/Kconfig | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ef53c00470d6..0dc09b2ac2f6 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -64,7 +64,7 @@ config RISCV
>  	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
>  	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
>  	select BUILDTIME_TABLE_SORT if MMU
> -	select CLINT_TIMER if !MMU
> +	select CLINT_TIMER if RISCV_M_MODE
>  	select CLONE_BACKWARDS
>  	select COMMON_CLK
>  	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
> @@ -220,8 +220,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MAX
>  
>  # set if we run in machine mode, cleared if we run in supervisor mode
>  config RISCV_M_MODE
> -	bool
> -	default !MMU
> +	bool "Build a kernel that runs in machine mode"
> +	depends on !MMU
> +	default y
> +	help
> +	  Select this option if you want to run the kernel in M-mode,
> +	  without the assistance of any other firmware.
>  
>  # set if we are running in S-mode and can use SBI calls
>  config RISCV_SBI
> @@ -238,8 +242,9 @@ config MMU
>  
>  config PAGE_OFFSET
>  	hex
> -	default 0xC0000000 if 32BIT && MMU
> -	default 0x80000000 if !MMU
> +	default 0x80000000 if !MMU && RISCV_M_MODE
> +	default 0x80200000 if !MMU
> +	default 0xc0000000 if 32BIT
>  	default 0xff60000000000000 if 64BIT

The first default seen with a passing condition is the default chosen,
right?

Cheers,
Conor.

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Re: [PATCH 4/4] riscv: Allow NOMMU kernels to run in S-mode

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1884 bytes --]

On Mon, Feb 26, 2024 at 04:34:49PM -0800, Samuel Holland wrote:
> For ease of testing, it is convenient to run NOMMU kernels in supervisor
> mode. The only required change is to offset the kernel load address,
> since the beginning of RAM is usually reserved for M-mode firmware.
> 
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> ---
> 
>  arch/riscv/Kconfig | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ef53c00470d6..0dc09b2ac2f6 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -64,7 +64,7 @@ config RISCV
>  	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
>  	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
>  	select BUILDTIME_TABLE_SORT if MMU
> -	select CLINT_TIMER if !MMU
> +	select CLINT_TIMER if RISCV_M_MODE
>  	select CLONE_BACKWARDS
>  	select COMMON_CLK
>  	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
> @@ -220,8 +220,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MAX
>  
>  # set if we run in machine mode, cleared if we run in supervisor mode
>  config RISCV_M_MODE
> -	bool
> -	default !MMU
> +	bool "Build a kernel that runs in machine mode"
> +	depends on !MMU
> +	default y
> +	help
> +	  Select this option if you want to run the kernel in M-mode,
> +	  without the assistance of any other firmware.
>  
>  # set if we are running in S-mode and can use SBI calls
>  config RISCV_SBI
> @@ -238,8 +242,9 @@ config MMU
>  
>  config PAGE_OFFSET
>  	hex
> -	default 0xC0000000 if 32BIT && MMU
> -	default 0x80000000 if !MMU
> +	default 0x80000000 if !MMU && RISCV_M_MODE
> +	default 0x80200000 if !MMU
> +	default 0xc0000000 if 32BIT
>  	default 0xff60000000000000 if 64BIT

The first default seen with a passing condition is the default chosen,
right?

Cheers,
Conor.

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Re: [PATCH 4/4] riscv: Allow NOMMU kernels to run in S-mode

[Samuel Holland]

Hi Conor,

On 2024-02-27 6:24 AM, Conor Dooley wrote:
> On Mon, Feb 26, 2024 at 04:34:49PM -0800, Samuel Holland wrote:
>> For ease of testing, it is convenient to run NOMMU kernels in supervisor
>> mode. The only required change is to offset the kernel load address,
>> since the beginning of RAM is usually reserved for M-mode firmware.
>>
>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>> ---
>>
>>  arch/riscv/Kconfig | 15 ++++++++++-----
>>  1 file changed, 10 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index ef53c00470d6..0dc09b2ac2f6 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -64,7 +64,7 @@ config RISCV
>>  	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
>>  	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
>>  	select BUILDTIME_TABLE_SORT if MMU
>> -	select CLINT_TIMER if !MMU
>> +	select CLINT_TIMER if RISCV_M_MODE
>>  	select CLONE_BACKWARDS
>>  	select COMMON_CLK
>>  	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
>> @@ -220,8 +220,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MAX
>>  
>>  # set if we run in machine mode, cleared if we run in supervisor mode
>>  config RISCV_M_MODE
>> -	bool
>> -	default !MMU
>> +	bool "Build a kernel that runs in machine mode"
>> +	depends on !MMU
>> +	default y
>> +	help
>> +	  Select this option if you want to run the kernel in M-mode,
>> +	  without the assistance of any other firmware.
>>  
>>  # set if we are running in S-mode and can use SBI calls
>>  config RISCV_SBI
>> @@ -238,8 +242,9 @@ config MMU
>>  
>>  config PAGE_OFFSET
>>  	hex
>> -	default 0xC0000000 if 32BIT && MMU
>> -	default 0x80000000 if !MMU
>> +	default 0x80000000 if !MMU && RISCV_M_MODE
>> +	default 0x80200000 if !MMU
>> +	default 0xc0000000 if 32BIT
>>  	default 0xff60000000000000 if 64BIT
> 
> The first default seen with a passing condition is the default chosen,
> right?

Yes, exactly. It's not required for the conditions to all be disjoint.

Regards,
Samuel


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Re: [PATCH 4/4] riscv: Allow NOMMU kernels to run in S-mode

[Samuel Holland]

Hi Conor,

On 2024-02-27 6:24 AM, Conor Dooley wrote:
> On Mon, Feb 26, 2024 at 04:34:49PM -0800, Samuel Holland wrote:
>> For ease of testing, it is convenient to run NOMMU kernels in supervisor
>> mode. The only required change is to offset the kernel load address,
>> since the beginning of RAM is usually reserved for M-mode firmware.
>>
>> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
>> ---
>>
>>  arch/riscv/Kconfig | 15 ++++++++++-----
>>  1 file changed, 10 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index ef53c00470d6..0dc09b2ac2f6 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -64,7 +64,7 @@ config RISCV
>>  	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
>>  	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
>>  	select BUILDTIME_TABLE_SORT if MMU
>> -	select CLINT_TIMER if !MMU
>> +	select CLINT_TIMER if RISCV_M_MODE
>>  	select CLONE_BACKWARDS
>>  	select COMMON_CLK
>>  	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
>> @@ -220,8 +220,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MAX
>>  
>>  # set if we run in machine mode, cleared if we run in supervisor mode
>>  config RISCV_M_MODE
>> -	bool
>> -	default !MMU
>> +	bool "Build a kernel that runs in machine mode"
>> +	depends on !MMU
>> +	default y
>> +	help
>> +	  Select this option if you want to run the kernel in M-mode,
>> +	  without the assistance of any other firmware.
>>  
>>  # set if we are running in S-mode and can use SBI calls
>>  config RISCV_SBI
>> @@ -238,8 +242,9 @@ config MMU
>>  
>>  config PAGE_OFFSET
>>  	hex
>> -	default 0xC0000000 if 32BIT && MMU
>> -	default 0x80000000 if !MMU
>> +	default 0x80000000 if !MMU && RISCV_M_MODE
>> +	default 0x80200000 if !MMU
>> +	default 0xc0000000 if 32BIT
>>  	default 0xff60000000000000 if 64BIT
> 
> The first default seen with a passing condition is the default chosen,
> right?

Yes, exactly. It's not required for the conditions to all be disjoint.

Regards,
Samuel

Re: [PATCH 4/4] riscv: Allow NOMMU kernels to run in S-mode

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 2662 bytes --]

On Tue, Feb 27, 2024 at 01:02:11PM -0600, Samuel Holland wrote:
> Hi Conor,
> 
> On 2024-02-27 6:24 AM, Conor Dooley wrote:
> > On Mon, Feb 26, 2024 at 04:34:49PM -0800, Samuel Holland wrote:
> >> For ease of testing, it is convenient to run NOMMU kernels in supervisor
> >> mode. The only required change is to offset the kernel load address,
> >> since the beginning of RAM is usually reserved for M-mode firmware.
> >>
> >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> >> ---
> >>
> >>  arch/riscv/Kconfig | 15 ++++++++++-----
> >>  1 file changed, 10 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >> index ef53c00470d6..0dc09b2ac2f6 100644
> >> --- a/arch/riscv/Kconfig
> >> +++ b/arch/riscv/Kconfig
> >> @@ -64,7 +64,7 @@ config RISCV
> >>  	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
> >>  	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
> >>  	select BUILDTIME_TABLE_SORT if MMU
> >> -	select CLINT_TIMER if !MMU
> >> +	select CLINT_TIMER if RISCV_M_MODE
> >>  	select CLONE_BACKWARDS
> >>  	select COMMON_CLK
> >>  	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
> >> @@ -220,8 +220,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MAX
> >>  
> >>  # set if we run in machine mode, cleared if we run in supervisor mode
> >>  config RISCV_M_MODE
> >> -	bool
> >> -	default !MMU
> >> +	bool "Build a kernel that runs in machine mode"
> >> +	depends on !MMU
> >> +	default y
> >> +	help
> >> +	  Select this option if you want to run the kernel in M-mode,
> >> +	  without the assistance of any other firmware.
> >>  
> >>  # set if we are running in S-mode and can use SBI calls
> >>  config RISCV_SBI
> >> @@ -238,8 +242,9 @@ config MMU
> >>  
> >>  config PAGE_OFFSET
> >>  	hex
> >> -	default 0xC0000000 if 32BIT && MMU
> >> -	default 0x80000000 if !MMU
> >> +	default 0x80000000 if !MMU && RISCV_M_MODE
> >> +	default 0x80200000 if !MMU
> >> +	default 0xc0000000 if 32BIT
> >>  	default 0xff60000000000000 if 64BIT
> > 
> > The first default seen with a passing condition is the default chosen,
> > right?
> 
> Yes, exactly. It's not required for the conditions to all be disjoint.

I had actually gone and checked was doing the right thing, but I didn't
manage to convince myself that this was intended behaviour rather than
an implementation detail. What I saw in the docs for default was:
"If multiple default values are visible, only the first defined one is active"
and I suppose "visible" is what is used to cover the if part.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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Re: [PATCH 4/4] riscv: Allow NOMMU kernels to run in S-mode

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2662 bytes --]

On Tue, Feb 27, 2024 at 01:02:11PM -0600, Samuel Holland wrote:
> Hi Conor,
> 
> On 2024-02-27 6:24 AM, Conor Dooley wrote:
> > On Mon, Feb 26, 2024 at 04:34:49PM -0800, Samuel Holland wrote:
> >> For ease of testing, it is convenient to run NOMMU kernels in supervisor
> >> mode. The only required change is to offset the kernel load address,
> >> since the beginning of RAM is usually reserved for M-mode firmware.
> >>
> >> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
> >> ---
> >>
> >>  arch/riscv/Kconfig | 15 ++++++++++-----
> >>  1 file changed, 10 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> >> index ef53c00470d6..0dc09b2ac2f6 100644
> >> --- a/arch/riscv/Kconfig
> >> +++ b/arch/riscv/Kconfig
> >> @@ -64,7 +64,7 @@ config RISCV
> >>  	select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
> >>  	select BINFMT_FLAT_NO_DATA_START_OFFSET if !MMU
> >>  	select BUILDTIME_TABLE_SORT if MMU
> >> -	select CLINT_TIMER if !MMU
> >> +	select CLINT_TIMER if RISCV_M_MODE
> >>  	select CLONE_BACKWARDS
> >>  	select COMMON_CLK
> >>  	select CPU_PM if CPU_IDLE || HIBERNATION || SUSPEND
> >> @@ -220,8 +220,12 @@ config ARCH_MMAP_RND_COMPAT_BITS_MAX
> >>  
> >>  # set if we run in machine mode, cleared if we run in supervisor mode
> >>  config RISCV_M_MODE
> >> -	bool
> >> -	default !MMU
> >> +	bool "Build a kernel that runs in machine mode"
> >> +	depends on !MMU
> >> +	default y
> >> +	help
> >> +	  Select this option if you want to run the kernel in M-mode,
> >> +	  without the assistance of any other firmware.
> >>  
> >>  # set if we are running in S-mode and can use SBI calls
> >>  config RISCV_SBI
> >> @@ -238,8 +242,9 @@ config MMU
> >>  
> >>  config PAGE_OFFSET
> >>  	hex
> >> -	default 0xC0000000 if 32BIT && MMU
> >> -	default 0x80000000 if !MMU
> >> +	default 0x80000000 if !MMU && RISCV_M_MODE
> >> +	default 0x80200000 if !MMU
> >> +	default 0xc0000000 if 32BIT
> >>  	default 0xff60000000000000 if 64BIT
> > 
> > The first default seen with a passing condition is the default chosen,
> > right?
> 
> Yes, exactly. It's not required for the conditions to all be disjoint.

I had actually gone and checked was doing the right thing, but I didn't
manage to convince myself that this was intended behaviour rather than
an implementation detail. What I saw in the docs for default was:
"If multiple default values are visible, only the first defined one is active"
and I suppose "visible" is what is used to cover the if part.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

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Re: [PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 1329 bytes --]

On Mon, Feb 26, 2024 at 04:34:45PM -0800, Samuel Holland wrote:
> This series aims to improve support for NOMMU, specifically by making it
> easier to test NOMMU kernels in QEMU and on various widely-available
> hardware (errata permitting). After all, everything supports Svbare...
> 
> After applying this series, a NOMMU kernel based on defconfig (changing
> only the three options below*) boots to userspace on QEMU when passed as
> -kernel.
> 
>   # CONFIG_RISCV_M_MODE is not set
>   # CONFIG_MMU is not set
>   CONFIG_NONPORTABLE=y
> 
> *if you are using LLD, you must also disable BPF_SYSCALL and KALLSYMS,
> because LLD bails on out-of-range references to undefined weak symbols.

That's not new to these patches though, right? IIRC that's an existing
issue.

Cheers,
Conor.

> 
> 
> Samuel Holland (4):
>   riscv: Fix TASK_SIZE on 64-bit NOMMU
>   riscv: Fix loading 64-bit NOMMU kernels past the start of RAM
>   riscv: Remove MMU dependency from Zbb and Zicboz
>   riscv: Allow NOMMU kernels to run in S-mode
> 
>  arch/riscv/Kconfig               | 17 ++++++++++-------
>  arch/riscv/include/asm/page.h    |  2 +-
>  arch/riscv/include/asm/pgtable.h |  2 +-
>  arch/riscv/mm/init.c             |  2 +-
>  4 files changed, 13 insertions(+), 10 deletions(-)
> 
> -- 
> 2.43.0
> 

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Re: [PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1329 bytes --]

On Mon, Feb 26, 2024 at 04:34:45PM -0800, Samuel Holland wrote:
> This series aims to improve support for NOMMU, specifically by making it
> easier to test NOMMU kernels in QEMU and on various widely-available
> hardware (errata permitting). After all, everything supports Svbare...
> 
> After applying this series, a NOMMU kernel based on defconfig (changing
> only the three options below*) boots to userspace on QEMU when passed as
> -kernel.
> 
>   # CONFIG_RISCV_M_MODE is not set
>   # CONFIG_MMU is not set
>   CONFIG_NONPORTABLE=y
> 
> *if you are using LLD, you must also disable BPF_SYSCALL and KALLSYMS,
> because LLD bails on out-of-range references to undefined weak symbols.

That's not new to these patches though, right? IIRC that's an existing
issue.

Cheers,
Conor.

> 
> 
> Samuel Holland (4):
>   riscv: Fix TASK_SIZE on 64-bit NOMMU
>   riscv: Fix loading 64-bit NOMMU kernels past the start of RAM
>   riscv: Remove MMU dependency from Zbb and Zicboz
>   riscv: Allow NOMMU kernels to run in S-mode
> 
>  arch/riscv/Kconfig               | 17 ++++++++++-------
>  arch/riscv/include/asm/page.h    |  2 +-
>  arch/riscv/include/asm/pgtable.h |  2 +-
>  arch/riscv/mm/init.c             |  2 +-
>  4 files changed, 13 insertions(+), 10 deletions(-)
> 
> -- 
> 2.43.0
> 

[-- Attachment #2: signature.asc --]
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Re: [PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[Samuel Holland]

Hi Conor,

On 2024-02-27 6:13 AM, Conor Dooley wrote:
> On Mon, Feb 26, 2024 at 04:34:45PM -0800, Samuel Holland wrote:
>> This series aims to improve support for NOMMU, specifically by making it
>> easier to test NOMMU kernels in QEMU and on various widely-available
>> hardware (errata permitting). After all, everything supports Svbare...
>>
>> After applying this series, a NOMMU kernel based on defconfig (changing
>> only the three options below*) boots to userspace on QEMU when passed as
>> -kernel.
>>
>>   # CONFIG_RISCV_M_MODE is not set
>>   # CONFIG_MMU is not set
>>   CONFIG_NONPORTABLE=y
>>
>> *if you are using LLD, you must also disable BPF_SYSCALL and KALLSYMS,
>> because LLD bails on out-of-range references to undefined weak symbols.
> 
> That's not new to these patches though, right? IIRC that's an existing
> issue.

Yes, that's correct. I see that arch/riscv/configs/nommu_* have KALLSYMS
disabled already; this may be the reason.

Regards,
Samuel


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Re: [PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[Samuel Holland]

Hi Conor,

On 2024-02-27 6:13 AM, Conor Dooley wrote:
> On Mon, Feb 26, 2024 at 04:34:45PM -0800, Samuel Holland wrote:
>> This series aims to improve support for NOMMU, specifically by making it
>> easier to test NOMMU kernels in QEMU and on various widely-available
>> hardware (errata permitting). After all, everything supports Svbare...
>>
>> After applying this series, a NOMMU kernel based on defconfig (changing
>> only the three options below*) boots to userspace on QEMU when passed as
>> -kernel.
>>
>>   # CONFIG_RISCV_M_MODE is not set
>>   # CONFIG_MMU is not set
>>   CONFIG_NONPORTABLE=y
>>
>> *if you are using LLD, you must also disable BPF_SYSCALL and KALLSYMS,
>> because LLD bails on out-of-range references to undefined weak symbols.
> 
> That's not new to these patches though, right? IIRC that's an existing
> issue.

Yes, that's correct. I see that arch/riscv/configs/nommu_* have KALLSYMS
disabled already; this may be the reason.

Regards,
Samuel

Re: [PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Mon, 26 Feb 2024 16:34:45 -0800 you wrote:
> This series aims to improve support for NOMMU, specifically by making it
> easier to test NOMMU kernels in QEMU and on various widely-available
> hardware (errata permitting). After all, everything supports Svbare...
> 
> After applying this series, a NOMMU kernel based on defconfig (changing
> only the three options below*) boots to userspace on QEMU when passed as
> -kernel.
> 
> [...]

Here is the summary with links:
  - [1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU
    https://git.kernel.org/riscv/c/6065e736f82c
  - [2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM
    https://git.kernel.org/riscv/c/aea702dde7e9
  - [3/4] riscv: Remove MMU dependency from Zbb and Zicboz
    (no matching commit)
  - [4/4] riscv: Allow NOMMU kernels to run in S-mode
    (no matching commit)

You are awesome, thank you!
-- 
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Re: [PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Mon, 26 Feb 2024 16:34:45 -0800 you wrote:
> This series aims to improve support for NOMMU, specifically by making it
> easier to test NOMMU kernels in QEMU and on various widely-available
> hardware (errata permitting). After all, everything supports Svbare...
> 
> After applying this series, a NOMMU kernel based on defconfig (changing
> only the three options below*) boots to userspace on QEMU when passed as
> -kernel.
> 
> [...]

Here is the summary with links:
  - [1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU
    https://git.kernel.org/riscv/c/6065e736f82c
  - [2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM
    https://git.kernel.org/riscv/c/aea702dde7e9
  - [3/4] riscv: Remove MMU dependency from Zbb and Zicboz
    (no matching commit)
  - [4/4] riscv: Allow NOMMU kernels to run in S-mode
    (no matching commit)

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
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Re: [PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Mon, 26 Feb 2024 16:34:45 -0800 you wrote:
> This series aims to improve support for NOMMU, specifically by making it
> easier to test NOMMU kernels in QEMU and on various widely-available
> hardware (errata permitting). After all, everything supports Svbare...
> 
> After applying this series, a NOMMU kernel based on defconfig (changing
> only the three options below*) boots to userspace on QEMU when passed as
> -kernel.
> 
> [...]

Here is the summary with links:
  - [1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU
    (no matching commit)
  - [2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM
    (no matching commit)
  - [3/4] riscv: Remove MMU dependency from Zbb and Zicboz
    https://git.kernel.org/riscv/c/9c4319d69744
  - [4/4] riscv: Allow NOMMU kernels to run in S-mode
    https://git.kernel.org/riscv/c/f862bbf4cdca

You are awesome, thank you!
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Re: [PATCH 0/4] riscv: 64-bit NOMMU fixes and enhancements

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Mon, 26 Feb 2024 16:34:45 -0800 you wrote:
> This series aims to improve support for NOMMU, specifically by making it
> easier to test NOMMU kernels in QEMU and on various widely-available
> hardware (errata permitting). After all, everything supports Svbare...
> 
> After applying this series, a NOMMU kernel based on defconfig (changing
> only the three options below*) boots to userspace on QEMU when passed as
> -kernel.
> 
> [...]

Here is the summary with links:
  - [1/4] riscv: Fix TASK_SIZE on 64-bit NOMMU
    (no matching commit)
  - [2/4] riscv: Fix loading 64-bit NOMMU kernels past the start of RAM
    (no matching commit)
  - [3/4] riscv: Remove MMU dependency from Zbb and Zicboz
    https://git.kernel.org/riscv/c/9c4319d69744
  - [4/4] riscv: Allow NOMMU kernels to run in S-mode
    https://git.kernel.org/riscv/c/f862bbf4cdca

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
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