* [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250
@ 2013-08-12 10:02 Vikas Sajjan
2013-08-12 10:02 ` [PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC Vikas Sajjan
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Vikas Sajjan @ 2013-08-12 10:02 UTC (permalink / raw)
To: mturquette, linux-samsung-soc
Cc: kgene.kim, t.figa, dianders, patches, linaro-kernel
Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250.
is rebased on Mike's
https://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=shortlog;h=refs/heads/clk-next
Vikas Sajjan (2):
clk: samsung: Add GPLL freq table for exynos5250 SoC
clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420
SoC
drivers/clk/samsung/clk-exynos5250.c | 19 +++++++-
drivers/clk/samsung/clk-exynos5420.c | 81 ++++++++++++++++++++++++++++++++++
2 files changed, 99 insertions(+), 1 deletion(-)
--
1.7.9.5
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC 2013-08-12 10:02 [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 Vikas Sajjan @ 2013-08-12 10:02 ` Vikas Sajjan 2013-08-28 8:06 ` Tomasz Figa 2013-08-12 10:02 ` [PATCH 2/2] clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC Vikas Sajjan 2013-08-14 5:06 ` [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 Vikas Sajjan 2 siblings, 1 reply; 9+ messages in thread From: Vikas Sajjan @ 2013-08-12 10:02 UTC (permalink / raw) To: mturquette, linux-samsung-soc Cc: kgene.kim, t.figa, dianders, patches, linaro-kernel Adds GPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> --- drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index a9916a4..c400e82 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -494,6 +494,21 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), }; +static struct samsung_pll_rate_table gpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(1400000000, 175, 3, 0), /* for 466MHz */ + PLL_35XX_RATE(800000000, 100, 3, 0), /* for 400MHz, 200MHz */ + PLL_35XX_RATE(667000000, 389, 7, 1), /* for 333MHz, 222MHz, 166MHz */ + PLL_35XX_RATE(600000000, 200, 4, 1), /* for 300MHz, 200MHz, 150MHz */ + PLL_35XX_RATE(533000000, 533, 12, 1), /* for 533MHz, 266MHz, 133MHz */ + PLL_35XX_RATE(450000000, 450, 12, 1), /* for 450Hz */ + PLL_35XX_RATE(400000000, 100, 3, 1), + PLL_35XX_RATE(333000000, 222, 4, 2), + PLL_35XX_RATE(200000000, 100, 3, 2), + { }, +}; + static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ @@ -565,8 +580,10 @@ static void __init exynos5250_clk_init(struct device_node *np) fin_pll_rate = _get_rate("fin_pll"); - if (fin_pll_rate == 24 * MHZ) + if (fin_pll_rate == 24 * MHZ) { exynos5250_plls[epll].rate_table = epll_24mhz_tbl; + exynos5250_plls[gpll].rate_table = gpll_24mhz_tbl; + } vpllsrc = __clk_lookup("mout_vpllsrc"); if (vpllsrc) -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC 2013-08-12 10:02 ` [PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC Vikas Sajjan @ 2013-08-28 8:06 ` Tomasz Figa 0 siblings, 0 replies; 9+ messages in thread From: Tomasz Figa @ 2013-08-28 8:06 UTC (permalink / raw) To: Vikas Sajjan Cc: mturquette, linux-samsung-soc, kgene.kim, t.figa, dianders, patches, linaro-kernel Hi Vikas, On Monday 12 of August 2013 15:32:13 Vikas Sajjan wrote: > Adds GPLL freq table for exynos5250 SoC. > > Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> > --- > drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos5250.c > b/drivers/clk/samsung/clk-exynos5250.c index a9916a4..c400e82 100644 > --- a/drivers/clk/samsung/clk-exynos5250.c > +++ b/drivers/clk/samsung/clk-exynos5250.c > @@ -494,6 +494,21 @@ static struct samsung_gate_clock > exynos5250_gate_clks[] __initdata = { GATE(g2d, "g2d", "aclk200", > GATE_IP_ACP, 3, 0, 0), > }; > > +static struct samsung_pll_rate_table gpll_24mhz_tbl[] __initdata = { > + /* sorted in descending order */ > + /* PLL_35XX_RATE(rate, m, p, s) */ > + PLL_35XX_RATE(1400000000, 175, 3, 0), /* for 466MHz */ > + PLL_35XX_RATE(800000000, 100, 3, 0), /* for 400MHz, 200MHz */ > + PLL_35XX_RATE(667000000, 389, 7, 1), /* for 333MHz, 222MHz, 166MHz */ Frequency generated by this entry is not exactly 667 MHz, but rather 666857142 Hz. This must be reflected by the rate field or PLL rate setting won't work correctly otherwise. > + PLL_35XX_RATE(600000000, 200, 4, 1), /* for 300MHz, 200MHz, 150MHz > */ + PLL_35XX_RATE(533000000, 533, 12, 1), /* for 533MHz, 266MHz, > 133MHz */ + PLL_35XX_RATE(450000000, 450, 12, 1), /* for 450Hz */ > + PLL_35XX_RATE(400000000, 100, 3, 1), > + PLL_35XX_RATE(333000000, 222, 4, 2), > + PLL_35XX_RATE(200000000, 100, 3, 2), > + { }, > +}; > + > static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { > /* sorted in descending order */ > /* PLL_36XX_RATE(rate, m, p, s, k) */ > @@ -565,8 +580,10 @@ static void __init exynos5250_clk_init(struct > device_node *np) > > fin_pll_rate = _get_rate("fin_pll"); > > - if (fin_pll_rate == 24 * MHZ) > + if (fin_pll_rate == 24 * MHZ) { > exynos5250_plls[epll].rate_table = epll_24mhz_tbl; > + exynos5250_plls[gpll].rate_table = gpll_24mhz_tbl; > + } Also you could rebase this series on my patches[1] cleaning several things up, to simplify this table setting code a bit. [1] - http://www.spinics.net/lists/arm-kernel/msg269848.html Best regards, Tomasz ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/2] clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC 2013-08-12 10:02 [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 Vikas Sajjan 2013-08-12 10:02 ` [PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC Vikas Sajjan @ 2013-08-12 10:02 ` Vikas Sajjan 2013-08-28 8:18 ` Tomasz Figa 2013-08-14 5:06 ` [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 Vikas Sajjan 2 siblings, 1 reply; 9+ messages in thread From: Vikas Sajjan @ 2013-08-12 10:02 UTC (permalink / raw) To: mturquette, linux-samsung-soc Cc: kgene.kim, t.figa, dianders, patches, linaro-kernel Adds APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC. Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> --- drivers/clk/samsung/clk-exynos5420.c | 81 ++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index e035fd0..42cea7e 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -757,10 +757,81 @@ static struct of_device_id ext_clk_match[] __initdata = { { }, }; +static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(2000000000, 250, 3, 0), + PLL_35XX_RATE(1900000000, 475, 6, 0), + PLL_35XX_RATE(1800000000, 225, 3, 0), + PLL_35XX_RATE(1700000000, 425, 6, 0), + PLL_35XX_RATE(1600000000, 200, 3, 0), + PLL_35XX_RATE(1500000000, 250, 4, 0), + PLL_35XX_RATE(1400000000, 175, 3, 0), + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 200, 2, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(900000000, 150, 2, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(600000000, 200, 2, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + { }, +}; + +static struct samsung_pll_rate_table kpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(1300000000, 325, 6, 0), + PLL_35XX_RATE(1200000000, 200, 2, 1), + PLL_35XX_RATE(1100000000, 275, 3, 1), + PLL_35XX_RATE(1000000000, 250, 3, 1), + PLL_35XX_RATE(900000000, 150, 2, 1), + PLL_35XX_RATE(800000000, 200, 3, 1), + PLL_35XX_RATE(700000000, 175, 3, 1), + PLL_35XX_RATE(600000000, 200, 2, 2), + PLL_35XX_RATE(500000000, 250, 3, 2), + PLL_35XX_RATE(400000000, 200, 3, 2), + PLL_35XX_RATE(300000000, 400, 4, 3), + PLL_35XX_RATE(200000000, 200, 3, 3), + { }, +}; + +static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(192000000, 64, 2, 2, 0), + PLL_36XX_RATE(180633600, 45, 3, 1, 10381), + PLL_36XX_RATE(180000000, 45, 3, 1, 0), + PLL_36XX_RATE(73728000, 98, 2, 4, 19923), + PLL_36XX_RATE(67737600, 90, 2, 4, 20762), + PLL_36XX_RATE(49152000, 98, 3, 4, 19923), + PLL_36XX_RATE(45158400, 90, 3, 4, 20762), + PLL_36XX_RATE(32768000, 131, 3, 5, 4719), + { }, +}; + +static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(533000000, 533, 6, 2), + PLL_35XX_RATE(480000000, 160, 2, 2), + PLL_35XX_RATE(420000000, 140, 2, 2), + PLL_35XX_RATE(350000000, 175, 3, 2), + PLL_35XX_RATE(266000000, 266, 3, 3), + PLL_35XX_RATE(177000000, 118, 2, 3), + PLL_35XX_RATE(100000000, 200, 3, 4), + { }, +}; + /* register exynos5420 clocks */ static void __init exynos5420_clk_init(struct device_node *np) { void __iomem *reg_base; + unsigned long fin_pll_rate; if (np) { reg_base = of_iomap(np, 0); @@ -776,6 +847,16 @@ static void __init exynos5420_clk_init(struct device_node *np) samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), ext_clk_match); + + fin_pll_rate = _get_rate("fin_pll"); + + if (fin_pll_rate == 24 * MHZ) { + exynos5420_plls[apll].rate_table = apll_24mhz_tbl; + exynos5420_plls[kpll].rate_table = kpll_24mhz_tbl; + exynos5420_plls[epll].rate_table = epll_24mhz_tbl; + exynos5420_plls[vpll].rate_table = vpll_24mhz_tbl; + } + samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), reg_base); samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks, -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC 2013-08-12 10:02 ` [PATCH 2/2] clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC Vikas Sajjan @ 2013-08-28 8:18 ` Tomasz Figa 0 siblings, 0 replies; 9+ messages in thread From: Tomasz Figa @ 2013-08-28 8:18 UTC (permalink / raw) To: Vikas Sajjan Cc: mturquette, linux-samsung-soc, kgene.kim, t.figa, dianders, patches, linaro-kernel Hi Vikas, On Monday 12 of August 2013 15:32:14 Vikas Sajjan wrote: > Adds APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC. > > Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> > --- > drivers/clk/samsung/clk-exynos5420.c | 81 > ++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos5420.c > b/drivers/clk/samsung/clk-exynos5420.c index e035fd0..42cea7e 100644 > --- a/drivers/clk/samsung/clk-exynos5420.c > +++ b/drivers/clk/samsung/clk-exynos5420.c > @@ -757,10 +757,81 @@ static struct of_device_id ext_clk_match[] > __initdata = { { }, > }; > > +static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = { > + /* sorted in descending order */ > + /* PLL_35XX_RATE(rate, m, p, s) */ > + PLL_35XX_RATE(2000000000, 250, 3, 0), > + PLL_35XX_RATE(1900000000, 475, 6, 0), > + PLL_35XX_RATE(1800000000, 225, 3, 0), > + PLL_35XX_RATE(1700000000, 425, 6, 0), > + PLL_35XX_RATE(1600000000, 200, 3, 0), > + PLL_35XX_RATE(1500000000, 250, 4, 0), > + PLL_35XX_RATE(1400000000, 175, 3, 0), > + PLL_35XX_RATE(1300000000, 325, 6, 0), > + PLL_35XX_RATE(1200000000, 200, 2, 1), > + PLL_35XX_RATE(1100000000, 275, 3, 1), > + PLL_35XX_RATE(1000000000, 250, 3, 1), > + PLL_35XX_RATE(900000000, 150, 2, 1), > + PLL_35XX_RATE(800000000, 200, 3, 1), > + PLL_35XX_RATE(700000000, 175, 3, 1), > + PLL_35XX_RATE(600000000, 200, 2, 2), > + PLL_35XX_RATE(500000000, 250, 3, 2), > + PLL_35XX_RATE(400000000, 200, 3, 2), > + PLL_35XX_RATE(300000000, 400, 4, 3), > + PLL_35XX_RATE(200000000, 200, 3, 3), > + { }, > +}; > + > +static struct samsung_pll_rate_table kpll_24mhz_tbl[] __initdata = { > + /* sorted in descending order */ > + /* PLL_35XX_RATE(rate, m, p, s) */ > + PLL_35XX_RATE(1300000000, 325, 6, 0), > + PLL_35XX_RATE(1200000000, 200, 2, 1), > + PLL_35XX_RATE(1100000000, 275, 3, 1), > + PLL_35XX_RATE(1000000000, 250, 3, 1), > + PLL_35XX_RATE(900000000, 150, 2, 1), > + PLL_35XX_RATE(800000000, 200, 3, 1), > + PLL_35XX_RATE(700000000, 175, 3, 1), > + PLL_35XX_RATE(600000000, 200, 2, 2), > + PLL_35XX_RATE(500000000, 250, 3, 2), > + PLL_35XX_RATE(400000000, 200, 3, 2), > + PLL_35XX_RATE(300000000, 400, 4, 3), > + PLL_35XX_RATE(200000000, 200, 3, 3), > + { }, > +}; > + > +static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = { > + /* sorted in descending order */ > + /* PLL_36XX_RATE(rate, m, p, s, k) */ > + PLL_36XX_RATE(192000000, 64, 2, 2, 0), > + PLL_36XX_RATE(180633600, 45, 3, 1, 10381), This one is in fact 180633605 Hz. > + PLL_36XX_RATE(180000000, 45, 3, 1, 0), > + PLL_36XX_RATE(73728000, 98, 2, 4, 19923), > + PLL_36XX_RATE(67737600, 90, 2, 4, 20762), 67737602 Hz > + PLL_36XX_RATE(49152000, 98, 3, 4, 19923), > + PLL_36XX_RATE(45158400, 90, 3, 4, 20762), 45158401 Hz > + PLL_36XX_RATE(32768000, 131, 3, 5, 4719), 32768001 Hz > + { }, > +}; > + > +static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { > + /* sorted in descending order */ > + /* PLL_35XX_RATE(rate, m, p, s) */ > + PLL_35XX_RATE(533000000, 533, 6, 2), > + PLL_35XX_RATE(480000000, 160, 2, 2), > + PLL_35XX_RATE(420000000, 140, 2, 2), > + PLL_35XX_RATE(350000000, 175, 3, 2), > + PLL_35XX_RATE(266000000, 266, 3, 3), > + PLL_35XX_RATE(177000000, 118, 2, 3), > + PLL_35XX_RATE(100000000, 200, 3, 4), > + { }, > +}; > + > /* register exynos5420 clocks */ > static void __init exynos5420_clk_init(struct device_node *np) > { > void __iomem *reg_base; > + unsigned long fin_pll_rate; This variable seems to be unnecessary. See below. > > if (np) { > reg_base = of_iomap(np, 0); > @@ -776,6 +847,16 @@ static void __init exynos5420_clk_init(struct > device_node *np) > samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, > ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), > ext_clk_match); > + > + fin_pll_rate = _get_rate("fin_pll"); > + > + if (fin_pll_rate == 24 * MHZ) { You can simplify this to if (_get_rate("fin_pll") == 24 * MHZ) { Best regards, Tomasz ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 2013-08-12 10:02 [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 Vikas Sajjan 2013-08-12 10:02 ` [PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC Vikas Sajjan 2013-08-12 10:02 ` [PATCH 2/2] clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC Vikas Sajjan @ 2013-08-14 5:06 ` Vikas Sajjan 2013-08-14 15:37 ` Tomasz Figa 2 siblings, 1 reply; 9+ messages in thread From: Vikas Sajjan @ 2013-08-14 5:06 UTC (permalink / raw) To: Mike Turquette Cc: linux-samsung-soc, Kukjin Kim, Tomasz Figa, Doug Anderson, patches, linaro-kernel Hi Mike, On Mon, Aug 12, 2013 at 3:32 PM, Vikas Sajjan <vikas.sajjan@linaro.org> wrote: > Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250. > > is rebased on Mike's > https://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=shortlog;h=refs/heads/clk-next > > > Vikas Sajjan (2): > clk: samsung: Add GPLL freq table for exynos5250 SoC > clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 > SoC > > drivers/clk/samsung/clk-exynos5250.c | 19 +++++++- > drivers/clk/samsung/clk-exynos5420.c | 81 ++++++++++++++++++++++++++++++++++ > 2 files changed, 99 insertions(+), 1 deletion(-) > Can you apply this patchset. > -- > 1.7.9.5 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 2013-08-14 5:06 ` [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 Vikas Sajjan @ 2013-08-14 15:37 ` Tomasz Figa 2013-08-22 7:00 ` Vikas Sajjan 0 siblings, 1 reply; 9+ messages in thread From: Tomasz Figa @ 2013-08-14 15:37 UTC (permalink / raw) To: Vikas Sajjan Cc: Mike Turquette, linux-samsung-soc, Kukjin Kim, Doug Anderson, patches, linaro-kernel [-- Attachment #1: Type: text/plain, Size: 1141 bytes --] Hi Vikas, On Wednesday 14 of August 2013 10:36:53 Vikas Sajjan wrote: > Hi Mike, > > On Mon, Aug 12, 2013 at 3:32 PM, Vikas Sajjan <vikas.sajjan@linaro.org> wrote: > > Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and > > exynos5250. > > > > is rebased on Mike's > > https://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=shortlog; > > h=refs/heads/clk-next> > > Vikas Sajjan (2): > > clk: samsung: Add GPLL freq table for exynos5250 SoC > > clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 > > > > SoC > > > > drivers/clk/samsung/clk-exynos5250.c | 19 +++++++- > > drivers/clk/samsung/clk-exynos5420.c | 81 > > ++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), > > 1 deletion(-) > > Can you apply this patchset. Please give few more days for the patch to be reviewed by people. A reasonable period of time which should pass after submitting a patch to ping the maintainers is around a week. This allows people to find some time to read your patches and share their opinions (and/or give their reviewed- by/acked-by tags). Best regards, Tomasz [-- Attachment #2: This is a digitally signed message part. --] [-- Type: application/pgp-signature, Size: 836 bytes --] ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 2013-08-14 15:37 ` Tomasz Figa @ 2013-08-22 7:00 ` Vikas Sajjan 2013-08-28 5:15 ` Vikas Sajjan 0 siblings, 1 reply; 9+ messages in thread From: Vikas Sajjan @ 2013-08-22 7:00 UTC (permalink / raw) To: Mike Turquette Cc: linux-samsung-soc, Kukjin Kim, Doug Anderson, patches, linaro-kernel, Tomasz Figa Hi Mike, On Wed, Aug 14, 2013 at 9:07 PM, Tomasz Figa <t.figa@samsung.com> wrote: > Hi Vikas, > > On Wednesday 14 of August 2013 10:36:53 Vikas Sajjan wrote: >> Hi Mike, >> >> On Mon, Aug 12, 2013 at 3:32 PM, Vikas Sajjan <vikas.sajjan@linaro.org> > wrote: >> > Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and >> > exynos5250. >> > >> > is rebased on Mike's >> > https://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=shortlog; >> > h=refs/heads/clk-next> >> > Vikas Sajjan (2): >> > clk: samsung: Add GPLL freq table for exynos5250 SoC >> > clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 >> > >> > SoC >> > >> > drivers/clk/samsung/clk-exynos5250.c | 19 +++++++- >> > drivers/clk/samsung/clk-exynos5420.c | 81 >> > ++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), >> > 1 deletion(-) >> >> Can you apply this patchset. > > Please give few more days for the patch to be reviewed by people. > > A reasonable period of time which should pass after submitting a patch to > ping the maintainers is around a week. This allows people to find some time > to read your patches and share their opinions (and/or give their reviewed- > by/acked-by tags). > any comments on this. > Best regards, > Tomasz ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 2013-08-22 7:00 ` Vikas Sajjan @ 2013-08-28 5:15 ` Vikas Sajjan 0 siblings, 0 replies; 9+ messages in thread From: Vikas Sajjan @ 2013-08-28 5:15 UTC (permalink / raw) To: Mike Turquette Cc: linux-samsung-soc, Kukjin Kim, Doug Anderson, patches, linaro-kernel, Tomasz Figa Hi Mike, On Thu, Aug 22, 2013 at 12:30 PM, Vikas Sajjan <sajjan.linux@gmail.com> wrote: > Hi Mike, > > On Wed, Aug 14, 2013 at 9:07 PM, Tomasz Figa <t.figa@samsung.com> wrote: >> Hi Vikas, >> >> On Wednesday 14 of August 2013 10:36:53 Vikas Sajjan wrote: >>> Hi Mike, >>> >>> On Mon, Aug 12, 2013 at 3:32 PM, Vikas Sajjan <vikas.sajjan@linaro.org> >> wrote: >>> > Adds GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and >>> > exynos5250. >>> > >>> > is rebased on Mike's >>> > https://git.linaro.org/gitweb?p=people/mturquette/linux.git;a=shortlog; >>> > h=refs/heads/clk-next> >>> > Vikas Sajjan (2): >>> > clk: samsung: Add GPLL freq table for exynos5250 SoC >>> > clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 >>> > >>> > SoC >>> > >>> > drivers/clk/samsung/clk-exynos5250.c | 19 +++++++- >>> > drivers/clk/samsung/clk-exynos5420.c | 81 >>> > ++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+), >>> > 1 deletion(-) >>> >>> Can you apply this patchset. >> >> Please give few more days for the patch to be reviewed by people. >> >> A reasonable period of time which should pass after submitting a patch to >> ping the maintainers is around a week. This allows people to find some time >> to read your patches and share their opinions (and/or give their reviewed- >> by/acked-by tags). >> > > any comments on this. > Can you apply this patchset. > >> Best regards, >> Tomasz ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2013-08-28 8:18 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2013-08-12 10:02 [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 Vikas Sajjan 2013-08-12 10:02 ` [PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC Vikas Sajjan 2013-08-28 8:06 ` Tomasz Figa 2013-08-12 10:02 ` [PATCH 2/2] clk: samsung: Add APLL, KPLL, EPLL and VPLL freq table for exynos5420 SoC Vikas Sajjan 2013-08-28 8:18 ` Tomasz Figa 2013-08-14 5:06 ` [PATCH 0/2] Add GPLL, APLL, KPLL, EPLL and VPLL freq table for exynos5420 and exynos5250 Vikas Sajjan 2013-08-14 15:37 ` Tomasz Figa 2013-08-22 7:00 ` Vikas Sajjan 2013-08-28 5:15 ` Vikas Sajjan
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