[parisc-linux] Should I read SHR[DW] as SHRP[DW] in parisc2.pdf?

[parisc-linux] Should I read SHR[DW] as SHRP[DW] in parisc2.pdf?

[Joel Soete]

Hi all,

About parisc 2.0 insn set at pages 7-49 and 7-51 I read SHRD,S,cond ...
and SHRW,S,cond ... but I don't find this mnemonic elsewhere in this book=
;
should I better read SHRPD and SHRPW respectively (mnemonic well defined)=
?

Thanks in advance for help,
    Joel

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Tiscali ADSL LIGHT, 19,95 EUR/mois pendant 6 mois, c'est le moment de fai=
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RE: [parisc-linux] Should I read SHR[DW] as SHRP[DW] in parisc2.pdf?

[Jim Hull]

Joel:

No.  SHRD and SHRW are not the same operations as SHRPD and SHRPW.  SHRD and
SHRW are not "real" machine instructions - they are pseudo-ops that the
assembler is supposed to recognize and convert to the appropriate "real"
instructions, in this case, EXTRD and EXTRW, respectively.  These pseudo-ops
exist solely for the convenience of the assembly programmer.  Rather than having
to remember that to do a right-shift operation, you need to code an EXTR[DW],
and figure out the correct pos and len arguments, you just write SHR[DW].

Similarly, SHLD (see notes on DEPD page), and SHLW (see notes on DEPW page) are
pseudo-ops for doing left-shifts.

Does the PA2.0 gnu assembler not recognize these (and other) pseudo-ops?  I'll
be the first to admit that we didn't do a very good job of documenting all the
PA2.0 pseudo-ops.  You might have expected a nice summary table in Appendix J,
but although the PA1.1 to PA2.0 pseudo-ops are there, the regular PA2.0 ones
aren't.  The only good way to find them all is to do a search for "pseudo" in
the PDF.

Here's what my search of:

 
http://h21007.www2.hp.com/dspp/files/unprotected/parisc20/PA_7_inst_descriptions
.pdf

found:

PDF Page  Page Number  Pseudo-Op           Real Instruction
-----------------------------------------------------------------------
13        7-11         B,n target          B,L,n target,%R0
                       CALL,n target       B,L,n target,%R2

23        7-21         CALL,n (b)          BVE,L,n (b),%R2
                       RET,n               BE,n (%R2)

41        7-39         SHLD,cond r,sa,t    DEPD,Z,cond r,63-sa,64-sa,t
                       SHLW,cond r,sa,t    DEPW,Z,cond r,31-sa,32-sa,t

51        7-49         SHRD,S,cond r,sa,t  EXTRD,S,cond r,63-sa,64-sa,t
                       SHRD,U,cond r,sa,t  EXTRD,U,cond r,63-sa,64-sa,t

53        7-51         SHRW,S,cond r,sa,t  EXTRW,S,cond r,31-sa,32-sa,t
                       SHRW,U,cond r,sa,t  EXTRW,U,cond r,31-sa,32-sa,t

85        7-83         LDI i,t             LDO i(0),t
                       COPY r,t            LDO 0(r),t

100       7-98         MTSAR r             MTCTL r,%SAR

105       7-103        NOP                 OR %R0,%R0,%R0

 -- Jim Hull
    PA-RISC/Itanium Processor Architect

> -----Original Message-----
> From: parisc-linux-bounces@lists.parisc-linux.org 
> [mailto:parisc-linux-bounces@lists.parisc-linux.org] On 
> Behalf Of Joel Soete
> Sent: Wednesday, August 11, 2004 10:35 AM
> To: List Parisc
> Subject: [parisc-linux] Should I read SHR[DW] as SHRP[DW] in 
> parisc2.pdf?
> 
> Hi all,
> 
> About parisc 2.0 insn set at pages 7-49 and 7-51 I read 
> SHRD,S,cond ...
> and SHRW,S,cond ... but I don't find this mnemonic elsewhere 
> in this book;
> should I better read SHRPD and SHRPW respectively (mnemonic 
> well defined)?
> 
> Thanks in advance for help,
>     Joel
> 
> --------------------------------------------------------------
> -------------
> Tiscali ADSL LIGHT, 19,95 EUR/mois pendant 6 mois, c'est le 
> moment de faire
> le pas!
> http://reg.tiscali.be/default.asp?lg=fr
> 
> 
> 
> 
> _______________________________________________
> parisc-linux mailing list
> parisc-linux@lists.parisc-linux.org
> http://lists.parisc-linux.org/mailman/listinfo/parisc-linux
> 


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Re: [parisc-linux] Should I read SHR[DW] as SHRP[DW] in parisc2.pdf?

[Michael S. Zick]

On Thu August 12 2004 12:41, Jim Hull wrote:
> Joel:
> 
- - - - -
> 
> Does the PA2.0 gnu assembler not recognize these (and other) pseudo-ops? 
Perhaps too well.
If I recall properly, the same table & code is used for both the assembler and
the 'disassemble' (-d) option of objdump.

'objdump -d' tries to be explicit in showing the space register assumed...
but it also displays the pseudo operations rather than the actual operation.
(Grumble, Grumble)

I think that Joel's question comes from (his and my) wondering if we need to
make 'machine independent' defines of some of these instructions.
According to Appendix J - we don't - the PA1.1 codes will assemble for
PA2.0 (with HP's assembler).
Time will show if gcc-inline assembly is that nice to we programmers.

Mike
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Re: [parisc-linux] Should I read SHR[DW] as SHRP[DW] in parisc2.p

[John David Anglin]

> Time will show if gcc-inline assembly is that nice to we programmers.

The PA-RISC GNU assembler was never intended to be a general purpose
assembler.  Features that GCC doesn't use are probably not that well
tested ;)

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)
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Re: [parisc-linux] Should I read SHR[DW] as SHRP[DW] in parisc2.p

[Michael S. Zick]

On Fri August 13 2004 10:20, John David Anglin wrote:
> > Time will show if gcc-inline assembly is that nice to we programmers.
> 
> The PA-RISC GNU assembler was never intended to be a general purpose
> assembler.  Features that GCC doesn't use are probably not that well
> tested ;)
> 
That is what I meant - we are on a 'feature discovery' trip here.

I did cheat a bit - I studied the pa.md file - figured that if what I was
interested in wasn't there, I need to be careful about using it.

Also discovered that software integer divide uses a similar bit-finder
to what I have proposed in the past. (Immediate, magic number,
bit masks).

But I have had that proposal turned down often enough - 
Even though it can be written to avoid register stalls; works
run-time, register size independent; does not dirty a d-cache
line and returns the bit-mask for the found bit 
(or the input mask modified by the found bit)
in addition to the index without additional instructions.
Which makes it ideal for all of those 'find next bit' loops.

Mike

> Dave
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Re: [parisc-linux] Should I read SHR[DW] as SHRP[DW] in parisc2.pdf?

[Michael S. Zick]

On Wed August 11 2004 12:35, Joel Soete wrote:
> Hi all,
> 
> About parisc 2.0 insn set at pages 7-49 and 7-51 I read SHRD,S,cond ...
> and SHRW,S,cond ... but I don't find this mnemonic elsewhere in this book;
> should I better read SHRPD and SHRPW respectively (mnemonic well defined)?
> 
Write as 'shd' either parisc-1.x or parisc-2.x for 32-bit operations.
I cut & pasted an example into a test source file, compiled (32 & 64),
objdump'd the *.o, then with the help of a hex-editor and
my Captain Midnight Decoder ring on the results:
	__asm__(
	"	ldi		0,%1\n"

/* compile & objdump the *.o; both 32-bit and 64-bit */
	"	shd		%%r0,%0,16,%2\n"	
	"	extru,=	%2,15,16,%%r0\n"	

/* Yields (see parisc2.0.pdf, appendix 'C'):
32-bit:
major op-code: 34, op-code extension: 011 (3)
  5c:   d2 80 09 f4     shrpw r0,r20,16,r20

major op-code: 34, op-code extension: 111 (7)
  60:   d2 80 39 f0     extrw,u,= r20,15,16,r0

Also on 64-bit, the identical bit pattern:
  80:   d2 80 09 f4     shrpw r0,r20,16,r20
  84:   d2 80 39 f0     extrw,u,= r20,15,16,r0

Then checking chapter 7 on 'shrpw' it very clearly
states that this instruction effects only the right
half of the registers. (no mention of left half)

Then checking chapter 7 on 'extrw' and it states
that the coded bit-position-number is internally
incremented by 32 so that it actually refers to (in
this example) pos=15+32, len=16.
(Claims left half is 'undefined')

Which means that 'int fls(int x)' as written would 
get its bit-position-numbers translated internally.
(and my earlier posting about it scanning the high
32 bits was wrong).

I still haven't figured out how the author gets that
the last bit to test is #0 rather than #31 - but then
that might be a typo in the code or another thinko
in my reasoning.
*/

Mike
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Re: [parisc-linux] Should I read SHR[DW] as SHRP[DW] in parisc2.p

[John David Anglin]

>   80:   d2 80 09 f4     shrpw r0,r20,16,r20
>   84:   d2 80 39 f0     extrw,u,= r20,15,16,r0
> 
> Then checking chapter 7 on 'shrpw' it very clearly
> states that this instruction effects only the right
> half of the registers. (no mention of left half)

It actually says for 'shrpw' that the leftmost 32 bits of the target
register (r20) are undefined.  If you had used a different target
register, r20 would not have been affected.

The condition in the 'extrw', "=", checks that all bits in the "word"
are zero.  The leftmost 32 bits in r20 are again undefined as a
result of the 'extrw' instruction.  However, they don't matter as the
target of the extrw is r0 (result discarded) and the condition test
only checks the rightmost 32 bits (word).

You need to be aware that a word is 32 bits and a double word 64 bits
in HP lingo.

The documentation is a bit vague when it comes to condition tests
when a result is discarded, but I believe that the test is done
before the result is discarded.  It doesn't make any sense to test
r0 which always reads as zero.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)
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Re: [parisc-linux] Should I read SHR[DW] as SHRP[DW] in parisc2.p

[Michael S. Zick]

On Fri August 13 2004 19:27, John David Anglin wrote:
> >   80:   d2 80 09 f4     shrpw r0,r20,16,r20
> >   84:   d2 80 39 f0     extrw,u,= r20,15,16,r0
> > 
> > Then checking chapter 7 on 'shrpw' it very clearly
> > states that this instruction effects only the right
> > half of the registers. (no mention of left half)
> 
> It actually says for 'shrpw' that the leftmost 32 bits of the target
> register (r20) are undefined.  If you had used a different target
> register, r20 would not have been affected.
> 
I need to learn to read better.

> 
> The documentation is a bit vague when it comes to condition tests
> when a result is discarded, but I believe that the test is done
> before the result is discarded.  It doesn't make any sense to test
> r0 which always reads as zero.
> 
Another vague thing -
Can you get a register stall (interlock) against gr0?
I.E:
op-code ....,destination Rx
op-code source Rx, .....
must wait for the store to Rx to be retired.
If Rx is GR0 - will the behavior be the same?
In tech. terms...
Is the discard prior to the retire stage of the
pipeline?
Is the discard even earlier than that in the pipeline? 
Does reference to GR0 count against the two 
register limit on issues?

I can find a partial answer - if the operation referencing
GR0 changes the flags - it seems that you can stall 
against the update of the flags in the PSW.
(or at least that would be reasonable to expect).

Mike
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