Re: I/O write ordering

[Jesse Barnes <jbarnes@engr.sgi.com>]

On Wednesday, September 22, 2004 10:40 am, Benjamin Herrenschmidt wrote:
> On Thu, 2004-09-23 at 00:32, Matthew Wilcox wrote:
> > I'd quite like to hear opinions from the PPC and Alpha people, they seem
> > to be the most out-of-order architectures.
>
> The more specific the barrier is, the happier we are on ppc so we can
> select the right one in our collection :)
>
> Write ordering is usually just a matter of eieio. _however_ the main
> problem we have is write ordering between two different storage classes,
> that is between cacheable space and non cacheable space. Our normal
> write ordering barrier will not order between those, thus causing all
> sorts of issues with devices mixing MMIO & DMA. We have to use a more
> heavy-weight barrier in those cases, but currently, linux lacks the
> proper abstraction for that, thus we had to clutter then normal MMIO
> writes to do the big barrier each time to be safe ...

Ok, mmiob() it is then.  Patch coming shortly (I'll post it to lkml).

As for write flushing, I guess we need to document that people should read a 
safe register (or config space if there isn't one, since that's guaranteed to 
soft fail).

Thanks,
Jesse