From: Andi Kleen <ak@suse.de>
To: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
Cc: linux-kernel@vger.kernel.org, discuss@x86-64.org, akpm@osdl.org
Subject: Re: [Patch] x86, x86_64: Intel HT, Multi core detection code cleanup
Date: Thu, 6 Oct 2005 12:42:25 +0200 [thread overview]
Message-ID: <200510061242.26563.ak@suse.de> (raw)
In-Reply-To: <20051005161706.B30098@unix-os.sc.intel.com>
On Thursday 06 October 2005 01:17, Siddha, Suresh B wrote:
> +
> +#ifdef CONFIG_X86_HT
> +#ifndef CONFIG_X86_64
> +#include <mach_apic.h>
> +#else
> +#include <asm/mach_apic.h>
> +#endif
Having such ifdefs is a clear cue that the code shouldn't be shared
between architectures.
-Andi
next prev parent reply other threads:[~2005-10-06 10:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-10-05 23:17 [Patch] x86, x86_64: Intel HT, Multi core detection code cleanup Siddha, Suresh B
2005-10-06 10:42 ` Andi Kleen [this message]
2005-10-07 2:20 ` Siddha, Suresh B
2005-10-07 9:52 ` [discuss] " Andi Kleen
2005-10-08 0:52 ` Siddha, Suresh B
2005-10-08 10:28 ` Andi Kleen
2005-10-12 21:30 ` Siddha, Suresh B
2005-10-12 21:36 ` [Patch 1/2] x86, x86_64: Intel HT, Multi core detection fixes Siddha, Suresh B
2005-10-12 21:49 ` [discuss] " Andi Kleen
2005-10-12 22:19 ` Siddha, Suresh B
2005-10-13 0:10 ` Andi Kleen
2005-10-13 21:55 ` Siddha, Suresh B
2005-10-13 21:59 ` [Patch 2/2] x86, x86_64: fix Intel cache detection code assumption about threads sharing Siddha, Suresh B
2005-10-12 21:41 ` Siddha, Suresh B
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