Re: [Qemu-devel] [PATCH 04/19] Allow 5 mmu indexes.

[Aurelien Jarno <aurelien@aurel32.net>]

On Mon, Mar 30, 2009 at 04:36:19PM +0200, Tristan Gingold wrote:
> This is necessary for alpha because it has 4 protection levels and pal mode.
> 
> Signed-off-by: Tristan Gingold <gingold@adacore.com>

Thanks, applied.

> ---
>  exec.c         |   30 +++++++++++++++++++++++++-----
>  softmmu_exec.h |   29 ++++++++++++++++++++++++-----
>  2 files changed, 49 insertions(+), 10 deletions(-)
> 
> diff --git a/exec.c b/exec.c
> index 5dc6bc7..7c2def0 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -1736,12 +1736,18 @@ void tlb_flush(CPUState *env, int flush_global)
>          env->tlb_table[2][i].addr_read = -1;
>          env->tlb_table[2][i].addr_write = -1;
>          env->tlb_table[2][i].addr_code = -1;
> -#if (NB_MMU_MODES == 4)
> +#endif
> +#if (NB_MMU_MODES >= 4)
>          env->tlb_table[3][i].addr_read = -1;
>          env->tlb_table[3][i].addr_write = -1;
>          env->tlb_table[3][i].addr_code = -1;
>  #endif
> +#if (NB_MMU_MODES >= 5)
> +        env->tlb_table[4][i].addr_read = -1;
> +        env->tlb_table[4][i].addr_write = -1;
> +        env->tlb_table[4][i].addr_code = -1;
>  #endif
> +
>      }
>  
>      memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
> @@ -1785,9 +1791,12 @@ void tlb_flush_page(CPUState *env, target_ulong addr)
>      tlb_flush_entry(&env->tlb_table[1][i], addr);
>  #if (NB_MMU_MODES >= 3)
>      tlb_flush_entry(&env->tlb_table[2][i], addr);
> -#if (NB_MMU_MODES == 4)
> +#endif
> +#if (NB_MMU_MODES >= 4)
>      tlb_flush_entry(&env->tlb_table[3][i], addr);
>  #endif
> +#if (NB_MMU_MODES >= 5)
> +    tlb_flush_entry(&env->tlb_table[4][i], addr);
>  #endif
>  
>      tlb_flush_jmp_cache(env, addr);
> @@ -1871,10 +1880,14 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
>  #if (NB_MMU_MODES >= 3)
>          for(i = 0; i < CPU_TLB_SIZE; i++)
>              tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
> -#if (NB_MMU_MODES == 4)
> +#endif
> +#if (NB_MMU_MODES >= 4)
>          for(i = 0; i < CPU_TLB_SIZE; i++)
>              tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
>  #endif
> +#if (NB_MMU_MODES >= 5)
> +        for(i = 0; i < CPU_TLB_SIZE; i++)
> +            tlb_reset_dirty_range(&env->tlb_table[4][i], start1, length);
>  #endif
>      }
>  }
> @@ -1920,10 +1933,14 @@ void cpu_tlb_update_dirty(CPUState *env)
>  #if (NB_MMU_MODES >= 3)
>      for(i = 0; i < CPU_TLB_SIZE; i++)
>          tlb_update_dirty(&env->tlb_table[2][i]);
> -#if (NB_MMU_MODES == 4)
> +#endif
> +#if (NB_MMU_MODES >= 4)
>      for(i = 0; i < CPU_TLB_SIZE; i++)
>          tlb_update_dirty(&env->tlb_table[3][i]);
>  #endif
> +#if (NB_MMU_MODES >= 5)
> +    for(i = 0; i < CPU_TLB_SIZE; i++)
> +        tlb_update_dirty(&env->tlb_table[4][i]);
>  #endif
>  }
>  
> @@ -1945,9 +1962,12 @@ static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
>      tlb_set_dirty1(&env->tlb_table[1][i], vaddr);
>  #if (NB_MMU_MODES >= 3)
>      tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
> -#if (NB_MMU_MODES == 4)
> +#endif
> +#if (NB_MMU_MODES >= 4)
>      tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
>  #endif
> +#if (NB_MMU_MODES >= 5)
> +    tlb_set_dirty1(&env->tlb_table[4][i], vaddr);
>  #endif
>  }
>  
> diff --git a/softmmu_exec.h b/softmmu_exec.h
> index 9cc4535..a43e621 100644
> --- a/softmmu_exec.h
> +++ b/softmmu_exec.h
> @@ -60,6 +60,7 @@
>  #include "softmmu_header.h"
>  #undef ACCESS_TYPE
>  #undef MEMSUFFIX
> +#endif /* (NB_MMU_MODES >= 3) */
>  
>  #if (NB_MMU_MODES >= 4)
>  
> @@ -78,12 +79,30 @@
>  #include "softmmu_header.h"
>  #undef ACCESS_TYPE
>  #undef MEMSUFFIX
> +#endif /* (NB_MMU_MODES >= 4) */
>  
> -#if (NB_MMU_MODES > 4)
> -#error "NB_MMU_MODES > 4 is not supported for now"
> -#endif /* (NB_MMU_MODES > 4) */
> -#endif /* (NB_MMU_MODES == 4) */
> -#endif /* (NB_MMU_MODES >= 3) */
> +#if (NB_MMU_MODES >= 5)
> +
> +#define ACCESS_TYPE 4
> +#define MEMSUFFIX MMU_MODE4_SUFFIX
> +#define DATA_SIZE 1
> +#include "softmmu_header.h"
> +
> +#define DATA_SIZE 2
> +#include "softmmu_header.h"
> +
> +#define DATA_SIZE 4
> +#include "softmmu_header.h"
> +
> +#define DATA_SIZE 8
> +#include "softmmu_header.h"
> +#undef ACCESS_TYPE
> +#undef MEMSUFFIX
> +#endif /* (NB_MMU_MODES >= 5) */
> +
> +#if (NB_MMU_MODES > 5)
> +#error "NB_MMU_MODES > 5 is not supported for now"
> +#endif /* (NB_MMU_MODES > 5) */
>  
>  /* these access are slower, they must be as rare as possible */
>  #define ACCESS_TYPE (NB_MMU_MODES)
> -- 
> 1.6.2
> 
> 
> 
> 

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net