Re: [Qemu-devel] [PATCH 18/19] Correctly decode hw_ld/hw_st opcodes for all alpha implementations.

[Aurelien Jarno <aurelien@aurel32.net>]

On Mon, Mar 30, 2009 at 04:36:33PM +0200, Tristan Gingold wrote:
> Allow privilegied pal_code only in kernel mode.
> 
> Signed-off-by: Tristan Gingold <gingold@adacore.com>
> ---
>  target-alpha/translate.c |   30 +++++++++++++++++++++++-------
>  1 files changed, 23 insertions(+), 7 deletions(-)
> 
> diff --git a/target-alpha/translate.c b/target-alpha/translate.c
> index 061cf5f..6938b5d 100644
> --- a/target-alpha/translate.c
> +++ b/target-alpha/translate.c
> @@ -52,6 +52,7 @@ struct DisasContext {
>      int pal_mode;
>  #endif
>      uint32_t amask;
> +    uint32_t implver;
>  };
>  
>  /* global register indexes */
> @@ -103,6 +104,20 @@ static void alpha_translate_init(void)
>      done_init = 1;
>  }
>  
> +static inline int get_mxcr_iprn(DisasContext *ctx, uint32_t insn)
> +{
> +    switch (ctx->implver) {
> +    case IMPLVER_2106x:
> +        return insn & 0xff;
> +    case IMPLVER_21164:
> +        return insn & 0xffff;
> +    case IMPLVER_21264:
> +        return (insn >> 8) & 0xff;
> +    default:
> +        abort();
> +    }
> +}
> +
>  static always_inline void gen_excp (DisasContext *ctx,
>                                      int exception, int error_code)
>  {
> @@ -689,7 +704,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
>  #if !defined (CONFIG_USER_ONLY)
>          } else if (palcode < 0x40) {
>              /* Privileged PAL code */
> -            if (ctx->mem_idx & 1)
> +            if (ctx->mem_idx != MMU_KERNEL_IDX)
>                  goto invalid_opc;
>              else
>                  gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0);
> @@ -1748,7 +1763,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
>          if (!ctx->pal_mode)
>              goto invalid_opc;
>          if (ra != 31) {
> -            TCGv tmp = tcg_const_i32(insn & 0xFF);
> +            TCGv tmp = tcg_const_i32(get_mxcr_iprn(ctx, insn));
>              gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]);
>              tcg_temp_free(tmp);
>          }
> @@ -2063,9 +2078,9 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
>          if (!ctx->pal_mode)
>              goto invalid_opc;
>          else {
> -            TCGv tmp1 = tcg_const_i32(insn & 0xFF);
> -            if (ra != 31)
> -                gen_helper_mtpr(tmp1, cpu_ir[ra]);
> +            TCGv tmp1 = tcg_const_i32(get_mxcr_iprn(ctx, insn));
> +            if (rb != 31)
> +                gen_helper_mtpr(tmp1, cpu_ir[rb]);
>              else {
>                  TCGv tmp2 = tcg_const_i64(0);
>                  gen_helper_mtpr(tmp1, tmp2);
> @@ -2089,7 +2104,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
>          } else {
>              TCGv tmp;
>  
> -            if (ra != 31) {
> +            if (rb != 31) {
>                  tmp = tcg_temp_new();
>                  tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51));
>              } else
> @@ -2097,7 +2112,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
>              gen_helper_hw_ret(tmp);
>              tcg_temp_free(tmp);
>          }
> -        ret = 2;
> +        ret = 3;
>          break;
>  #endif
>      case 0x1F:
> @@ -2352,6 +2367,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
>      gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
>      ctx.pc = pc_start;
>      ctx.amask = env->amask;
> +    ctx.implver = env->implver;
>  #if defined (CONFIG_USER_ONLY)
>      ctx.mem_idx = 0;
>  #else

implver is defined once at init time, and I don't expect it to change
once qemu has been started. Therefore I think there is no need to copy
env->implver into ctx.implver, env->implver can be accessed directly,
even from translate.c

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net