Re: [PATCH v2] edac: mpc85xx: Add support for new MPCxxx/Pxxxx EDAC controllers

[Andrew Morton <akpm@linux-foundation.org>]

On Fri, 16 Jul 2010 15:12:24 -0500
Scott Wood <scottwood@freescale.com> wrote:

> On Thu, 15 Jul 2010 22:25:07 +0400
> Anton Vorontsov <avorontsov@mvista.com> wrote:
> 
> > Simply add proper IDs into the device table.
> > 
> > Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
> > ---
> > 
> > It appears that the driver has two device ID tables. :-)
> > So, my previous attempt enabled only half of the functionality.
> > 
> > Andrew,
> > 
> > Can you please replace
> > 
> >   edac-mpc85xx-add-support-for-mpc8569-edac-controllers.patch
> > 
> > with this patch? It also adds some more IDs for the newer chips.
> > 

edac-mpc85xx-add-support-for-mpc8569-edac-controllers.patch already got
itself merged.  I queued this:

--- a/drivers/edac/mpc85xx_edac.c~edac-mpc85xx-add-support-for-new-mpcxxx-pxxxx-edac-controllers
+++ a/drivers/edac/mpc85xx_edac.c
@@ -646,8 +646,12 @@ static struct of_device_id mpc85xx_l2_er
 	{ .compatible = "fsl,mpc8555-l2-cache-controller", },
 	{ .compatible = "fsl,mpc8560-l2-cache-controller", },
 	{ .compatible = "fsl,mpc8568-l2-cache-controller", },
+	{ .compatible = "fsl,mpc8569-l2-cache-controller", },
 	{ .compatible = "fsl,mpc8572-l2-cache-controller", },
+	{ .compatible = "fsl,p1020-l2-cache-controller", },
+	{ .compatible = "fsl,p1021-l2-cache-controller", },
 	{ .compatible = "fsl,p2020-l2-cache-controller", },
+	{ .compatible = "fsl,p4080-l2-cache-controller", },
 	{},
 };
 
@@ -1123,7 +1127,10 @@ static struct of_device_id mpc85xx_mc_er
 	{ .compatible = "fsl,mpc8569-memory-controller", },
 	{ .compatible = "fsl,mpc8572-memory-controller", },
 	{ .compatible = "fsl,mpc8349-memory-controller", },
+	{ .compatible = "fsl,p1020-memory-controller", },
+	{ .compatible = "fsl,p1021-memory-controller", },
 	{ .compatible = "fsl,p2020-memory-controller", },
+	{ .compatible = "fsl,p4080-memory-controller", },
 	{},
 };
 
_


> > 
> >  drivers/edac/mpc85xx_edac.c |    8 ++++++++
> >  1 files changed, 8 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
> > index 52ca09b..3820879 100644
> > --- a/drivers/edac/mpc85xx_edac.c
> > +++ b/drivers/edac/mpc85xx_edac.c
> > @@ -646,8 +646,12 @@ static struct of_device_id mpc85xx_l2_err_of_match[] = {
> >  	{ .compatible = "fsl,mpc8555-l2-cache-controller", },
> >  	{ .compatible = "fsl,mpc8560-l2-cache-controller", },
> >  	{ .compatible = "fsl,mpc8568-l2-cache-controller", },
> > +	{ .compatible = "fsl,mpc8569-l2-cache-controller", },
> >  	{ .compatible = "fsl,mpc8572-l2-cache-controller", },
> > +	{ .compatible = "fsl,p1020-l2-cache-controller", },
> > +	{ .compatible = "fsl,p1021-l2-cache-controller", },
> >  	{ .compatible = "fsl,p2020-l2-cache-controller", },
> > +	{ .compatible = "fsl,p4080-l2-cache-controller", },
> 
> L2 on the p4080 is quite different from those other chips.  It's part
> of the core, controlled by SPRs.

erm, was that an ack or a nack?