Re: [tip:perf/urgent] perf, x86: Catch spurious interrupts after disabling counters

[Robert Richter <robert.richter@amd.com>]

On 29.09.10 10:00:54, Stephane Eranian wrote:

> > Here is another difference I noticed in x86_handle_irq() vs.
> > intel_pmu_handle_irq().
> > For Intel, handled is incremented even if there is no 64-bit overflow.
> >
> > With generic X86, it is incremented only when you have a 64-bit
> > overflow. I think that's wrong. You don't hit that condition very often
> > on AMD because counters are 47 bits wide, but this is generic code
> > and on P6 you definitively will. I believe you need to hoist handled++
> > just after the check on active_mask.
> >
> >
> > What do you think?
> >
> In other words, I think handled is there to track interrupts, i.e., hw
> counter overflows, and not 64-bit software counter overflows (which
> do trigger sample recording).

Stephane, the code looks good. We must first read the counter msr, its
raw value is returned by x86_perf_event_update(). Then we check we MSB
of the *counter* value and if it is zero, we detected a counter
overflow (not a 64 bit overflow) and increment 'handled'.

-Robert

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Advanced Micro Devices, Inc.
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