[PATCH] drm/i915: fix swizzling on gen6+

[PATCH] drm/i915: fix swizzling on gen6+

[Daniel Vetter]

Fixes tests/gem_tiled_pread on my snb. I know, mesa doesn't use this
on gen6+, but I also hate failing testcases.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_gem_tiling.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 99c4faa..103da6f 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -92,7 +92,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
-	if (INTEL_INFO(dev)->gen >= 5) {
+	if (INTEL_INFO(dev)->gen >= 6) {
+		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
+		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
+	} else if (IS_GEN5(dev)) {
 		/* On Ironlake whatever DRAM config, GPU always do
 		 * same swizzling setup.
 		 */
-- 
1.7.6

Re: [PATCH] drm/i915: fix swizzling on gen6+

[Ben Widawsky]

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH] drm/i915: fix swizzling on gen6+

[Chris Wilson]

On Mon, 12 Sep 2011 20:49:16 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Fixes tests/gem_tiled_pread on my snb. I know, mesa doesn't use this
> on gen6+, but I also hate failing testcases.

Hmm, I thought gen6 also has DRAM configuration registers that we were
meant to set and to follow. Not that I could actually find the
cross-references! I've been surprised that it works and scared
to poke too hard just in case it was broken underneath. ;-)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH] drm/i915: fix swizzling on gen6+

[Daniel Vetter]

On Mon, Sep 12, 2011 at 09:13:39PM +0100, Chris Wilson wrote:
> On Mon, 12 Sep 2011 20:49:16 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > Fixes tests/gem_tiled_pread on my snb. I know, mesa doesn't use this
> > on gen6+, but I also hate failing testcases.
> 
> Hmm, I thought gen6 also has DRAM configuration registers that we were
> meant to set and to follow. Not that I could actually find the
> cross-references! I've been surprised that it works and scared
> to poke too hard just in case it was broken underneath. ;-)

Well, I've checked with my ilk and snb, and now it works for both. ymmv.
The other options is to return SWIZZLE_UNKOWN back to userspace and
disable the tests on gen5+. I don't care too much either way, but I think
making it work is less risky. And now that qa actually runs our tests, we
might even catch this earlier.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH] drm/i915: fix swizzling on gen6+

[Chris Wilson]

On Mon, 12 Sep 2011 22:37:14 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Sep 12, 2011 at 09:13:39PM +0100, Chris Wilson wrote:
> > On Mon, 12 Sep 2011 20:49:16 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > > Fixes tests/gem_tiled_pread on my snb. I know, mesa doesn't use this
> > > on gen6+, but I also hate failing testcases.
> > 
> > Hmm, I thought gen6 also has DRAM configuration registers that we were
> > meant to set and to follow. Not that I could actually find the
> > cross-references! I've been surprised that it works and scared
> > to poke too hard just in case it was broken underneath. ;-)
> 
> Well, I've checked with my ilk and snb, and now it works for both. ymmv.
> The other options is to return SWIZZLE_UNKOWN back to userspace and
> disable the tests on gen5+. I don't care too much either way, but I think
> making it work is less risky. And now that qa actually runs our tests, we
> might even catch this earlier.

I suspect we are missing some code to handle atypical configurations.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH] drm/i915: fix swizzling on gen6+

[Daniel Vetter]

Hi Keith,

This one fixes a testcase from intel-gpu-tools. No actual userspace
depends upon it, afaics. The other option is to stop supporting this on
gen6+ and return SWIZZLE_UNKOWN. I don't mind either way, I just don't
like broken interfaces ;-)

Yours, Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

[PATCH] drm/i915: fix swizzling on gen6+

[Daniel Vetter]

This is commit acc83eb5a1e0ae7dbbf89ca2a1a943ade224bb84

Latest mesa relies on correctly detected swizzling for certain operations,
hence this patch needs to be applied to all kernels prior to v3.2.
Otherwise certain OpenGL features will not quite work correctly on
Sandybridge/Ivybdridge machines.

Fixes tests/gem_tiled_pread on my snb. I know, mesa doesn't use this
on gen6+, but I also hate failing testcases.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
---
 drivers/gpu/drm/i915/i915_gem_tiling.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 99c4faa..103da6f 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -92,7 +92,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
 	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
 	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
-	if (INTEL_INFO(dev)->gen >= 5) {
+	if (INTEL_INFO(dev)->gen >= 6) {
+		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
+		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
+	} else if (IS_GEN5(dev)) {
 		/* On Ironlake whatever DRAM config, GPU always do
 		 * same swizzling setup.
 		 */
-- 
1.7.9.1

Re: [PATCH] drm/i915: fix swizzling on gen6+

[Daniel Vetter]

On Fri, Mar 02, 2012 at 09:33:53PM +0100, Daniel Vetter wrote:
> This is commit acc83eb5a1e0ae7dbbf89ca2a1a943ade224bb84

Oops, the "upstream." got cut away, i.e. this a stable submission for
pre-3.2 kernels.
-Daniel

> Latest mesa relies on correctly detected swizzling for certain operations,
> hence this patch needs to be applied to all kernels prior to v3.2.
> Otherwise certain OpenGL features will not quite work correctly on
> Sandybridge/Ivybdridge machines.
> 
> Fixes tests/gem_tiled_pread on my snb. I know, mesa doesn't use this
> on gen6+, but I also hate failing testcases.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Keith Packard <keithp@keithp.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_tiling.c |    5 ++++-
>  1 files changed, 4 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
> index 99c4faa..103da6f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_tiling.c
> +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
> @@ -92,7 +92,10 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
>  	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
>  	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
>  
> -	if (INTEL_INFO(dev)->gen >= 5) {
> +	if (INTEL_INFO(dev)->gen >= 6) {
> +		swizzle_x = I915_BIT_6_SWIZZLE_NONE;
> +		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
> +	} else if (IS_GEN5(dev)) {
>  		/* On Ironlake whatever DRAM config, GPU always do
>  		 * same swizzling setup.
>  		 */
> -- 
> 1.7.9.1
> 

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48