Garbage on screen when switching resolution after BIOS post

Garbage on screen when switching resolution after BIOS post

[meteor]

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We are developing a Linux solution. Our platform is using Intel SandyBridge
and its VGA
(kernel 2.6.35.8, 915 KMS driver).

We found system will show garbage at the moment VGA is hand over to OS after
BIOS POST.
The symptom doesn’t happen in WIN 7.
After checking with EE, the LCD_VDD_EN pin is pull low again when boot to
Win 7.
However, this pin is not pull low when boot to Linux.

After BIOS POST, there’s a power reset during driver loading for resolution
pattern sending.
It’s why driver needs to control PCH "L_VDD_EN" for power reset, and the
panel spec suggests to
have VDD power off  for >=500ms.

Please refer to the VDD power monitoring image:
http://imageshack.us/photo/my-images/827/auoi.jpg/

Need help to fix the issue in driver.

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Re: Garbage on screen when switching resolution after BIOS post

[Daniel Vetter]

On Tue, Oct 04, 2011 at 05:53:08PM +0800, meteor wrote:
> We are developing a Linux solution. Our platform is using Intel SandyBridge
> and its VGA
> (kernel 2.6.35.8, 915 KMS driver).
> 
> We found system will show garbage at the moment VGA is hand over to OS after
> BIOS POST.
> The symptom doesn’t happen in WIN 7.
> After checking with EE, the LCD_VDD_EN pin is pull low again when boot to
> Win 7.
> However, this pin is not pull low when boot to Linux.
> 
> After BIOS POST, there’s a power reset during driver loading for resolution
> pattern sending.
> It’s why driver needs to control PCH "L_VDD_EN" for power reset, and the
> panel spec suggests to
> have VDD power off  for >=500ms.
> 
> Please refer to the VDD power monitoring image:
> http://imageshack.us/photo/my-images/827/auoi.jpg/
> 
> Need help to fix the issue in driver.

Sounds like you need Keith's eDP power sequencing rework. Afaik you can
grab the latest version here:

http://cgit.freedesktop.org/~keithp/linux/log/?h=macbook-air

Testing feedback highly welcome (and with some details about the panel
type/hw, if possible).

Yours, Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
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Re: Garbage on screen when switching resolution after BIOS post

[Keith Packard]

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On Tue, 4 Oct 2011 17:53:08 +0800, meteor <meteor@ms1.url.com.tw> wrote:

> Please refer to the VDD power monitoring image:
> http://imageshack.us/photo/my-images/827/auoi.jpg/

Nice picture. As Daniel mentioned, you'll want to try my eDP power
sequencing changes and see what they do.

I'm not sure they will though -- my understanding of the eDP spec is
that if we drop VDD, we must hold it low for the specified interval, but
I haven't found anything saying that we must lower VDD when disabling
and re-enabling the display.

Given that the VDD low interval is often quite long (500ms or more), I'd
prefer to avoid doing this when booting the operating system.

I wonder if the final solution will be to move the whole DP link
training and eDP power sequencing stuff to a separate thread to keep
that out of the sequential path of the mode setting code which is run
when the driver loads.

-- 
keith.packard@intel.com

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