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From: Robert Richter <robert.richter@amd.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: "Andi Kleen" <andi@firstfloor.org>, "Ingo Molnar" <mingo@elte.hu>,
	"Stephane Eranian" <eranian@google.com>,
	LKML <linux-kernel@vger.kernel.org>,
	"Don Zickus" <dzickus@redhat.com>, acme <acme@ghostprotocols.net>,
	"Frédéric Weisbecker" <fweisbec@gmail.com>,
	"Thomas Gleixner" <tglx@linutronix.de>
Subject: Re: [V3][PATCH 0/7] perf, x86: Implement AMD IBS
Date: Tue, 4 Oct 2011 19:16:03 +0200	[thread overview]
Message-ID: <20111004171603.GI21506@erda.amd.com> (raw)
In-Reply-To: <1317746709.32543.23.camel@twins>

On 04.10.11 12:45:09, Peter Zijlstra wrote:
> I would much prefer perf {ibs,pebs} commands implemented in C, so that
> normal people can change/improve them too.

Would a perf {ibs,pebs} be an ascii dump or so? Then I just would
better extend perf-report (-D option) to support decoding of raw
samples from dynamically pmus. Something like:

# perf report -D
[...]
. ... raw event: size 88 bytes
.  0000:  01 00 00 00 02 00 58 00 6d 11 00 00 6d 11 00 00  ......X.m...m...
.  0010:  00 80 86 b7 00 00 00 00 00 10 01 00 00 00 00 00  ................
.  0020:  00 00 00 00 00 00 00 00 2f 6c 69 62 2f 6c 69 62  ......../lib/lib
.  0030:  7a 2e 73 6f 2e 31 2e 32 2e 33 00 00 00 00 00 00  z.so.1.2.3......
.  0040:  00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
.  0050:  00 00 00 00 00 00 00 00                          ........
.  # IBS sample (ibs_fetch):
.  # IbsFetchCtl          = 0x0000000000000000
.  #   IbsFetchMaxCnt=0
.  #   IbsFetchCnt=0
.  #   IbsFetchLat=0
.  #   IbsFetchEn=0
.  #   IbsFetchVal=0
.  #   IbsFetchComp=0
.  #   IbsIcMiss=0
.  #   IbsPhyAddrValid=0
.  #   IbsL1TlbPgSz=0
.  #   IbsL1TlbMiss=0
.  #   IbsL2TlbMiss=0
.  #   IbsRandEn=0
.  # IbsFetchLinAd        = 0x00000000813e8b80
.  #   IbsFetchLinAd=0xffffffff813e8b80
.  # IbsFetchPhysAd       = 0x00000000013e8b80
.  #   IbsFetchPhysAd=0x13e8b80
[...]

(Data decoding not correct in this example.)

This wouln't require architecture specific commands.

-Robert

-- 
Advanced Micro Devices, Inc.
Operating System Research Center


  reply	other threads:[~2011-10-04 17:16 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-09-21  9:30 [V3][PATCH 0/7] perf, x86: Implement AMD IBS Robert Richter
2011-09-21  9:30 ` [V3][PATCH 1/7] perf, x86: share IBS macros between perf and oprofile Robert Richter
2011-09-21  9:30 ` [V3][PATCH 2/7] perf, x86: Implement IBS initialization Robert Richter
2011-09-21  9:30 ` [V3][PATCH 3/7] perf, x86: Implement IBS event configuration Robert Richter
2011-09-21  9:30 ` [V3][PATCH 4/7] perf, x86: Implement IBS interrupt handler Robert Richter
2011-09-22 21:51   ` Andi Kleen
2011-09-23  8:44     ` Robert Richter
2011-09-21  9:30 ` [V3][PATCH 5/7] perf, x86: Implement IBS pmu control ops Robert Richter
2011-09-21  9:30 ` [V3][PATCH 6/7] perf, x86: Implement 64 bit counter support for IBS Robert Richter
2011-09-21  9:30 ` [V3][PATCH 7/7] perf, x86: Example code for AMD IBS Robert Richter
2011-09-23 11:48 ` [V3][PATCH 0/7] perf, x86: Implement " Peter Zijlstra
2011-09-23 12:20   ` Robert Richter
2011-09-23 22:28     ` Andi Kleen
2011-09-25 15:20       ` David Ahern
2011-09-25 15:26         ` Andi Kleen
2011-09-25 15:29           ` David Ahern
2011-10-04 12:35       ` Stephane Eranian
2011-10-04 13:18         ` Andi Kleen
2011-10-04 13:20           ` Stephane Eranian
2011-10-04  8:27     ` Peter Zijlstra
2011-10-04  8:54       ` Ingo Molnar
2011-10-04 14:26         ` Robert Richter
2011-10-10 14:48           ` Robert Richter
2011-10-12  7:04           ` Ingo Molnar
2011-10-04 16:41         ` Andi Kleen
2011-10-04 16:45           ` Peter Zijlstra
2011-10-04 17:16             ` Robert Richter [this message]
2011-10-04 17:42               ` Andi Kleen
2011-10-10  6:05             ` Ingo Molnar

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