From: Andi Kleen <andi@firstfloor.org>
To: Robert Richter <robert.richter@amd.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@elte.hu>,
Stephane Eranian <eranian@google.com>,
LKML <linux-kernel@vger.kernel.org>,
Don Zickus <dzickus@redhat.com>
Subject: Re: [V3][PATCH 0/7] perf, x86: Implement AMD IBS
Date: Fri, 23 Sep 2011 15:28:49 -0700 [thread overview]
Message-ID: <m2hb42ki5a.fsf@firstfloor.org> (raw)
In-Reply-To: <20110923122014.GP6063@erda.amd.com> (Robert Richter's message of "Fri, 23 Sep 2011 14:20:14 +0200")
Robert Richter <robert.richter@amd.com> writes:
>
> I think we could extend perf report to parse also ibs samples. The
> only thing we need for it should be the pmu name/type mapping in the
> perf.data header and the pmu type in the sample. See my comment on
> Stephane's patch '[PATCH] perf: make perf.data more self-descriptive
> (v5)'.
I would like to have a similar user tool for Intel PEBS data.
I have some hacks currently to dump more data from the PEBS record and
it's useful for some situations. I was actually thinking of adapting
Robert's tool, but integrating it into other tools is fine too.
Sometimes a "perf print-samples" to print individual samples
would be useful too (it's already possible with -R, but very unfriendly
without post processing)
-Andi
--
ak@linux.intel.com -- Speaking for myself only
next prev parent reply other threads:[~2011-09-23 22:28 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-21 9:30 [V3][PATCH 0/7] perf, x86: Implement AMD IBS Robert Richter
2011-09-21 9:30 ` [V3][PATCH 1/7] perf, x86: share IBS macros between perf and oprofile Robert Richter
2011-09-21 9:30 ` [V3][PATCH 2/7] perf, x86: Implement IBS initialization Robert Richter
2011-09-21 9:30 ` [V3][PATCH 3/7] perf, x86: Implement IBS event configuration Robert Richter
2011-09-21 9:30 ` [V3][PATCH 4/7] perf, x86: Implement IBS interrupt handler Robert Richter
2011-09-22 21:51 ` Andi Kleen
2011-09-23 8:44 ` Robert Richter
2011-09-21 9:30 ` [V3][PATCH 5/7] perf, x86: Implement IBS pmu control ops Robert Richter
2011-09-21 9:30 ` [V3][PATCH 6/7] perf, x86: Implement 64 bit counter support for IBS Robert Richter
2011-09-21 9:30 ` [V3][PATCH 7/7] perf, x86: Example code for AMD IBS Robert Richter
2011-09-23 11:48 ` [V3][PATCH 0/7] perf, x86: Implement " Peter Zijlstra
2011-09-23 12:20 ` Robert Richter
2011-09-23 22:28 ` Andi Kleen [this message]
2011-09-25 15:20 ` David Ahern
2011-09-25 15:26 ` Andi Kleen
2011-09-25 15:29 ` David Ahern
2011-10-04 12:35 ` Stephane Eranian
2011-10-04 13:18 ` Andi Kleen
2011-10-04 13:20 ` Stephane Eranian
2011-10-04 8:27 ` Peter Zijlstra
2011-10-04 8:54 ` Ingo Molnar
2011-10-04 14:26 ` Robert Richter
2011-10-10 14:48 ` Robert Richter
2011-10-12 7:04 ` Ingo Molnar
2011-10-04 16:41 ` Andi Kleen
2011-10-04 16:45 ` Peter Zijlstra
2011-10-04 17:16 ` Robert Richter
2011-10-04 17:42 ` Andi Kleen
2011-10-10 6:05 ` Ingo Molnar
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