From: Andi Kleen <andi@firstfloor.org>
To: Robert Richter <robert.richter@amd.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@elte.hu>,
Stephane Eranian <eranian@google.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [V3][PATCH 4/7] perf, x86: Implement IBS interrupt handler
Date: Thu, 22 Sep 2011 14:51:34 -0700 [thread overview]
Message-ID: <m2litgjleh.fsf@firstfloor.org> (raw)
In-Reply-To: <1316597423-25723-5-git-send-email-robert.richter@amd.com> (Robert Richter's message of "Wed, 21 Sep 2011 11:30:20 +0200")
Robert Richter <robert.richter@amd.com> writes:
>
> +static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
> +{
> + struct perf_event *event = NULL;
> + struct hw_perf_event *hwc = &event->hw;
> + struct perf_sample_data data;
> + struct perf_raw_record raw;
> + struct pt_regs regs;
> + struct perf_ibs_data ibs_data;
> + int offset, size;
> + unsigned int msr;
> + u64 *buf;
> +
> + msr = hwc->config_base;
> + buf = ibs_data.regs;
> + rdmsrl(msr, *buf);
> + if (!(*buf++ & perf_ibs->valid_mask))
> + return 0;
No check if the NMI is really caused by IBS? Very nasty.
This will not interoperate well with other NMIs.
-Andi
--
ak@linux.intel.com -- Speaking for myself only
next prev parent reply other threads:[~2011-09-22 21:51 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-21 9:30 [V3][PATCH 0/7] perf, x86: Implement AMD IBS Robert Richter
2011-09-21 9:30 ` [V3][PATCH 1/7] perf, x86: share IBS macros between perf and oprofile Robert Richter
2011-09-21 9:30 ` [V3][PATCH 2/7] perf, x86: Implement IBS initialization Robert Richter
2011-09-21 9:30 ` [V3][PATCH 3/7] perf, x86: Implement IBS event configuration Robert Richter
2011-09-21 9:30 ` [V3][PATCH 4/7] perf, x86: Implement IBS interrupt handler Robert Richter
2011-09-22 21:51 ` Andi Kleen [this message]
2011-09-23 8:44 ` Robert Richter
2011-09-21 9:30 ` [V3][PATCH 5/7] perf, x86: Implement IBS pmu control ops Robert Richter
2011-09-21 9:30 ` [V3][PATCH 6/7] perf, x86: Implement 64 bit counter support for IBS Robert Richter
2011-09-21 9:30 ` [V3][PATCH 7/7] perf, x86: Example code for AMD IBS Robert Richter
2011-09-23 11:48 ` [V3][PATCH 0/7] perf, x86: Implement " Peter Zijlstra
2011-09-23 12:20 ` Robert Richter
2011-09-23 22:28 ` Andi Kleen
2011-09-25 15:20 ` David Ahern
2011-09-25 15:26 ` Andi Kleen
2011-09-25 15:29 ` David Ahern
2011-10-04 12:35 ` Stephane Eranian
2011-10-04 13:18 ` Andi Kleen
2011-10-04 13:20 ` Stephane Eranian
2011-10-04 8:27 ` Peter Zijlstra
2011-10-04 8:54 ` Ingo Molnar
2011-10-04 14:26 ` Robert Richter
2011-10-10 14:48 ` Robert Richter
2011-10-12 7:04 ` Ingo Molnar
2011-10-04 16:41 ` Andi Kleen
2011-10-04 16:45 ` Peter Zijlstra
2011-10-04 17:16 ` Robert Richter
2011-10-04 17:42 ` Andi Kleen
2011-10-10 6:05 ` Ingo Molnar
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