[PATCH 12/12] MIPS: Netlogic: Mark Netlogic chips as SMT capable

[PATCH 12/12] MIPS: Netlogic: Mark Netlogic chips as SMT capable

[Hillf Danton]

Netlogic XLR chip has multiple cores. Each core includes four integrated
hardware threads, and they share L1 data and instruction caches.

If the chip is marked to be SMT capable, scheduler then could do more, say,
idle load balancing.

Changes are now confined only to the code of XLR, and hardware is probed
to get core ID for correct setup.

[jayachandranc: simplified and adapted for new merged XLR/XLP code]

Signed-off-by: Hillf Danton <dhillf@gmail.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
---
 arch/mips/netlogic/common/smp.c |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 4657fe8..7249f93 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -108,9 +108,16 @@ void nlm_early_init_secondary(int cpu)
  */
 static void __cpuinit nlm_init_secondary(void)
 {
+	current_cpu_data.core = hard_smp_processor_id() / 4;
 	nlm_smp_irq_init();
 }
 
+void nlm_prepare_cpus(unsigned int max_cpus)
+{
+	/* declare we are SMT capable */
+	smp_num_siblings = nlm_threads_per_core;
+}
+
 void nlm_smp_finish(void)
 {
 #ifdef notyet
@@ -179,10 +186,6 @@ void __init nlm_smp_setup(void)
 	nlm_set_nmi_handler(nlm_boot_secondary_cpus);
 }
 
-void nlm_prepare_cpus(unsigned int max_cpus)
-{
-}
-
 static int nlm_parse_cpumask(u32 cpu_mask)
 {
 	uint32_t core0_thr_mask, core_thr_mask;
-- 
1.7.4.1

[PATCH 12/12] MIPS: Netlogic: Mark Netlogic chips as SMT capable

[Hillf Danton]

Netlogic XLR chip has multiple cores. Each core includes four integrated
hardware threads, and they share L1 data and instruction caches.

If the chip is marked to be SMT capable, scheduler then could do more, say,
idle load balancing.

Changes are now confined only to the code of XLR, and hardware is probed
to get core ID for correct setup.

[jayachandranc: simplified and adapted for new merged XLR/XLP code]

Signed-off-by: Hillf Danton <dhillf@gmail.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
---
 arch/mips/netlogic/common/smp.c |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 4657fe8..7249f93 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -108,9 +108,16 @@ void nlm_early_init_secondary(int cpu)
  */
 static void __cpuinit nlm_init_secondary(void)
 {
+	current_cpu_data.core = hard_smp_processor_id() / 4;
 	nlm_smp_irq_init();
 }
 
+void nlm_prepare_cpus(unsigned int max_cpus)
+{
+	/* declare we are SMT capable */
+	smp_num_siblings = nlm_threads_per_core;
+}
+
 void nlm_smp_finish(void)
 {
 #ifdef notyet
@@ -179,10 +186,6 @@ void __init nlm_smp_setup(void)
 	nlm_set_nmi_handler(nlm_boot_secondary_cpus);
 }
 
-void nlm_prepare_cpus(unsigned int max_cpus)
-{
-}
-
 static int nlm_parse_cpumask(u32 cpu_mask)
 {
 	uint32_t core0_thr_mask, core_thr_mask;
-- 
1.7.4.1

[PATCH 12/12] MIPS: Netlogic: Mark Netlogic chips as SMT capable

[Hillf Danton]

Netlogic XLR chip has multiple cores. Each core includes four integrated
hardware threads, and they share L1 data and instruction caches.

If the chip is marked to be SMT capable, scheduler then could do more, say,
idle load balancing.

Changes are now confined only to the code of XLR, and hardware is probed
to get core ID for correct setup.

[jayachandranc: simplified and adapted for new merged XLR/XLP code]

Signed-off-by: Hillf Danton <dhillf@gmail.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
---
 arch/mips/netlogic/common/smp.c |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 476c93e..db17f49 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -108,9 +108,16 @@ void nlm_early_init_secondary(int cpu)
  */
 static void __cpuinit nlm_init_secondary(void)
 {
+	current_cpu_data.core = hard_smp_processor_id() / 4;
 	nlm_smp_irq_init();
 }
 
+void nlm_prepare_cpus(unsigned int max_cpus)
+{
+	/* declare we are SMT capable */
+	smp_num_siblings = nlm_threads_per_core;
+}
+
 void nlm_smp_finish(void)
 {
 #ifdef notyet
@@ -183,10 +190,6 @@ void __init nlm_smp_setup(void)
 	nlm_set_nmi_handler(nlm_boot_secondary_cpus);
 }
 
-void nlm_prepare_cpus(unsigned int max_cpus)
-{
-}
-
 static int nlm_parse_cpumask(u32 cpu_mask)
 {
 	uint32_t core0_thr_mask, core_thr_mask;
-- 
1.7.5.4

[PATCH 12/12] MIPS: Netlogic: Mark Netlogic chips as SMT capable

[Hillf Danton]

Netlogic XLR chip has multiple cores. Each core includes four integrated
hardware threads, and they share L1 data and instruction caches.

If the chip is marked to be SMT capable, scheduler then could do more, say,
idle load balancing.

Changes are now confined only to the code of XLR, and hardware is probed
to get core ID for correct setup.

[jayachandranc: simplified and adapted for new merged XLR/XLP code]

Signed-off-by: Hillf Danton <dhillf@gmail.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
---
 arch/mips/netlogic/common/smp.c |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 476c93e..db17f49 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -108,9 +108,16 @@ void nlm_early_init_secondary(int cpu)
  */
 static void __cpuinit nlm_init_secondary(void)
 {
+	current_cpu_data.core = hard_smp_processor_id() / 4;
 	nlm_smp_irq_init();
 }
 
+void nlm_prepare_cpus(unsigned int max_cpus)
+{
+	/* declare we are SMT capable */
+	smp_num_siblings = nlm_threads_per_core;
+}
+
 void nlm_smp_finish(void)
 {
 #ifdef notyet
@@ -183,10 +190,6 @@ void __init nlm_smp_setup(void)
 	nlm_set_nmi_handler(nlm_boot_secondary_cpus);
 }
 
-void nlm_prepare_cpus(unsigned int max_cpus)
-{
-}
-
 static int nlm_parse_cpumask(u32 cpu_mask)
 {
 	uint32_t core0_thr_mask, core_thr_mask;
-- 
1.7.5.4

Re: [PATCH 12/12] MIPS: Netlogic: Mark Netlogic chips as SMT capable

[Ralf Baechle]

On Fri, Nov 11, 2011 at 05:11:08PM +0530, Hillf Danton wrote:
> Date:   Fri, 11 Nov 2011 17:11:08 +0530
> From: Hillf Danton <dhillf@gmail.com>

Normally if you're resending other people's patches they should be sent
out with your email in the email's From: header and with the patch
author's name and Email address in a From: line in the first (important,
otherwise git won't parse it right) of the body.  Somehow here Hillf
ended up in the From: header which may be confusing, might upset him
and might also trigger spam filters.

No need to resend but you may want to fix that for the next batch of
patches.

  Ralf

Re: [PATCH 12/12] MIPS: Netlogic: Mark Netlogic chips as SMT capable

[Ralf Baechle]

On Fri, Nov 11, 2011 at 12:54:36PM +0000, Ralf Baechle wrote:

> On Fri, Nov 11, 2011 at 05:11:08PM +0530, Hillf Danton wrote:
> > Date:   Fri, 11 Nov 2011 17:11:08 +0530
> > From: Hillf Danton <dhillf@gmail.com>
> 
> Normally if you're resending other people's patches they should be sent
> out with your email in the email's From: header and with the patch
> author's name and Email address in a From: line in the first (important,
> otherwise git won't parse it right) of the body.  Somehow here Hillf
> ended up in the From: header which may be confusing, might upset him
> and might also trigger spam filters.
> 
> No need to resend but you may want to fix that for the next batch of
> patches.

And promptly the reply went to Hillf, whops :)

  Ralf

Re: [PATCH 12/12] MIPS: Netlogic: Mark Netlogic chips as SMT capable

[Hillf Danton]

With Jayachandran Cced

On Fri, Nov 11, 2011 at 8:54 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Fri, Nov 11, 2011 at 05:11:08PM +0530, Hillf Danton wrote:
>> Date:   Fri, 11 Nov 2011 17:11:08 +0530
>> From: Hillf Danton <dhillf@gmail.com>
>
> Normally if you're resending other people's patches they should be sent
> out with your email in the email's From: header and with the patch
> author's name and Email address in a From: line in the first (important,
> otherwise git won't parse it right) of the body.  Somehow here Hillf
> ended up in the From: header which may be confusing, might upset him
> and might also trigger spam filters.
>
> No need to resend but you may want to fix that for the next batch of
> patches.
>
Hi  Ralf,

The patch was delivered by me, and reprepared under ideas and comments from
you and Jayachandran, thanks. It was fine tuned, and SOB, by Jayachandran, and
included in this patchset, which is far beyond my capability, for supporting
Netlogic chips. And please reconsider the patchset.

Thanks

Hillf

Re: [PATCH 12/12] MIPS: Netlogic: Mark Netlogic chips as SMT capable

[Ralf Baechle]

On Fri, Nov 11, 2011 at 09:39:00PM +0800, Hillf Danton wrote:

> The patch was delivered by me, and reprepared under ideas and comments from
> you and Jayachandran, thanks. It was fine tuned, and SOB, by Jayachandran, and
> included in this patchset, which is far beyond my capability, for supporting
> Netlogic chips. And please reconsider the patchset.

This was just a comment on the mechanics of sending patches, not a review
of the patch itself - in fact I think it's fine.

What seems to have happened is that Jayachandran prepared the patches
with git-format-patch, then sent them out using mutt -H, not as the
authors of git had intended using git-send-email.  Git-send-email
puts the sender's email address into the from header and inserts a From:
into the first line of the body, where needed.

On the receiving side it doesn't change a thing - the patch would have
looked exactly the same after being applied to git but as elaborated
before, there are other problems.

  Ralf

Re: [PATCH 12/12] MIPS: Netlogic: Mark Netlogic chips as SMT capable

[Ralf Baechle]

Queued for 3.3.  Thanks,

  Ralf