* [PATCH 0/5] MIPS: Octeon: PCI{,e} updates for Octeon II SOCs
@ 2011-11-15 23:46 ddaney.cavm
2011-11-15 23:46 ` [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definitions for new chips ddaney.cavm
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: ddaney.cavm @ 2011-11-15 23:46 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney
From: David Daney <david.daney@cavium.com>
Nothing earth shattering. The bulk of the change is the register
definitions for the new PCIe hardware.
David Daney (5):
MIPS: Octeon: Update SOC PCI related register definitions for new
chips.
MIPS: Octeon: Update feature test functions for new chips and
features.
MIPS: Octeon: Update DMA mapping operations for OCTEON II processors.
MIPS: Octeon: Update PCI Latency timer, PCIe payload, and PCIe max
read to allow larger transactions
MIPS: Octeon: Add support for OCTEON II PCIe
arch/mips/cavium-octeon/dma-octeon.c | 23 +-
arch/mips/include/asm/octeon/cvmx-dpi-defs.h | 643 +++++++
arch/mips/include/asm/octeon/cvmx-npei-defs.h | 4 +-
arch/mips/include/asm/octeon/cvmx-pciercx-defs.h | 609 ++++++-
arch/mips/include/asm/octeon/cvmx-pemx-defs.h | 509 +++++
arch/mips/include/asm/octeon/cvmx-pexp-defs.h | 19 +-
arch/mips/include/asm/octeon/cvmx-sli-defs.h | 2172 ++++++++++++++++++++++
arch/mips/include/asm/octeon/cvmx-sriox-defs.h | 1036 +++++++++++
arch/mips/include/asm/octeon/cvmx.h | 42 +-
arch/mips/include/asm/octeon/octeon-feature.h | 114 ++-
arch/mips/include/asm/octeon/pci-octeon.h | 3 +-
arch/mips/pci/pci-octeon.c | 26 +-
arch/mips/pci/pcie-octeon.c | 1349 ++++++++++----
13 files changed, 6097 insertions(+), 452 deletions(-)
create mode 100644 arch/mips/include/asm/octeon/cvmx-dpi-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pemx-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-sli-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-sriox-defs.h
--
1.7.2.3
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definitions for new chips.
2011-11-15 23:46 [PATCH 0/5] MIPS: Octeon: PCI{,e} updates for Octeon II SOCs ddaney.cavm
@ 2011-11-15 23:46 ` ddaney.cavm
2011-11-16 0:59 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 2/5] MIPS: Octeon: Update feature test functions for new chips and features ddaney.cavm
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: ddaney.cavm @ 2011-11-15 23:46 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney
From: David Daney <david.daney@cavium.com>
Signed-off-by: David Daney <david.daney@cavium.com>
---
arch/mips/include/asm/octeon/cvmx-dpi-defs.h | 643 +++++++
arch/mips/include/asm/octeon/cvmx-npei-defs.h | 4 +-
arch/mips/include/asm/octeon/cvmx-pciercx-defs.h | 609 ++++++-
arch/mips/include/asm/octeon/cvmx-pemx-defs.h | 509 +++++
arch/mips/include/asm/octeon/cvmx-pexp-defs.h | 19 +-
arch/mips/include/asm/octeon/cvmx-sli-defs.h | 2172 ++++++++++++++++++++++
arch/mips/include/asm/octeon/cvmx-sriox-defs.h | 1036 +++++++++++
7 files changed, 4909 insertions(+), 83 deletions(-)
create mode 100644 arch/mips/include/asm/octeon/cvmx-dpi-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-pemx-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-sli-defs.h
create mode 100644 arch/mips/include/asm/octeon/cvmx-sriox-defs.h
diff --git a/arch/mips/include/asm/octeon/cvmx-dpi-defs.h b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
new file mode 100644
index 0000000..c34ad04
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-dpi-defs.h
@@ -0,0 +1,643 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_DPI_DEFS_H__
+#define __CVMX_DPI_DEFS_H__
+
+#define CVMX_DPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x0001DF0000000000ull))
+#define CVMX_DPI_CTL (CVMX_ADD_IO_SEG(0x0001DF0000000040ull))
+#define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x0001DF0000000048ull))
+#define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_DMA_PPX_CNT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000B00ull) + ((offset) & 31) * 8)
+#define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
+#define CVMX_DPI_INFO_REG (CVMX_ADD_IO_SEG(0x0001DF0000000980ull))
+#define CVMX_DPI_INT_EN (CVMX_ADD_IO_SEG(0x0001DF0000000010ull))
+#define CVMX_DPI_INT_REG (CVMX_ADD_IO_SEG(0x0001DF0000000008ull))
+#define CVMX_DPI_NCBX_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001DF0000000800ull))
+#define CVMX_DPI_PINT_INFO (CVMX_ADD_IO_SEG(0x0001DF0000000830ull))
+#define CVMX_DPI_PKT_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000078ull))
+#define CVMX_DPI_REQ_ERR_RSP (CVMX_ADD_IO_SEG(0x0001DF0000000058ull))
+#define CVMX_DPI_REQ_ERR_RSP_EN (CVMX_ADD_IO_SEG(0x0001DF0000000068ull))
+#define CVMX_DPI_REQ_ERR_RST (CVMX_ADD_IO_SEG(0x0001DF0000000060ull))
+#define CVMX_DPI_REQ_ERR_RST_EN (CVMX_ADD_IO_SEG(0x0001DF0000000070ull))
+#define CVMX_DPI_REQ_ERR_SKIP_COMP (CVMX_ADD_IO_SEG(0x0001DF0000000838ull))
+#define CVMX_DPI_REQ_GBL_EN (CVMX_ADD_IO_SEG(0x0001DF0000000050ull))
+#define CVMX_DPI_SLI_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000900ull) + ((offset) & 3) * 8)
+#define CVMX_DPI_SLI_PRTX_ERR_INFO(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000940ull) + ((offset) & 3) * 8)
+
+union cvmx_dpi_bist_status {
+ uint64_t u64;
+ struct cvmx_dpi_bist_status_s {
+ uint64_t reserved_47_63:17;
+ uint64_t bist:47;
+ } s;
+ struct cvmx_dpi_bist_status_s cn61xx;
+ struct cvmx_dpi_bist_status_cn63xx {
+ uint64_t reserved_45_63:19;
+ uint64_t bist:45;
+ } cn63xx;
+ struct cvmx_dpi_bist_status_cn63xxp1 {
+ uint64_t reserved_37_63:27;
+ uint64_t bist:37;
+ } cn63xxp1;
+ struct cvmx_dpi_bist_status_s cn66xx;
+ struct cvmx_dpi_bist_status_cn63xx cn68xx;
+ struct cvmx_dpi_bist_status_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_ctl {
+ uint64_t u64;
+ struct cvmx_dpi_ctl_s {
+ uint64_t reserved_2_63:62;
+ uint64_t clk:1;
+ uint64_t en:1;
+ } s;
+ struct cvmx_dpi_ctl_cn61xx {
+ uint64_t reserved_1_63:63;
+ uint64_t en:1;
+ } cn61xx;
+ struct cvmx_dpi_ctl_s cn63xx;
+ struct cvmx_dpi_ctl_s cn63xxp1;
+ struct cvmx_dpi_ctl_s cn66xx;
+ struct cvmx_dpi_ctl_s cn68xx;
+ struct cvmx_dpi_ctl_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_counts {
+ uint64_t u64;
+ struct cvmx_dpi_dmax_counts_s {
+ uint64_t reserved_39_63:25;
+ uint64_t fcnt:7;
+ uint64_t dbell:32;
+ } s;
+ struct cvmx_dpi_dmax_counts_s cn61xx;
+ struct cvmx_dpi_dmax_counts_s cn63xx;
+ struct cvmx_dpi_dmax_counts_s cn63xxp1;
+ struct cvmx_dpi_dmax_counts_s cn66xx;
+ struct cvmx_dpi_dmax_counts_s cn68xx;
+ struct cvmx_dpi_dmax_counts_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_dbell {
+ uint64_t u64;
+ struct cvmx_dpi_dmax_dbell_s {
+ uint64_t reserved_16_63:48;
+ uint64_t dbell:16;
+ } s;
+ struct cvmx_dpi_dmax_dbell_s cn61xx;
+ struct cvmx_dpi_dmax_dbell_s cn63xx;
+ struct cvmx_dpi_dmax_dbell_s cn63xxp1;
+ struct cvmx_dpi_dmax_dbell_s cn66xx;
+ struct cvmx_dpi_dmax_dbell_s cn68xx;
+ struct cvmx_dpi_dmax_dbell_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_err_rsp_status {
+ uint64_t u64;
+ struct cvmx_dpi_dmax_err_rsp_status_s {
+ uint64_t reserved_6_63:58;
+ uint64_t status:6;
+ } s;
+ struct cvmx_dpi_dmax_err_rsp_status_s cn61xx;
+ struct cvmx_dpi_dmax_err_rsp_status_s cn66xx;
+ struct cvmx_dpi_dmax_err_rsp_status_s cn68xx;
+ struct cvmx_dpi_dmax_err_rsp_status_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_ibuff_saddr {
+ uint64_t u64;
+ struct cvmx_dpi_dmax_ibuff_saddr_s {
+ uint64_t reserved_62_63:2;
+ uint64_t csize:14;
+ uint64_t reserved_41_47:7;
+ uint64_t idle:1;
+ uint64_t saddr:33;
+ uint64_t reserved_0_6:7;
+ } s;
+ struct cvmx_dpi_dmax_ibuff_saddr_cn61xx {
+ uint64_t reserved_62_63:2;
+ uint64_t csize:14;
+ uint64_t reserved_41_47:7;
+ uint64_t idle:1;
+ uint64_t reserved_36_39:4;
+ uint64_t saddr:29;
+ uint64_t reserved_0_6:7;
+ } cn61xx;
+ struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xx;
+ struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn63xxp1;
+ struct cvmx_dpi_dmax_ibuff_saddr_cn61xx cn66xx;
+ struct cvmx_dpi_dmax_ibuff_saddr_s cn68xx;
+ struct cvmx_dpi_dmax_ibuff_saddr_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_iflight {
+ uint64_t u64;
+ struct cvmx_dpi_dmax_iflight_s {
+ uint64_t reserved_3_63:61;
+ uint64_t cnt:3;
+ } s;
+ struct cvmx_dpi_dmax_iflight_s cn61xx;
+ struct cvmx_dpi_dmax_iflight_s cn66xx;
+ struct cvmx_dpi_dmax_iflight_s cn68xx;
+ struct cvmx_dpi_dmax_iflight_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_naddr {
+ uint64_t u64;
+ struct cvmx_dpi_dmax_naddr_s {
+ uint64_t reserved_40_63:24;
+ uint64_t addr:40;
+ } s;
+ struct cvmx_dpi_dmax_naddr_cn61xx {
+ uint64_t reserved_36_63:28;
+ uint64_t addr:36;
+ } cn61xx;
+ struct cvmx_dpi_dmax_naddr_cn61xx cn63xx;
+ struct cvmx_dpi_dmax_naddr_cn61xx cn63xxp1;
+ struct cvmx_dpi_dmax_naddr_cn61xx cn66xx;
+ struct cvmx_dpi_dmax_naddr_s cn68xx;
+ struct cvmx_dpi_dmax_naddr_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_reqbnk0 {
+ uint64_t u64;
+ struct cvmx_dpi_dmax_reqbnk0_s {
+ uint64_t state:64;
+ } s;
+ struct cvmx_dpi_dmax_reqbnk0_s cn61xx;
+ struct cvmx_dpi_dmax_reqbnk0_s cn63xx;
+ struct cvmx_dpi_dmax_reqbnk0_s cn63xxp1;
+ struct cvmx_dpi_dmax_reqbnk0_s cn66xx;
+ struct cvmx_dpi_dmax_reqbnk0_s cn68xx;
+ struct cvmx_dpi_dmax_reqbnk0_s cn68xxp1;
+};
+
+union cvmx_dpi_dmax_reqbnk1 {
+ uint64_t u64;
+ struct cvmx_dpi_dmax_reqbnk1_s {
+ uint64_t state:64;
+ } s;
+ struct cvmx_dpi_dmax_reqbnk1_s cn61xx;
+ struct cvmx_dpi_dmax_reqbnk1_s cn63xx;
+ struct cvmx_dpi_dmax_reqbnk1_s cn63xxp1;
+ struct cvmx_dpi_dmax_reqbnk1_s cn66xx;
+ struct cvmx_dpi_dmax_reqbnk1_s cn68xx;
+ struct cvmx_dpi_dmax_reqbnk1_s cn68xxp1;
+};
+
+union cvmx_dpi_dma_control {
+ uint64_t u64;
+ struct cvmx_dpi_dma_control_s {
+ uint64_t reserved_62_63:2;
+ uint64_t dici_mode:1;
+ uint64_t pkt_en1:1;
+ uint64_t ffp_dis:1;
+ uint64_t commit_mode:1;
+ uint64_t pkt_hp:1;
+ uint64_t pkt_en:1;
+ uint64_t reserved_54_55:2;
+ uint64_t dma_enb:6;
+ uint64_t reserved_34_47:14;
+ uint64_t b0_lend:1;
+ uint64_t dwb_denb:1;
+ uint64_t dwb_ichk:9;
+ uint64_t fpa_que:3;
+ uint64_t o_add1:1;
+ uint64_t o_ro:1;
+ uint64_t o_ns:1;
+ uint64_t o_es:2;
+ uint64_t o_mode:1;
+ uint64_t reserved_0_13:14;
+ } s;
+ struct cvmx_dpi_dma_control_s cn61xx;
+ struct cvmx_dpi_dma_control_cn63xx {
+ uint64_t reserved_61_63:3;
+ uint64_t pkt_en1:1;
+ uint64_t ffp_dis:1;
+ uint64_t commit_mode:1;
+ uint64_t pkt_hp:1;
+ uint64_t pkt_en:1;
+ uint64_t reserved_54_55:2;
+ uint64_t dma_enb:6;
+ uint64_t reserved_34_47:14;
+ uint64_t b0_lend:1;
+ uint64_t dwb_denb:1;
+ uint64_t dwb_ichk:9;
+ uint64_t fpa_que:3;
+ uint64_t o_add1:1;
+ uint64_t o_ro:1;
+ uint64_t o_ns:1;
+ uint64_t o_es:2;
+ uint64_t o_mode:1;
+ uint64_t reserved_0_13:14;
+ } cn63xx;
+ struct cvmx_dpi_dma_control_cn63xxp1 {
+ uint64_t reserved_59_63:5;
+ uint64_t commit_mode:1;
+ uint64_t pkt_hp:1;
+ uint64_t pkt_en:1;
+ uint64_t reserved_54_55:2;
+ uint64_t dma_enb:6;
+ uint64_t reserved_34_47:14;
+ uint64_t b0_lend:1;
+ uint64_t dwb_denb:1;
+ uint64_t dwb_ichk:9;
+ uint64_t fpa_que:3;
+ uint64_t o_add1:1;
+ uint64_t o_ro:1;
+ uint64_t o_ns:1;
+ uint64_t o_es:2;
+ uint64_t o_mode:1;
+ uint64_t reserved_0_13:14;
+ } cn63xxp1;
+ struct cvmx_dpi_dma_control_cn63xx cn66xx;
+ struct cvmx_dpi_dma_control_s cn68xx;
+ struct cvmx_dpi_dma_control_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_dma_engx_en {
+ uint64_t u64;
+ struct cvmx_dpi_dma_engx_en_s {
+ uint64_t reserved_8_63:56;
+ uint64_t qen:8;
+ } s;
+ struct cvmx_dpi_dma_engx_en_s cn61xx;
+ struct cvmx_dpi_dma_engx_en_s cn63xx;
+ struct cvmx_dpi_dma_engx_en_s cn63xxp1;
+ struct cvmx_dpi_dma_engx_en_s cn66xx;
+ struct cvmx_dpi_dma_engx_en_s cn68xx;
+ struct cvmx_dpi_dma_engx_en_s cn68xxp1;
+};
+
+union cvmx_dpi_dma_ppx_cnt {
+ uint64_t u64;
+ struct cvmx_dpi_dma_ppx_cnt_s {
+ uint64_t reserved_16_63:48;
+ uint64_t cnt:16;
+ } s;
+ struct cvmx_dpi_dma_ppx_cnt_s cn61xx;
+ struct cvmx_dpi_dma_ppx_cnt_s cn68xx;
+};
+
+union cvmx_dpi_engx_buf {
+ uint64_t u64;
+ struct cvmx_dpi_engx_buf_s {
+ uint64_t reserved_37_63:27;
+ uint64_t compblks:5;
+ uint64_t reserved_9_31:23;
+ uint64_t base:5;
+ uint64_t blks:4;
+ } s;
+ struct cvmx_dpi_engx_buf_s cn61xx;
+ struct cvmx_dpi_engx_buf_cn63xx {
+ uint64_t reserved_8_63:56;
+ uint64_t base:4;
+ uint64_t blks:4;
+ } cn63xx;
+ struct cvmx_dpi_engx_buf_cn63xx cn63xxp1;
+ struct cvmx_dpi_engx_buf_s cn66xx;
+ struct cvmx_dpi_engx_buf_s cn68xx;
+ struct cvmx_dpi_engx_buf_s cn68xxp1;
+};
+
+union cvmx_dpi_info_reg {
+ uint64_t u64;
+ struct cvmx_dpi_info_reg_s {
+ uint64_t reserved_8_63:56;
+ uint64_t ffp:4;
+ uint64_t reserved_2_3:2;
+ uint64_t ncb:1;
+ uint64_t rsl:1;
+ } s;
+ struct cvmx_dpi_info_reg_s cn61xx;
+ struct cvmx_dpi_info_reg_s cn63xx;
+ struct cvmx_dpi_info_reg_cn63xxp1 {
+ uint64_t reserved_2_63:62;
+ uint64_t ncb:1;
+ uint64_t rsl:1;
+ } cn63xxp1;
+ struct cvmx_dpi_info_reg_s cn66xx;
+ struct cvmx_dpi_info_reg_s cn68xx;
+ struct cvmx_dpi_info_reg_s cn68xxp1;
+};
+
+union cvmx_dpi_int_en {
+ uint64_t u64;
+ struct cvmx_dpi_int_en_s {
+ uint64_t reserved_28_63:36;
+ uint64_t sprt3_rst:1;
+ uint64_t sprt2_rst:1;
+ uint64_t sprt1_rst:1;
+ uint64_t sprt0_rst:1;
+ uint64_t reserved_23_23:1;
+ uint64_t req_badfil:1;
+ uint64_t req_inull:1;
+ uint64_t req_anull:1;
+ uint64_t req_undflw:1;
+ uint64_t req_ovrflw:1;
+ uint64_t req_badlen:1;
+ uint64_t req_badadr:1;
+ uint64_t dmadbo:8;
+ uint64_t reserved_2_7:6;
+ uint64_t nfovr:1;
+ uint64_t nderr:1;
+ } s;
+ struct cvmx_dpi_int_en_s cn61xx;
+ struct cvmx_dpi_int_en_cn63xx {
+ uint64_t reserved_26_63:38;
+ uint64_t sprt1_rst:1;
+ uint64_t sprt0_rst:1;
+ uint64_t reserved_23_23:1;
+ uint64_t req_badfil:1;
+ uint64_t req_inull:1;
+ uint64_t req_anull:1;
+ uint64_t req_undflw:1;
+ uint64_t req_ovrflw:1;
+ uint64_t req_badlen:1;
+ uint64_t req_badadr:1;
+ uint64_t dmadbo:8;
+ uint64_t reserved_2_7:6;
+ uint64_t nfovr:1;
+ uint64_t nderr:1;
+ } cn63xx;
+ struct cvmx_dpi_int_en_cn63xx cn63xxp1;
+ struct cvmx_dpi_int_en_s cn66xx;
+ struct cvmx_dpi_int_en_cn63xx cn68xx;
+ struct cvmx_dpi_int_en_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_int_reg {
+ uint64_t u64;
+ struct cvmx_dpi_int_reg_s {
+ uint64_t reserved_28_63:36;
+ uint64_t sprt3_rst:1;
+ uint64_t sprt2_rst:1;
+ uint64_t sprt1_rst:1;
+ uint64_t sprt0_rst:1;
+ uint64_t reserved_23_23:1;
+ uint64_t req_badfil:1;
+ uint64_t req_inull:1;
+ uint64_t req_anull:1;
+ uint64_t req_undflw:1;
+ uint64_t req_ovrflw:1;
+ uint64_t req_badlen:1;
+ uint64_t req_badadr:1;
+ uint64_t dmadbo:8;
+ uint64_t reserved_2_7:6;
+ uint64_t nfovr:1;
+ uint64_t nderr:1;
+ } s;
+ struct cvmx_dpi_int_reg_s cn61xx;
+ struct cvmx_dpi_int_reg_cn63xx {
+ uint64_t reserved_26_63:38;
+ uint64_t sprt1_rst:1;
+ uint64_t sprt0_rst:1;
+ uint64_t reserved_23_23:1;
+ uint64_t req_badfil:1;
+ uint64_t req_inull:1;
+ uint64_t req_anull:1;
+ uint64_t req_undflw:1;
+ uint64_t req_ovrflw:1;
+ uint64_t req_badlen:1;
+ uint64_t req_badadr:1;
+ uint64_t dmadbo:8;
+ uint64_t reserved_2_7:6;
+ uint64_t nfovr:1;
+ uint64_t nderr:1;
+ } cn63xx;
+ struct cvmx_dpi_int_reg_cn63xx cn63xxp1;
+ struct cvmx_dpi_int_reg_s cn66xx;
+ struct cvmx_dpi_int_reg_cn63xx cn68xx;
+ struct cvmx_dpi_int_reg_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_ncbx_cfg {
+ uint64_t u64;
+ struct cvmx_dpi_ncbx_cfg_s {
+ uint64_t reserved_6_63:58;
+ uint64_t molr:6;
+ } s;
+ struct cvmx_dpi_ncbx_cfg_s cn61xx;
+ struct cvmx_dpi_ncbx_cfg_s cn66xx;
+ struct cvmx_dpi_ncbx_cfg_s cn68xx;
+};
+
+union cvmx_dpi_pint_info {
+ uint64_t u64;
+ struct cvmx_dpi_pint_info_s {
+ uint64_t reserved_14_63:50;
+ uint64_t iinfo:6;
+ uint64_t reserved_6_7:2;
+ uint64_t sinfo:6;
+ } s;
+ struct cvmx_dpi_pint_info_s cn61xx;
+ struct cvmx_dpi_pint_info_s cn63xx;
+ struct cvmx_dpi_pint_info_s cn63xxp1;
+ struct cvmx_dpi_pint_info_s cn66xx;
+ struct cvmx_dpi_pint_info_s cn68xx;
+ struct cvmx_dpi_pint_info_s cn68xxp1;
+};
+
+union cvmx_dpi_pkt_err_rsp {
+ uint64_t u64;
+ struct cvmx_dpi_pkt_err_rsp_s {
+ uint64_t reserved_1_63:63;
+ uint64_t pkterr:1;
+ } s;
+ struct cvmx_dpi_pkt_err_rsp_s cn61xx;
+ struct cvmx_dpi_pkt_err_rsp_s cn63xx;
+ struct cvmx_dpi_pkt_err_rsp_s cn63xxp1;
+ struct cvmx_dpi_pkt_err_rsp_s cn66xx;
+ struct cvmx_dpi_pkt_err_rsp_s cn68xx;
+ struct cvmx_dpi_pkt_err_rsp_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rsp {
+ uint64_t u64;
+ struct cvmx_dpi_req_err_rsp_s {
+ uint64_t reserved_8_63:56;
+ uint64_t qerr:8;
+ } s;
+ struct cvmx_dpi_req_err_rsp_s cn61xx;
+ struct cvmx_dpi_req_err_rsp_s cn63xx;
+ struct cvmx_dpi_req_err_rsp_s cn63xxp1;
+ struct cvmx_dpi_req_err_rsp_s cn66xx;
+ struct cvmx_dpi_req_err_rsp_s cn68xx;
+ struct cvmx_dpi_req_err_rsp_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rsp_en {
+ uint64_t u64;
+ struct cvmx_dpi_req_err_rsp_en_s {
+ uint64_t reserved_8_63:56;
+ uint64_t en:8;
+ } s;
+ struct cvmx_dpi_req_err_rsp_en_s cn61xx;
+ struct cvmx_dpi_req_err_rsp_en_s cn63xx;
+ struct cvmx_dpi_req_err_rsp_en_s cn63xxp1;
+ struct cvmx_dpi_req_err_rsp_en_s cn66xx;
+ struct cvmx_dpi_req_err_rsp_en_s cn68xx;
+ struct cvmx_dpi_req_err_rsp_en_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rst {
+ uint64_t u64;
+ struct cvmx_dpi_req_err_rst_s {
+ uint64_t reserved_8_63:56;
+ uint64_t qerr:8;
+ } s;
+ struct cvmx_dpi_req_err_rst_s cn61xx;
+ struct cvmx_dpi_req_err_rst_s cn63xx;
+ struct cvmx_dpi_req_err_rst_s cn63xxp1;
+ struct cvmx_dpi_req_err_rst_s cn66xx;
+ struct cvmx_dpi_req_err_rst_s cn68xx;
+ struct cvmx_dpi_req_err_rst_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_rst_en {
+ uint64_t u64;
+ struct cvmx_dpi_req_err_rst_en_s {
+ uint64_t reserved_8_63:56;
+ uint64_t en:8;
+ } s;
+ struct cvmx_dpi_req_err_rst_en_s cn61xx;
+ struct cvmx_dpi_req_err_rst_en_s cn63xx;
+ struct cvmx_dpi_req_err_rst_en_s cn63xxp1;
+ struct cvmx_dpi_req_err_rst_en_s cn66xx;
+ struct cvmx_dpi_req_err_rst_en_s cn68xx;
+ struct cvmx_dpi_req_err_rst_en_s cn68xxp1;
+};
+
+union cvmx_dpi_req_err_skip_comp {
+ uint64_t u64;
+ struct cvmx_dpi_req_err_skip_comp_s {
+ uint64_t reserved_24_63:40;
+ uint64_t en_rst:8;
+ uint64_t reserved_8_15:8;
+ uint64_t en_rsp:8;
+ } s;
+ struct cvmx_dpi_req_err_skip_comp_s cn61xx;
+ struct cvmx_dpi_req_err_skip_comp_s cn66xx;
+ struct cvmx_dpi_req_err_skip_comp_s cn68xx;
+ struct cvmx_dpi_req_err_skip_comp_s cn68xxp1;
+};
+
+union cvmx_dpi_req_gbl_en {
+ uint64_t u64;
+ struct cvmx_dpi_req_gbl_en_s {
+ uint64_t reserved_8_63:56;
+ uint64_t qen:8;
+ } s;
+ struct cvmx_dpi_req_gbl_en_s cn61xx;
+ struct cvmx_dpi_req_gbl_en_s cn63xx;
+ struct cvmx_dpi_req_gbl_en_s cn63xxp1;
+ struct cvmx_dpi_req_gbl_en_s cn66xx;
+ struct cvmx_dpi_req_gbl_en_s cn68xx;
+ struct cvmx_dpi_req_gbl_en_s cn68xxp1;
+};
+
+union cvmx_dpi_sli_prtx_cfg {
+ uint64_t u64;
+ struct cvmx_dpi_sli_prtx_cfg_s {
+ uint64_t reserved_25_63:39;
+ uint64_t halt:1;
+ uint64_t qlm_cfg:4;
+ uint64_t reserved_17_19:3;
+ uint64_t rd_mode:1;
+ uint64_t reserved_14_15:2;
+ uint64_t molr:6;
+ uint64_t mps_lim:1;
+ uint64_t reserved_5_6:2;
+ uint64_t mps:1;
+ uint64_t mrrs_lim:1;
+ uint64_t reserved_2_2:1;
+ uint64_t mrrs:2;
+ } s;
+ struct cvmx_dpi_sli_prtx_cfg_s cn61xx;
+ struct cvmx_dpi_sli_prtx_cfg_cn63xx {
+ uint64_t reserved_25_63:39;
+ uint64_t halt:1;
+ uint64_t reserved_21_23:3;
+ uint64_t qlm_cfg:1;
+ uint64_t reserved_17_19:3;
+ uint64_t rd_mode:1;
+ uint64_t reserved_14_15:2;
+ uint64_t molr:6;
+ uint64_t mps_lim:1;
+ uint64_t reserved_5_6:2;
+ uint64_t mps:1;
+ uint64_t mrrs_lim:1;
+ uint64_t reserved_2_2:1;
+ uint64_t mrrs:2;
+ } cn63xx;
+ struct cvmx_dpi_sli_prtx_cfg_cn63xx cn63xxp1;
+ struct cvmx_dpi_sli_prtx_cfg_s cn66xx;
+ struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xx;
+ struct cvmx_dpi_sli_prtx_cfg_cn63xx cn68xxp1;
+};
+
+union cvmx_dpi_sli_prtx_err {
+ uint64_t u64;
+ struct cvmx_dpi_sli_prtx_err_s {
+ uint64_t addr:61;
+ uint64_t reserved_0_2:3;
+ } s;
+ struct cvmx_dpi_sli_prtx_err_s cn61xx;
+ struct cvmx_dpi_sli_prtx_err_s cn63xx;
+ struct cvmx_dpi_sli_prtx_err_s cn63xxp1;
+ struct cvmx_dpi_sli_prtx_err_s cn66xx;
+ struct cvmx_dpi_sli_prtx_err_s cn68xx;
+ struct cvmx_dpi_sli_prtx_err_s cn68xxp1;
+};
+
+union cvmx_dpi_sli_prtx_err_info {
+ uint64_t u64;
+ struct cvmx_dpi_sli_prtx_err_info_s {
+ uint64_t reserved_9_63:55;
+ uint64_t lock:1;
+ uint64_t reserved_5_7:3;
+ uint64_t type:1;
+ uint64_t reserved_3_3:1;
+ uint64_t reqq:3;
+ } s;
+ struct cvmx_dpi_sli_prtx_err_info_s cn61xx;
+ struct cvmx_dpi_sli_prtx_err_info_s cn63xx;
+ struct cvmx_dpi_sli_prtx_err_info_s cn63xxp1;
+ struct cvmx_dpi_sli_prtx_err_info_s cn66xx;
+ struct cvmx_dpi_sli_prtx_err_info_s cn68xx;
+ struct cvmx_dpi_sli_prtx_err_info_s cn68xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
index 9899a9d..a3075f7 100644
--- a/arch/mips/include/asm/octeon/cvmx-npei-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2011 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -65,7 +65,7 @@
#define CVMX_NPEI_LAST_WIN_RDATA0 (0x0000000000000600ull)
#define CVMX_NPEI_LAST_WIN_RDATA1 (0x0000000000000610ull)
#define CVMX_NPEI_MEM_ACCESS_CTL (0x00000000000004F0ull)
-#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000340ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) (0x0000000000000280ull + ((offset) & 31) * 16 - 16*12)
#define CVMX_NPEI_MSI_ENB0 (0x0000000000003C50ull)
#define CVMX_NPEI_MSI_ENB1 (0x0000000000003C60ull)
#define CVMX_NPEI_MSI_ENB2 (0x0000000000003C70ull)
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
index f8cb889..7b1dc8b 100644
--- a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2011 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -116,8 +116,12 @@ union cvmx_pciercx_cfg000 {
struct cvmx_pciercx_cfg000_s cn52xxp1;
struct cvmx_pciercx_cfg000_s cn56xx;
struct cvmx_pciercx_cfg000_s cn56xxp1;
+ struct cvmx_pciercx_cfg000_s cn61xx;
struct cvmx_pciercx_cfg000_s cn63xx;
struct cvmx_pciercx_cfg000_s cn63xxp1;
+ struct cvmx_pciercx_cfg000_s cn66xx;
+ struct cvmx_pciercx_cfg000_s cn68xx;
+ struct cvmx_pciercx_cfg000_s cn68xxp1;
};
union cvmx_pciercx_cfg001 {
@@ -152,8 +156,12 @@ union cvmx_pciercx_cfg001 {
struct cvmx_pciercx_cfg001_s cn52xxp1;
struct cvmx_pciercx_cfg001_s cn56xx;
struct cvmx_pciercx_cfg001_s cn56xxp1;
+ struct cvmx_pciercx_cfg001_s cn61xx;
struct cvmx_pciercx_cfg001_s cn63xx;
struct cvmx_pciercx_cfg001_s cn63xxp1;
+ struct cvmx_pciercx_cfg001_s cn66xx;
+ struct cvmx_pciercx_cfg001_s cn68xx;
+ struct cvmx_pciercx_cfg001_s cn68xxp1;
};
union cvmx_pciercx_cfg002 {
@@ -168,8 +176,12 @@ union cvmx_pciercx_cfg002 {
struct cvmx_pciercx_cfg002_s cn52xxp1;
struct cvmx_pciercx_cfg002_s cn56xx;
struct cvmx_pciercx_cfg002_s cn56xxp1;
+ struct cvmx_pciercx_cfg002_s cn61xx;
struct cvmx_pciercx_cfg002_s cn63xx;
struct cvmx_pciercx_cfg002_s cn63xxp1;
+ struct cvmx_pciercx_cfg002_s cn66xx;
+ struct cvmx_pciercx_cfg002_s cn68xx;
+ struct cvmx_pciercx_cfg002_s cn68xxp1;
};
union cvmx_pciercx_cfg003 {
@@ -185,8 +197,12 @@ union cvmx_pciercx_cfg003 {
struct cvmx_pciercx_cfg003_s cn52xxp1;
struct cvmx_pciercx_cfg003_s cn56xx;
struct cvmx_pciercx_cfg003_s cn56xxp1;
+ struct cvmx_pciercx_cfg003_s cn61xx;
struct cvmx_pciercx_cfg003_s cn63xx;
struct cvmx_pciercx_cfg003_s cn63xxp1;
+ struct cvmx_pciercx_cfg003_s cn66xx;
+ struct cvmx_pciercx_cfg003_s cn68xx;
+ struct cvmx_pciercx_cfg003_s cn68xxp1;
};
union cvmx_pciercx_cfg004 {
@@ -198,8 +214,12 @@ union cvmx_pciercx_cfg004 {
struct cvmx_pciercx_cfg004_s cn52xxp1;
struct cvmx_pciercx_cfg004_s cn56xx;
struct cvmx_pciercx_cfg004_s cn56xxp1;
+ struct cvmx_pciercx_cfg004_s cn61xx;
struct cvmx_pciercx_cfg004_s cn63xx;
struct cvmx_pciercx_cfg004_s cn63xxp1;
+ struct cvmx_pciercx_cfg004_s cn66xx;
+ struct cvmx_pciercx_cfg004_s cn68xx;
+ struct cvmx_pciercx_cfg004_s cn68xxp1;
};
union cvmx_pciercx_cfg005 {
@@ -211,8 +231,12 @@ union cvmx_pciercx_cfg005 {
struct cvmx_pciercx_cfg005_s cn52xxp1;
struct cvmx_pciercx_cfg005_s cn56xx;
struct cvmx_pciercx_cfg005_s cn56xxp1;
+ struct cvmx_pciercx_cfg005_s cn61xx;
struct cvmx_pciercx_cfg005_s cn63xx;
struct cvmx_pciercx_cfg005_s cn63xxp1;
+ struct cvmx_pciercx_cfg005_s cn66xx;
+ struct cvmx_pciercx_cfg005_s cn68xx;
+ struct cvmx_pciercx_cfg005_s cn68xxp1;
};
union cvmx_pciercx_cfg006 {
@@ -227,8 +251,12 @@ union cvmx_pciercx_cfg006 {
struct cvmx_pciercx_cfg006_s cn52xxp1;
struct cvmx_pciercx_cfg006_s cn56xx;
struct cvmx_pciercx_cfg006_s cn56xxp1;
+ struct cvmx_pciercx_cfg006_s cn61xx;
struct cvmx_pciercx_cfg006_s cn63xx;
struct cvmx_pciercx_cfg006_s cn63xxp1;
+ struct cvmx_pciercx_cfg006_s cn66xx;
+ struct cvmx_pciercx_cfg006_s cn68xx;
+ struct cvmx_pciercx_cfg006_s cn68xxp1;
};
union cvmx_pciercx_cfg007 {
@@ -256,8 +284,12 @@ union cvmx_pciercx_cfg007 {
struct cvmx_pciercx_cfg007_s cn52xxp1;
struct cvmx_pciercx_cfg007_s cn56xx;
struct cvmx_pciercx_cfg007_s cn56xxp1;
+ struct cvmx_pciercx_cfg007_s cn61xx;
struct cvmx_pciercx_cfg007_s cn63xx;
struct cvmx_pciercx_cfg007_s cn63xxp1;
+ struct cvmx_pciercx_cfg007_s cn66xx;
+ struct cvmx_pciercx_cfg007_s cn68xx;
+ struct cvmx_pciercx_cfg007_s cn68xxp1;
};
union cvmx_pciercx_cfg008 {
@@ -272,8 +304,12 @@ union cvmx_pciercx_cfg008 {
struct cvmx_pciercx_cfg008_s cn52xxp1;
struct cvmx_pciercx_cfg008_s cn56xx;
struct cvmx_pciercx_cfg008_s cn56xxp1;
+ struct cvmx_pciercx_cfg008_s cn61xx;
struct cvmx_pciercx_cfg008_s cn63xx;
struct cvmx_pciercx_cfg008_s cn63xxp1;
+ struct cvmx_pciercx_cfg008_s cn66xx;
+ struct cvmx_pciercx_cfg008_s cn68xx;
+ struct cvmx_pciercx_cfg008_s cn68xxp1;
};
union cvmx_pciercx_cfg009 {
@@ -290,8 +326,12 @@ union cvmx_pciercx_cfg009 {
struct cvmx_pciercx_cfg009_s cn52xxp1;
struct cvmx_pciercx_cfg009_s cn56xx;
struct cvmx_pciercx_cfg009_s cn56xxp1;
+ struct cvmx_pciercx_cfg009_s cn61xx;
struct cvmx_pciercx_cfg009_s cn63xx;
struct cvmx_pciercx_cfg009_s cn63xxp1;
+ struct cvmx_pciercx_cfg009_s cn66xx;
+ struct cvmx_pciercx_cfg009_s cn68xx;
+ struct cvmx_pciercx_cfg009_s cn68xxp1;
};
union cvmx_pciercx_cfg010 {
@@ -303,8 +343,12 @@ union cvmx_pciercx_cfg010 {
struct cvmx_pciercx_cfg010_s cn52xxp1;
struct cvmx_pciercx_cfg010_s cn56xx;
struct cvmx_pciercx_cfg010_s cn56xxp1;
+ struct cvmx_pciercx_cfg010_s cn61xx;
struct cvmx_pciercx_cfg010_s cn63xx;
struct cvmx_pciercx_cfg010_s cn63xxp1;
+ struct cvmx_pciercx_cfg010_s cn66xx;
+ struct cvmx_pciercx_cfg010_s cn68xx;
+ struct cvmx_pciercx_cfg010_s cn68xxp1;
};
union cvmx_pciercx_cfg011 {
@@ -316,8 +360,12 @@ union cvmx_pciercx_cfg011 {
struct cvmx_pciercx_cfg011_s cn52xxp1;
struct cvmx_pciercx_cfg011_s cn56xx;
struct cvmx_pciercx_cfg011_s cn56xxp1;
+ struct cvmx_pciercx_cfg011_s cn61xx;
struct cvmx_pciercx_cfg011_s cn63xx;
struct cvmx_pciercx_cfg011_s cn63xxp1;
+ struct cvmx_pciercx_cfg011_s cn66xx;
+ struct cvmx_pciercx_cfg011_s cn68xx;
+ struct cvmx_pciercx_cfg011_s cn68xxp1;
};
union cvmx_pciercx_cfg012 {
@@ -330,8 +378,12 @@ union cvmx_pciercx_cfg012 {
struct cvmx_pciercx_cfg012_s cn52xxp1;
struct cvmx_pciercx_cfg012_s cn56xx;
struct cvmx_pciercx_cfg012_s cn56xxp1;
+ struct cvmx_pciercx_cfg012_s cn61xx;
struct cvmx_pciercx_cfg012_s cn63xx;
struct cvmx_pciercx_cfg012_s cn63xxp1;
+ struct cvmx_pciercx_cfg012_s cn66xx;
+ struct cvmx_pciercx_cfg012_s cn68xx;
+ struct cvmx_pciercx_cfg012_s cn68xxp1;
};
union cvmx_pciercx_cfg013 {
@@ -344,8 +396,12 @@ union cvmx_pciercx_cfg013 {
struct cvmx_pciercx_cfg013_s cn52xxp1;
struct cvmx_pciercx_cfg013_s cn56xx;
struct cvmx_pciercx_cfg013_s cn56xxp1;
+ struct cvmx_pciercx_cfg013_s cn61xx;
struct cvmx_pciercx_cfg013_s cn63xx;
struct cvmx_pciercx_cfg013_s cn63xxp1;
+ struct cvmx_pciercx_cfg013_s cn66xx;
+ struct cvmx_pciercx_cfg013_s cn68xx;
+ struct cvmx_pciercx_cfg013_s cn68xxp1;
};
union cvmx_pciercx_cfg014 {
@@ -357,8 +413,12 @@ union cvmx_pciercx_cfg014 {
struct cvmx_pciercx_cfg014_s cn52xxp1;
struct cvmx_pciercx_cfg014_s cn56xx;
struct cvmx_pciercx_cfg014_s cn56xxp1;
+ struct cvmx_pciercx_cfg014_s cn61xx;
struct cvmx_pciercx_cfg014_s cn63xx;
struct cvmx_pciercx_cfg014_s cn63xxp1;
+ struct cvmx_pciercx_cfg014_s cn66xx;
+ struct cvmx_pciercx_cfg014_s cn68xx;
+ struct cvmx_pciercx_cfg014_s cn68xxp1;
};
union cvmx_pciercx_cfg015 {
@@ -384,8 +444,12 @@ union cvmx_pciercx_cfg015 {
struct cvmx_pciercx_cfg015_s cn52xxp1;
struct cvmx_pciercx_cfg015_s cn56xx;
struct cvmx_pciercx_cfg015_s cn56xxp1;
+ struct cvmx_pciercx_cfg015_s cn61xx;
struct cvmx_pciercx_cfg015_s cn63xx;
struct cvmx_pciercx_cfg015_s cn63xxp1;
+ struct cvmx_pciercx_cfg015_s cn66xx;
+ struct cvmx_pciercx_cfg015_s cn68xx;
+ struct cvmx_pciercx_cfg015_s cn68xxp1;
};
union cvmx_pciercx_cfg016 {
@@ -406,8 +470,12 @@ union cvmx_pciercx_cfg016 {
struct cvmx_pciercx_cfg016_s cn52xxp1;
struct cvmx_pciercx_cfg016_s cn56xx;
struct cvmx_pciercx_cfg016_s cn56xxp1;
+ struct cvmx_pciercx_cfg016_s cn61xx;
struct cvmx_pciercx_cfg016_s cn63xx;
struct cvmx_pciercx_cfg016_s cn63xxp1;
+ struct cvmx_pciercx_cfg016_s cn66xx;
+ struct cvmx_pciercx_cfg016_s cn68xx;
+ struct cvmx_pciercx_cfg016_s cn68xxp1;
};
union cvmx_pciercx_cfg017 {
@@ -430,14 +498,19 @@ union cvmx_pciercx_cfg017 {
struct cvmx_pciercx_cfg017_s cn52xxp1;
struct cvmx_pciercx_cfg017_s cn56xx;
struct cvmx_pciercx_cfg017_s cn56xxp1;
+ struct cvmx_pciercx_cfg017_s cn61xx;
struct cvmx_pciercx_cfg017_s cn63xx;
struct cvmx_pciercx_cfg017_s cn63xxp1;
+ struct cvmx_pciercx_cfg017_s cn66xx;
+ struct cvmx_pciercx_cfg017_s cn68xx;
+ struct cvmx_pciercx_cfg017_s cn68xxp1;
};
union cvmx_pciercx_cfg020 {
uint32_t u32;
struct cvmx_pciercx_cfg020_s {
- uint32_t reserved_24_31:8;
+ uint32_t reserved_25_31:7;
+ uint32_t pvm:1;
uint32_t m64:1;
uint32_t mme:3;
uint32_t mmc:3;
@@ -445,12 +518,24 @@ union cvmx_pciercx_cfg020 {
uint32_t ncp:8;
uint32_t msicid:8;
} s;
- struct cvmx_pciercx_cfg020_s cn52xx;
- struct cvmx_pciercx_cfg020_s cn52xxp1;
- struct cvmx_pciercx_cfg020_s cn56xx;
- struct cvmx_pciercx_cfg020_s cn56xxp1;
- struct cvmx_pciercx_cfg020_s cn63xx;
- struct cvmx_pciercx_cfg020_s cn63xxp1;
+ struct cvmx_pciercx_cfg020_cn52xx {
+ uint32_t reserved_24_31:8;
+ uint32_t m64:1;
+ uint32_t mme:3;
+ uint32_t mmc:3;
+ uint32_t msien:1;
+ uint32_t ncp:8;
+ uint32_t msicid:8;
+ } cn52xx;
+ struct cvmx_pciercx_cfg020_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg020_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg020_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg020_s cn61xx;
+ struct cvmx_pciercx_cfg020_cn52xx cn63xx;
+ struct cvmx_pciercx_cfg020_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg020_cn52xx cn66xx;
+ struct cvmx_pciercx_cfg020_cn52xx cn68xx;
+ struct cvmx_pciercx_cfg020_cn52xx cn68xxp1;
};
union cvmx_pciercx_cfg021 {
@@ -463,8 +548,12 @@ union cvmx_pciercx_cfg021 {
struct cvmx_pciercx_cfg021_s cn52xxp1;
struct cvmx_pciercx_cfg021_s cn56xx;
struct cvmx_pciercx_cfg021_s cn56xxp1;
+ struct cvmx_pciercx_cfg021_s cn61xx;
struct cvmx_pciercx_cfg021_s cn63xx;
struct cvmx_pciercx_cfg021_s cn63xxp1;
+ struct cvmx_pciercx_cfg021_s cn66xx;
+ struct cvmx_pciercx_cfg021_s cn68xx;
+ struct cvmx_pciercx_cfg021_s cn68xxp1;
};
union cvmx_pciercx_cfg022 {
@@ -476,8 +565,12 @@ union cvmx_pciercx_cfg022 {
struct cvmx_pciercx_cfg022_s cn52xxp1;
struct cvmx_pciercx_cfg022_s cn56xx;
struct cvmx_pciercx_cfg022_s cn56xxp1;
+ struct cvmx_pciercx_cfg022_s cn61xx;
struct cvmx_pciercx_cfg022_s cn63xx;
struct cvmx_pciercx_cfg022_s cn63xxp1;
+ struct cvmx_pciercx_cfg022_s cn66xx;
+ struct cvmx_pciercx_cfg022_s cn68xx;
+ struct cvmx_pciercx_cfg022_s cn68xxp1;
};
union cvmx_pciercx_cfg023 {
@@ -490,8 +583,12 @@ union cvmx_pciercx_cfg023 {
struct cvmx_pciercx_cfg023_s cn52xxp1;
struct cvmx_pciercx_cfg023_s cn56xx;
struct cvmx_pciercx_cfg023_s cn56xxp1;
+ struct cvmx_pciercx_cfg023_s cn61xx;
struct cvmx_pciercx_cfg023_s cn63xx;
struct cvmx_pciercx_cfg023_s cn63xxp1;
+ struct cvmx_pciercx_cfg023_s cn66xx;
+ struct cvmx_pciercx_cfg023_s cn68xx;
+ struct cvmx_pciercx_cfg023_s cn68xxp1;
};
union cvmx_pciercx_cfg028 {
@@ -509,8 +606,12 @@ union cvmx_pciercx_cfg028 {
struct cvmx_pciercx_cfg028_s cn52xxp1;
struct cvmx_pciercx_cfg028_s cn56xx;
struct cvmx_pciercx_cfg028_s cn56xxp1;
+ struct cvmx_pciercx_cfg028_s cn61xx;
struct cvmx_pciercx_cfg028_s cn63xx;
struct cvmx_pciercx_cfg028_s cn63xxp1;
+ struct cvmx_pciercx_cfg028_s cn66xx;
+ struct cvmx_pciercx_cfg028_s cn68xx;
+ struct cvmx_pciercx_cfg028_s cn68xxp1;
};
union cvmx_pciercx_cfg029 {
@@ -532,8 +633,12 @@ union cvmx_pciercx_cfg029 {
struct cvmx_pciercx_cfg029_s cn52xxp1;
struct cvmx_pciercx_cfg029_s cn56xx;
struct cvmx_pciercx_cfg029_s cn56xxp1;
+ struct cvmx_pciercx_cfg029_s cn61xx;
struct cvmx_pciercx_cfg029_s cn63xx;
struct cvmx_pciercx_cfg029_s cn63xxp1;
+ struct cvmx_pciercx_cfg029_s cn66xx;
+ struct cvmx_pciercx_cfg029_s cn68xx;
+ struct cvmx_pciercx_cfg029_s cn68xxp1;
};
union cvmx_pciercx_cfg030 {
@@ -563,15 +668,20 @@ union cvmx_pciercx_cfg030 {
struct cvmx_pciercx_cfg030_s cn52xxp1;
struct cvmx_pciercx_cfg030_s cn56xx;
struct cvmx_pciercx_cfg030_s cn56xxp1;
+ struct cvmx_pciercx_cfg030_s cn61xx;
struct cvmx_pciercx_cfg030_s cn63xx;
struct cvmx_pciercx_cfg030_s cn63xxp1;
+ struct cvmx_pciercx_cfg030_s cn66xx;
+ struct cvmx_pciercx_cfg030_s cn68xx;
+ struct cvmx_pciercx_cfg030_s cn68xxp1;
};
union cvmx_pciercx_cfg031 {
uint32_t u32;
struct cvmx_pciercx_cfg031_s {
uint32_t pnum:8;
- uint32_t reserved_22_23:2;
+ uint32_t reserved_23_23:1;
+ uint32_t aspm:1;
uint32_t lbnc:1;
uint32_t dllarc:1;
uint32_t sderc:1;
@@ -582,12 +692,28 @@ union cvmx_pciercx_cfg031 {
uint32_t mlw:6;
uint32_t mls:4;
} s;
- struct cvmx_pciercx_cfg031_s cn52xx;
- struct cvmx_pciercx_cfg031_s cn52xxp1;
- struct cvmx_pciercx_cfg031_s cn56xx;
- struct cvmx_pciercx_cfg031_s cn56xxp1;
- struct cvmx_pciercx_cfg031_s cn63xx;
- struct cvmx_pciercx_cfg031_s cn63xxp1;
+ struct cvmx_pciercx_cfg031_cn52xx {
+ uint32_t pnum:8;
+ uint32_t reserved_22_23:2;
+ uint32_t lbnc:1;
+ uint32_t dllarc:1;
+ uint32_t sderc:1;
+ uint32_t cpm:1;
+ uint32_t l1el:3;
+ uint32_t l0el:3;
+ uint32_t aslpms:2;
+ uint32_t mlw:6;
+ uint32_t mls:4;
+ } cn52xx;
+ struct cvmx_pciercx_cfg031_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg031_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg031_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg031_s cn61xx;
+ struct cvmx_pciercx_cfg031_cn52xx cn63xx;
+ struct cvmx_pciercx_cfg031_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg031_s cn66xx;
+ struct cvmx_pciercx_cfg031_s cn68xx;
+ struct cvmx_pciercx_cfg031_cn52xx cn68xxp1;
};
union cvmx_pciercx_cfg032 {
@@ -618,8 +744,12 @@ union cvmx_pciercx_cfg032 {
struct cvmx_pciercx_cfg032_s cn52xxp1;
struct cvmx_pciercx_cfg032_s cn56xx;
struct cvmx_pciercx_cfg032_s cn56xxp1;
+ struct cvmx_pciercx_cfg032_s cn61xx;
struct cvmx_pciercx_cfg032_s cn63xx;
struct cvmx_pciercx_cfg032_s cn63xxp1;
+ struct cvmx_pciercx_cfg032_s cn66xx;
+ struct cvmx_pciercx_cfg032_s cn68xx;
+ struct cvmx_pciercx_cfg032_s cn68xxp1;
};
union cvmx_pciercx_cfg033 {
@@ -642,8 +772,12 @@ union cvmx_pciercx_cfg033 {
struct cvmx_pciercx_cfg033_s cn52xxp1;
struct cvmx_pciercx_cfg033_s cn56xx;
struct cvmx_pciercx_cfg033_s cn56xxp1;
+ struct cvmx_pciercx_cfg033_s cn61xx;
struct cvmx_pciercx_cfg033_s cn63xx;
struct cvmx_pciercx_cfg033_s cn63xxp1;
+ struct cvmx_pciercx_cfg033_s cn66xx;
+ struct cvmx_pciercx_cfg033_s cn68xx;
+ struct cvmx_pciercx_cfg033_s cn68xxp1;
};
union cvmx_pciercx_cfg034 {
@@ -676,8 +810,12 @@ union cvmx_pciercx_cfg034 {
struct cvmx_pciercx_cfg034_s cn52xxp1;
struct cvmx_pciercx_cfg034_s cn56xx;
struct cvmx_pciercx_cfg034_s cn56xxp1;
+ struct cvmx_pciercx_cfg034_s cn61xx;
struct cvmx_pciercx_cfg034_s cn63xx;
struct cvmx_pciercx_cfg034_s cn63xxp1;
+ struct cvmx_pciercx_cfg034_s cn66xx;
+ struct cvmx_pciercx_cfg034_s cn68xx;
+ struct cvmx_pciercx_cfg034_s cn68xxp1;
};
union cvmx_pciercx_cfg035 {
@@ -696,8 +834,12 @@ union cvmx_pciercx_cfg035 {
struct cvmx_pciercx_cfg035_s cn52xxp1;
struct cvmx_pciercx_cfg035_s cn56xx;
struct cvmx_pciercx_cfg035_s cn56xxp1;
+ struct cvmx_pciercx_cfg035_s cn61xx;
struct cvmx_pciercx_cfg035_s cn63xx;
struct cvmx_pciercx_cfg035_s cn63xxp1;
+ struct cvmx_pciercx_cfg035_s cn66xx;
+ struct cvmx_pciercx_cfg035_s cn68xx;
+ struct cvmx_pciercx_cfg035_s cn68xxp1;
};
union cvmx_pciercx_cfg036 {
@@ -712,38 +854,95 @@ union cvmx_pciercx_cfg036 {
struct cvmx_pciercx_cfg036_s cn52xxp1;
struct cvmx_pciercx_cfg036_s cn56xx;
struct cvmx_pciercx_cfg036_s cn56xxp1;
+ struct cvmx_pciercx_cfg036_s cn61xx;
struct cvmx_pciercx_cfg036_s cn63xx;
struct cvmx_pciercx_cfg036_s cn63xxp1;
+ struct cvmx_pciercx_cfg036_s cn66xx;
+ struct cvmx_pciercx_cfg036_s cn68xx;
+ struct cvmx_pciercx_cfg036_s cn68xxp1;
};
union cvmx_pciercx_cfg037 {
uint32_t u32;
struct cvmx_pciercx_cfg037_s {
- uint32_t reserved_5_31:27;
+ uint32_t reserved_14_31:18;
+ uint32_t tph:2;
+ uint32_t reserved_11_11:1;
+ uint32_t noroprpr:1;
+ uint32_t atom128s:1;
+ uint32_t atom64s:1;
+ uint32_t atom32s:1;
+ uint32_t atom_ops:1;
+ uint32_t reserved_5_5:1;
uint32_t ctds:1;
uint32_t ctrs:4;
} s;
- struct cvmx_pciercx_cfg037_s cn52xx;
- struct cvmx_pciercx_cfg037_s cn52xxp1;
- struct cvmx_pciercx_cfg037_s cn56xx;
- struct cvmx_pciercx_cfg037_s cn56xxp1;
- struct cvmx_pciercx_cfg037_s cn63xx;
- struct cvmx_pciercx_cfg037_s cn63xxp1;
+ struct cvmx_pciercx_cfg037_cn52xx {
+ uint32_t reserved_5_31:27;
+ uint32_t ctds:1;
+ uint32_t ctrs:4;
+ } cn52xx;
+ struct cvmx_pciercx_cfg037_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg037_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg037_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg037_cn61xx {
+ uint32_t reserved_14_31:18;
+ uint32_t tph:2;
+ uint32_t reserved_11_11:1;
+ uint32_t noroprpr:1;
+ uint32_t atom128s:1;
+ uint32_t atom64s:1;
+ uint32_t atom32s:1;
+ uint32_t atom_ops:1;
+ uint32_t ari_fw:1;
+ uint32_t ctds:1;
+ uint32_t ctrs:4;
+ } cn61xx;
+ struct cvmx_pciercx_cfg037_cn52xx cn63xx;
+ struct cvmx_pciercx_cfg037_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg037_cn66xx {
+ uint32_t reserved_14_31:18;
+ uint32_t tph:2;
+ uint32_t reserved_11_11:1;
+ uint32_t noroprpr:1;
+ uint32_t atom128s:1;
+ uint32_t atom64s:1;
+ uint32_t atom32s:1;
+ uint32_t atom_ops:1;
+ uint32_t ari:1;
+ uint32_t ctds:1;
+ uint32_t ctrs:4;
+ } cn66xx;
+ struct cvmx_pciercx_cfg037_cn66xx cn68xx;
+ struct cvmx_pciercx_cfg037_cn66xx cn68xxp1;
};
union cvmx_pciercx_cfg038 {
uint32_t u32;
struct cvmx_pciercx_cfg038_s {
- uint32_t reserved_5_31:27;
+ uint32_t reserved_10_31:22;
+ uint32_t id0_cp:1;
+ uint32_t id0_rq:1;
+ uint32_t atom_op_eb:1;
+ uint32_t atom_op:1;
+ uint32_t ari:1;
uint32_t ctd:1;
uint32_t ctv:4;
} s;
- struct cvmx_pciercx_cfg038_s cn52xx;
- struct cvmx_pciercx_cfg038_s cn52xxp1;
- struct cvmx_pciercx_cfg038_s cn56xx;
- struct cvmx_pciercx_cfg038_s cn56xxp1;
- struct cvmx_pciercx_cfg038_s cn63xx;
- struct cvmx_pciercx_cfg038_s cn63xxp1;
+ struct cvmx_pciercx_cfg038_cn52xx {
+ uint32_t reserved_5_31:27;
+ uint32_t ctd:1;
+ uint32_t ctv:4;
+ } cn52xx;
+ struct cvmx_pciercx_cfg038_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg038_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg038_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg038_s cn61xx;
+ struct cvmx_pciercx_cfg038_cn52xx cn63xx;
+ struct cvmx_pciercx_cfg038_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg038_s cn66xx;
+ struct cvmx_pciercx_cfg038_s cn68xx;
+ struct cvmx_pciercx_cfg038_s cn68xxp1;
};
union cvmx_pciercx_cfg039 {
@@ -760,8 +959,12 @@ union cvmx_pciercx_cfg039 {
struct cvmx_pciercx_cfg039_cn52xx cn52xxp1;
struct cvmx_pciercx_cfg039_cn52xx cn56xx;
struct cvmx_pciercx_cfg039_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg039_s cn61xx;
struct cvmx_pciercx_cfg039_s cn63xx;
struct cvmx_pciercx_cfg039_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg039_s cn66xx;
+ struct cvmx_pciercx_cfg039_s cn68xx;
+ struct cvmx_pciercx_cfg039_s cn68xxp1;
};
union cvmx_pciercx_cfg040 {
@@ -785,8 +988,12 @@ union cvmx_pciercx_cfg040 {
struct cvmx_pciercx_cfg040_cn52xx cn52xxp1;
struct cvmx_pciercx_cfg040_cn52xx cn56xx;
struct cvmx_pciercx_cfg040_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg040_s cn61xx;
struct cvmx_pciercx_cfg040_s cn63xx;
struct cvmx_pciercx_cfg040_s cn63xxp1;
+ struct cvmx_pciercx_cfg040_s cn66xx;
+ struct cvmx_pciercx_cfg040_s cn68xx;
+ struct cvmx_pciercx_cfg040_s cn68xxp1;
};
union cvmx_pciercx_cfg041 {
@@ -798,8 +1005,12 @@ union cvmx_pciercx_cfg041 {
struct cvmx_pciercx_cfg041_s cn52xxp1;
struct cvmx_pciercx_cfg041_s cn56xx;
struct cvmx_pciercx_cfg041_s cn56xxp1;
+ struct cvmx_pciercx_cfg041_s cn61xx;
struct cvmx_pciercx_cfg041_s cn63xx;
struct cvmx_pciercx_cfg041_s cn63xxp1;
+ struct cvmx_pciercx_cfg041_s cn66xx;
+ struct cvmx_pciercx_cfg041_s cn68xx;
+ struct cvmx_pciercx_cfg041_s cn68xxp1;
};
union cvmx_pciercx_cfg042 {
@@ -811,8 +1022,12 @@ union cvmx_pciercx_cfg042 {
struct cvmx_pciercx_cfg042_s cn52xxp1;
struct cvmx_pciercx_cfg042_s cn56xx;
struct cvmx_pciercx_cfg042_s cn56xxp1;
+ struct cvmx_pciercx_cfg042_s cn61xx;
struct cvmx_pciercx_cfg042_s cn63xx;
struct cvmx_pciercx_cfg042_s cn63xxp1;
+ struct cvmx_pciercx_cfg042_s cn66xx;
+ struct cvmx_pciercx_cfg042_s cn68xx;
+ struct cvmx_pciercx_cfg042_s cn68xxp1;
};
union cvmx_pciercx_cfg064 {
@@ -826,14 +1041,20 @@ union cvmx_pciercx_cfg064 {
struct cvmx_pciercx_cfg064_s cn52xxp1;
struct cvmx_pciercx_cfg064_s cn56xx;
struct cvmx_pciercx_cfg064_s cn56xxp1;
+ struct cvmx_pciercx_cfg064_s cn61xx;
struct cvmx_pciercx_cfg064_s cn63xx;
struct cvmx_pciercx_cfg064_s cn63xxp1;
+ struct cvmx_pciercx_cfg064_s cn66xx;
+ struct cvmx_pciercx_cfg064_s cn68xx;
+ struct cvmx_pciercx_cfg064_s cn68xxp1;
};
union cvmx_pciercx_cfg065 {
uint32_t u32;
struct cvmx_pciercx_cfg065_s {
- uint32_t reserved_21_31:11;
+ uint32_t reserved_25_31:7;
+ uint32_t uatombs:1;
+ uint32_t reserved_21_23:3;
uint32_t ures:1;
uint32_t ecrces:1;
uint32_t mtlps:1;
@@ -848,18 +1069,39 @@ union cvmx_pciercx_cfg065 {
uint32_t dlpes:1;
uint32_t reserved_0_3:4;
} s;
- struct cvmx_pciercx_cfg065_s cn52xx;
- struct cvmx_pciercx_cfg065_s cn52xxp1;
- struct cvmx_pciercx_cfg065_s cn56xx;
- struct cvmx_pciercx_cfg065_s cn56xxp1;
- struct cvmx_pciercx_cfg065_s cn63xx;
- struct cvmx_pciercx_cfg065_s cn63xxp1;
+ struct cvmx_pciercx_cfg065_cn52xx {
+ uint32_t reserved_21_31:11;
+ uint32_t ures:1;
+ uint32_t ecrces:1;
+ uint32_t mtlps:1;
+ uint32_t ros:1;
+ uint32_t ucs:1;
+ uint32_t cas:1;
+ uint32_t cts:1;
+ uint32_t fcpes:1;
+ uint32_t ptlps:1;
+ uint32_t reserved_6_11:6;
+ uint32_t sdes:1;
+ uint32_t dlpes:1;
+ uint32_t reserved_0_3:4;
+ } cn52xx;
+ struct cvmx_pciercx_cfg065_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg065_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg065_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg065_s cn61xx;
+ struct cvmx_pciercx_cfg065_cn52xx cn63xx;
+ struct cvmx_pciercx_cfg065_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg065_s cn66xx;
+ struct cvmx_pciercx_cfg065_s cn68xx;
+ struct cvmx_pciercx_cfg065_cn52xx cn68xxp1;
};
union cvmx_pciercx_cfg066 {
uint32_t u32;
struct cvmx_pciercx_cfg066_s {
- uint32_t reserved_21_31:11;
+ uint32_t reserved_25_31:7;
+ uint32_t uatombm:1;
+ uint32_t reserved_21_23:3;
uint32_t urem:1;
uint32_t ecrcem:1;
uint32_t mtlpm:1;
@@ -874,18 +1116,39 @@ union cvmx_pciercx_cfg066 {
uint32_t dlpem:1;
uint32_t reserved_0_3:4;
} s;
- struct cvmx_pciercx_cfg066_s cn52xx;
- struct cvmx_pciercx_cfg066_s cn52xxp1;
- struct cvmx_pciercx_cfg066_s cn56xx;
- struct cvmx_pciercx_cfg066_s cn56xxp1;
- struct cvmx_pciercx_cfg066_s cn63xx;
- struct cvmx_pciercx_cfg066_s cn63xxp1;
+ struct cvmx_pciercx_cfg066_cn52xx {
+ uint32_t reserved_21_31:11;
+ uint32_t urem:1;
+ uint32_t ecrcem:1;
+ uint32_t mtlpm:1;
+ uint32_t rom:1;
+ uint32_t ucm:1;
+ uint32_t cam:1;
+ uint32_t ctm:1;
+ uint32_t fcpem:1;
+ uint32_t ptlpm:1;
+ uint32_t reserved_6_11:6;
+ uint32_t sdem:1;
+ uint32_t dlpem:1;
+ uint32_t reserved_0_3:4;
+ } cn52xx;
+ struct cvmx_pciercx_cfg066_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg066_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg066_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg066_s cn61xx;
+ struct cvmx_pciercx_cfg066_cn52xx cn63xx;
+ struct cvmx_pciercx_cfg066_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg066_s cn66xx;
+ struct cvmx_pciercx_cfg066_s cn68xx;
+ struct cvmx_pciercx_cfg066_cn52xx cn68xxp1;
};
union cvmx_pciercx_cfg067 {
uint32_t u32;
struct cvmx_pciercx_cfg067_s {
- uint32_t reserved_21_31:11;
+ uint32_t reserved_25_31:7;
+ uint32_t uatombs:1;
+ uint32_t reserved_21_23:3;
uint32_t ures:1;
uint32_t ecrces:1;
uint32_t mtlps:1;
@@ -900,12 +1163,31 @@ union cvmx_pciercx_cfg067 {
uint32_t dlpes:1;
uint32_t reserved_0_3:4;
} s;
- struct cvmx_pciercx_cfg067_s cn52xx;
- struct cvmx_pciercx_cfg067_s cn52xxp1;
- struct cvmx_pciercx_cfg067_s cn56xx;
- struct cvmx_pciercx_cfg067_s cn56xxp1;
- struct cvmx_pciercx_cfg067_s cn63xx;
- struct cvmx_pciercx_cfg067_s cn63xxp1;
+ struct cvmx_pciercx_cfg067_cn52xx {
+ uint32_t reserved_21_31:11;
+ uint32_t ures:1;
+ uint32_t ecrces:1;
+ uint32_t mtlps:1;
+ uint32_t ros:1;
+ uint32_t ucs:1;
+ uint32_t cas:1;
+ uint32_t cts:1;
+ uint32_t fcpes:1;
+ uint32_t ptlps:1;
+ uint32_t reserved_6_11:6;
+ uint32_t sdes:1;
+ uint32_t dlpes:1;
+ uint32_t reserved_0_3:4;
+ } cn52xx;
+ struct cvmx_pciercx_cfg067_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg067_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg067_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg067_s cn61xx;
+ struct cvmx_pciercx_cfg067_cn52xx cn63xx;
+ struct cvmx_pciercx_cfg067_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg067_s cn66xx;
+ struct cvmx_pciercx_cfg067_s cn68xx;
+ struct cvmx_pciercx_cfg067_cn52xx cn68xxp1;
};
union cvmx_pciercx_cfg068 {
@@ -925,8 +1207,12 @@ union cvmx_pciercx_cfg068 {
struct cvmx_pciercx_cfg068_s cn52xxp1;
struct cvmx_pciercx_cfg068_s cn56xx;
struct cvmx_pciercx_cfg068_s cn56xxp1;
+ struct cvmx_pciercx_cfg068_s cn61xx;
struct cvmx_pciercx_cfg068_s cn63xx;
struct cvmx_pciercx_cfg068_s cn63xxp1;
+ struct cvmx_pciercx_cfg068_s cn66xx;
+ struct cvmx_pciercx_cfg068_s cn68xx;
+ struct cvmx_pciercx_cfg068_s cn68xxp1;
};
union cvmx_pciercx_cfg069 {
@@ -946,8 +1232,12 @@ union cvmx_pciercx_cfg069 {
struct cvmx_pciercx_cfg069_s cn52xxp1;
struct cvmx_pciercx_cfg069_s cn56xx;
struct cvmx_pciercx_cfg069_s cn56xxp1;
+ struct cvmx_pciercx_cfg069_s cn61xx;
struct cvmx_pciercx_cfg069_s cn63xx;
struct cvmx_pciercx_cfg069_s cn63xxp1;
+ struct cvmx_pciercx_cfg069_s cn66xx;
+ struct cvmx_pciercx_cfg069_s cn68xx;
+ struct cvmx_pciercx_cfg069_s cn68xxp1;
};
union cvmx_pciercx_cfg070 {
@@ -964,8 +1254,12 @@ union cvmx_pciercx_cfg070 {
struct cvmx_pciercx_cfg070_s cn52xxp1;
struct cvmx_pciercx_cfg070_s cn56xx;
struct cvmx_pciercx_cfg070_s cn56xxp1;
+ struct cvmx_pciercx_cfg070_s cn61xx;
struct cvmx_pciercx_cfg070_s cn63xx;
struct cvmx_pciercx_cfg070_s cn63xxp1;
+ struct cvmx_pciercx_cfg070_s cn66xx;
+ struct cvmx_pciercx_cfg070_s cn68xx;
+ struct cvmx_pciercx_cfg070_s cn68xxp1;
};
union cvmx_pciercx_cfg071 {
@@ -977,8 +1271,12 @@ union cvmx_pciercx_cfg071 {
struct cvmx_pciercx_cfg071_s cn52xxp1;
struct cvmx_pciercx_cfg071_s cn56xx;
struct cvmx_pciercx_cfg071_s cn56xxp1;
+ struct cvmx_pciercx_cfg071_s cn61xx;
struct cvmx_pciercx_cfg071_s cn63xx;
struct cvmx_pciercx_cfg071_s cn63xxp1;
+ struct cvmx_pciercx_cfg071_s cn66xx;
+ struct cvmx_pciercx_cfg071_s cn68xx;
+ struct cvmx_pciercx_cfg071_s cn68xxp1;
};
union cvmx_pciercx_cfg072 {
@@ -990,8 +1288,12 @@ union cvmx_pciercx_cfg072 {
struct cvmx_pciercx_cfg072_s cn52xxp1;
struct cvmx_pciercx_cfg072_s cn56xx;
struct cvmx_pciercx_cfg072_s cn56xxp1;
+ struct cvmx_pciercx_cfg072_s cn61xx;
struct cvmx_pciercx_cfg072_s cn63xx;
struct cvmx_pciercx_cfg072_s cn63xxp1;
+ struct cvmx_pciercx_cfg072_s cn66xx;
+ struct cvmx_pciercx_cfg072_s cn68xx;
+ struct cvmx_pciercx_cfg072_s cn68xxp1;
};
union cvmx_pciercx_cfg073 {
@@ -1003,8 +1305,12 @@ union cvmx_pciercx_cfg073 {
struct cvmx_pciercx_cfg073_s cn52xxp1;
struct cvmx_pciercx_cfg073_s cn56xx;
struct cvmx_pciercx_cfg073_s cn56xxp1;
+ struct cvmx_pciercx_cfg073_s cn61xx;
struct cvmx_pciercx_cfg073_s cn63xx;
struct cvmx_pciercx_cfg073_s cn63xxp1;
+ struct cvmx_pciercx_cfg073_s cn66xx;
+ struct cvmx_pciercx_cfg073_s cn68xx;
+ struct cvmx_pciercx_cfg073_s cn68xxp1;
};
union cvmx_pciercx_cfg074 {
@@ -1016,8 +1322,12 @@ union cvmx_pciercx_cfg074 {
struct cvmx_pciercx_cfg074_s cn52xxp1;
struct cvmx_pciercx_cfg074_s cn56xx;
struct cvmx_pciercx_cfg074_s cn56xxp1;
+ struct cvmx_pciercx_cfg074_s cn61xx;
struct cvmx_pciercx_cfg074_s cn63xx;
struct cvmx_pciercx_cfg074_s cn63xxp1;
+ struct cvmx_pciercx_cfg074_s cn66xx;
+ struct cvmx_pciercx_cfg074_s cn68xx;
+ struct cvmx_pciercx_cfg074_s cn68xxp1;
};
union cvmx_pciercx_cfg075 {
@@ -1032,8 +1342,12 @@ union cvmx_pciercx_cfg075 {
struct cvmx_pciercx_cfg075_s cn52xxp1;
struct cvmx_pciercx_cfg075_s cn56xx;
struct cvmx_pciercx_cfg075_s cn56xxp1;
+ struct cvmx_pciercx_cfg075_s cn61xx;
struct cvmx_pciercx_cfg075_s cn63xx;
struct cvmx_pciercx_cfg075_s cn63xxp1;
+ struct cvmx_pciercx_cfg075_s cn66xx;
+ struct cvmx_pciercx_cfg075_s cn68xx;
+ struct cvmx_pciercx_cfg075_s cn68xxp1;
};
union cvmx_pciercx_cfg076 {
@@ -1053,8 +1367,12 @@ union cvmx_pciercx_cfg076 {
struct cvmx_pciercx_cfg076_s cn52xxp1;
struct cvmx_pciercx_cfg076_s cn56xx;
struct cvmx_pciercx_cfg076_s cn56xxp1;
+ struct cvmx_pciercx_cfg076_s cn61xx;
struct cvmx_pciercx_cfg076_s cn63xx;
struct cvmx_pciercx_cfg076_s cn63xxp1;
+ struct cvmx_pciercx_cfg076_s cn66xx;
+ struct cvmx_pciercx_cfg076_s cn68xx;
+ struct cvmx_pciercx_cfg076_s cn68xxp1;
};
union cvmx_pciercx_cfg077 {
@@ -1067,8 +1385,12 @@ union cvmx_pciercx_cfg077 {
struct cvmx_pciercx_cfg077_s cn52xxp1;
struct cvmx_pciercx_cfg077_s cn56xx;
struct cvmx_pciercx_cfg077_s cn56xxp1;
+ struct cvmx_pciercx_cfg077_s cn61xx;
struct cvmx_pciercx_cfg077_s cn63xx;
struct cvmx_pciercx_cfg077_s cn63xxp1;
+ struct cvmx_pciercx_cfg077_s cn66xx;
+ struct cvmx_pciercx_cfg077_s cn68xx;
+ struct cvmx_pciercx_cfg077_s cn68xxp1;
};
union cvmx_pciercx_cfg448 {
@@ -1081,8 +1403,12 @@ union cvmx_pciercx_cfg448 {
struct cvmx_pciercx_cfg448_s cn52xxp1;
struct cvmx_pciercx_cfg448_s cn56xx;
struct cvmx_pciercx_cfg448_s cn56xxp1;
+ struct cvmx_pciercx_cfg448_s cn61xx;
struct cvmx_pciercx_cfg448_s cn63xx;
struct cvmx_pciercx_cfg448_s cn63xxp1;
+ struct cvmx_pciercx_cfg448_s cn66xx;
+ struct cvmx_pciercx_cfg448_s cn68xx;
+ struct cvmx_pciercx_cfg448_s cn68xxp1;
};
union cvmx_pciercx_cfg449 {
@@ -1094,8 +1420,12 @@ union cvmx_pciercx_cfg449 {
struct cvmx_pciercx_cfg449_s cn52xxp1;
struct cvmx_pciercx_cfg449_s cn56xx;
struct cvmx_pciercx_cfg449_s cn56xxp1;
+ struct cvmx_pciercx_cfg449_s cn61xx;
struct cvmx_pciercx_cfg449_s cn63xx;
struct cvmx_pciercx_cfg449_s cn63xxp1;
+ struct cvmx_pciercx_cfg449_s cn66xx;
+ struct cvmx_pciercx_cfg449_s cn68xx;
+ struct cvmx_pciercx_cfg449_s cn68xxp1;
};
union cvmx_pciercx_cfg450 {
@@ -1112,26 +1442,42 @@ union cvmx_pciercx_cfg450 {
struct cvmx_pciercx_cfg450_s cn52xxp1;
struct cvmx_pciercx_cfg450_s cn56xx;
struct cvmx_pciercx_cfg450_s cn56xxp1;
+ struct cvmx_pciercx_cfg450_s cn61xx;
struct cvmx_pciercx_cfg450_s cn63xx;
struct cvmx_pciercx_cfg450_s cn63xxp1;
+ struct cvmx_pciercx_cfg450_s cn66xx;
+ struct cvmx_pciercx_cfg450_s cn68xx;
+ struct cvmx_pciercx_cfg450_s cn68xxp1;
};
union cvmx_pciercx_cfg451 {
uint32_t u32;
struct cvmx_pciercx_cfg451_s {
- uint32_t reserved_30_31:2;
+ uint32_t reserved_31_31:1;
+ uint32_t easpml1:1;
uint32_t l1el:3;
uint32_t l0el:3;
uint32_t n_fts_cc:8;
uint32_t n_fts:8;
uint32_t ack_freq:8;
} s;
- struct cvmx_pciercx_cfg451_s cn52xx;
- struct cvmx_pciercx_cfg451_s cn52xxp1;
- struct cvmx_pciercx_cfg451_s cn56xx;
- struct cvmx_pciercx_cfg451_s cn56xxp1;
- struct cvmx_pciercx_cfg451_s cn63xx;
- struct cvmx_pciercx_cfg451_s cn63xxp1;
+ struct cvmx_pciercx_cfg451_cn52xx {
+ uint32_t reserved_30_31:2;
+ uint32_t l1el:3;
+ uint32_t l0el:3;
+ uint32_t n_fts_cc:8;
+ uint32_t n_fts:8;
+ uint32_t ack_freq:8;
+ } cn52xx;
+ struct cvmx_pciercx_cfg451_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg451_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg451_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg451_s cn61xx;
+ struct cvmx_pciercx_cfg451_cn52xx cn63xx;
+ struct cvmx_pciercx_cfg451_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg451_s cn66xx;
+ struct cvmx_pciercx_cfg451_s cn68xx;
+ struct cvmx_pciercx_cfg451_s cn68xxp1;
};
union cvmx_pciercx_cfg452 {
@@ -1155,8 +1501,24 @@ union cvmx_pciercx_cfg452 {
struct cvmx_pciercx_cfg452_s cn52xxp1;
struct cvmx_pciercx_cfg452_s cn56xx;
struct cvmx_pciercx_cfg452_s cn56xxp1;
+ struct cvmx_pciercx_cfg452_cn61xx {
+ uint32_t reserved_22_31:10;
+ uint32_t lme:6;
+ uint32_t reserved_8_15:8;
+ uint32_t flm:1;
+ uint32_t reserved_6_6:1;
+ uint32_t dllle:1;
+ uint32_t reserved_4_4:1;
+ uint32_t ra:1;
+ uint32_t le:1;
+ uint32_t sd:1;
+ uint32_t omr:1;
+ } cn61xx;
struct cvmx_pciercx_cfg452_s cn63xx;
struct cvmx_pciercx_cfg452_s cn63xxp1;
+ struct cvmx_pciercx_cfg452_cn61xx cn66xx;
+ struct cvmx_pciercx_cfg452_cn61xx cn68xx;
+ struct cvmx_pciercx_cfg452_cn61xx cn68xxp1;
};
union cvmx_pciercx_cfg453 {
@@ -1172,13 +1534,26 @@ union cvmx_pciercx_cfg453 {
struct cvmx_pciercx_cfg453_s cn52xxp1;
struct cvmx_pciercx_cfg453_s cn56xx;
struct cvmx_pciercx_cfg453_s cn56xxp1;
+ struct cvmx_pciercx_cfg453_s cn61xx;
struct cvmx_pciercx_cfg453_s cn63xx;
struct cvmx_pciercx_cfg453_s cn63xxp1;
+ struct cvmx_pciercx_cfg453_s cn66xx;
+ struct cvmx_pciercx_cfg453_s cn68xx;
+ struct cvmx_pciercx_cfg453_s cn68xxp1;
};
union cvmx_pciercx_cfg454 {
uint32_t u32;
struct cvmx_pciercx_cfg454_s {
+ uint32_t cx_nfunc:3;
+ uint32_t tmfcwt:5;
+ uint32_t tmanlt:5;
+ uint32_t tmrt:5;
+ uint32_t reserved_11_13:3;
+ uint32_t nskps:3;
+ uint32_t reserved_0_7:8;
+ } s;
+ struct cvmx_pciercx_cfg454_cn52xx {
uint32_t reserved_29_31:3;
uint32_t tmfcwt:5;
uint32_t tmanlt:5;
@@ -1187,13 +1562,23 @@ union cvmx_pciercx_cfg454 {
uint32_t nskps:3;
uint32_t reserved_4_7:4;
uint32_t ntss:4;
- } s;
- struct cvmx_pciercx_cfg454_s cn52xx;
- struct cvmx_pciercx_cfg454_s cn52xxp1;
- struct cvmx_pciercx_cfg454_s cn56xx;
- struct cvmx_pciercx_cfg454_s cn56xxp1;
- struct cvmx_pciercx_cfg454_s cn63xx;
- struct cvmx_pciercx_cfg454_s cn63xxp1;
+ } cn52xx;
+ struct cvmx_pciercx_cfg454_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg454_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg454_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg454_cn61xx {
+ uint32_t cx_nfunc:3;
+ uint32_t tmfcwt:5;
+ uint32_t tmanlt:5;
+ uint32_t tmrt:5;
+ uint32_t reserved_8_13:6;
+ uint32_t mfuncn:8;
+ } cn61xx;
+ struct cvmx_pciercx_cfg454_cn52xx cn63xx;
+ struct cvmx_pciercx_cfg454_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg454_cn61xx cn66xx;
+ struct cvmx_pciercx_cfg454_cn61xx cn68xx;
+ struct cvmx_pciercx_cfg454_cn52xx cn68xxp1;
};
union cvmx_pciercx_cfg455 {
@@ -1223,23 +1608,37 @@ union cvmx_pciercx_cfg455 {
struct cvmx_pciercx_cfg455_s cn52xxp1;
struct cvmx_pciercx_cfg455_s cn56xx;
struct cvmx_pciercx_cfg455_s cn56xxp1;
+ struct cvmx_pciercx_cfg455_s cn61xx;
struct cvmx_pciercx_cfg455_s cn63xx;
struct cvmx_pciercx_cfg455_s cn63xxp1;
+ struct cvmx_pciercx_cfg455_s cn66xx;
+ struct cvmx_pciercx_cfg455_s cn68xx;
+ struct cvmx_pciercx_cfg455_s cn68xxp1;
};
union cvmx_pciercx_cfg456 {
uint32_t u32;
struct cvmx_pciercx_cfg456_s {
- uint32_t reserved_2_31:30;
+ uint32_t reserved_4_31:28;
+ uint32_t m_handle_flush:1;
+ uint32_t m_dabort_4ucpl:1;
uint32_t m_vend1_drp:1;
uint32_t m_vend0_drp:1;
} s;
- struct cvmx_pciercx_cfg456_s cn52xx;
- struct cvmx_pciercx_cfg456_s cn52xxp1;
- struct cvmx_pciercx_cfg456_s cn56xx;
- struct cvmx_pciercx_cfg456_s cn56xxp1;
- struct cvmx_pciercx_cfg456_s cn63xx;
- struct cvmx_pciercx_cfg456_s cn63xxp1;
+ struct cvmx_pciercx_cfg456_cn52xx {
+ uint32_t reserved_2_31:30;
+ uint32_t m_vend1_drp:1;
+ uint32_t m_vend0_drp:1;
+ } cn52xx;
+ struct cvmx_pciercx_cfg456_cn52xx cn52xxp1;
+ struct cvmx_pciercx_cfg456_cn52xx cn56xx;
+ struct cvmx_pciercx_cfg456_cn52xx cn56xxp1;
+ struct cvmx_pciercx_cfg456_s cn61xx;
+ struct cvmx_pciercx_cfg456_cn52xx cn63xx;
+ struct cvmx_pciercx_cfg456_cn52xx cn63xxp1;
+ struct cvmx_pciercx_cfg456_s cn66xx;
+ struct cvmx_pciercx_cfg456_s cn68xx;
+ struct cvmx_pciercx_cfg456_cn52xx cn68xxp1;
};
union cvmx_pciercx_cfg458 {
@@ -1251,8 +1650,12 @@ union cvmx_pciercx_cfg458 {
struct cvmx_pciercx_cfg458_s cn52xxp1;
struct cvmx_pciercx_cfg458_s cn56xx;
struct cvmx_pciercx_cfg458_s cn56xxp1;
+ struct cvmx_pciercx_cfg458_s cn61xx;
struct cvmx_pciercx_cfg458_s cn63xx;
struct cvmx_pciercx_cfg458_s cn63xxp1;
+ struct cvmx_pciercx_cfg458_s cn66xx;
+ struct cvmx_pciercx_cfg458_s cn68xx;
+ struct cvmx_pciercx_cfg458_s cn68xxp1;
};
union cvmx_pciercx_cfg459 {
@@ -1264,8 +1667,12 @@ union cvmx_pciercx_cfg459 {
struct cvmx_pciercx_cfg459_s cn52xxp1;
struct cvmx_pciercx_cfg459_s cn56xx;
struct cvmx_pciercx_cfg459_s cn56xxp1;
+ struct cvmx_pciercx_cfg459_s cn61xx;
struct cvmx_pciercx_cfg459_s cn63xx;
struct cvmx_pciercx_cfg459_s cn63xxp1;
+ struct cvmx_pciercx_cfg459_s cn66xx;
+ struct cvmx_pciercx_cfg459_s cn68xx;
+ struct cvmx_pciercx_cfg459_s cn68xxp1;
};
union cvmx_pciercx_cfg460 {
@@ -1279,8 +1686,12 @@ union cvmx_pciercx_cfg460 {
struct cvmx_pciercx_cfg460_s cn52xxp1;
struct cvmx_pciercx_cfg460_s cn56xx;
struct cvmx_pciercx_cfg460_s cn56xxp1;
+ struct cvmx_pciercx_cfg460_s cn61xx;
struct cvmx_pciercx_cfg460_s cn63xx;
struct cvmx_pciercx_cfg460_s cn63xxp1;
+ struct cvmx_pciercx_cfg460_s cn66xx;
+ struct cvmx_pciercx_cfg460_s cn68xx;
+ struct cvmx_pciercx_cfg460_s cn68xxp1;
};
union cvmx_pciercx_cfg461 {
@@ -1294,8 +1705,12 @@ union cvmx_pciercx_cfg461 {
struct cvmx_pciercx_cfg461_s cn52xxp1;
struct cvmx_pciercx_cfg461_s cn56xx;
struct cvmx_pciercx_cfg461_s cn56xxp1;
+ struct cvmx_pciercx_cfg461_s cn61xx;
struct cvmx_pciercx_cfg461_s cn63xx;
struct cvmx_pciercx_cfg461_s cn63xxp1;
+ struct cvmx_pciercx_cfg461_s cn66xx;
+ struct cvmx_pciercx_cfg461_s cn68xx;
+ struct cvmx_pciercx_cfg461_s cn68xxp1;
};
union cvmx_pciercx_cfg462 {
@@ -1309,8 +1724,12 @@ union cvmx_pciercx_cfg462 {
struct cvmx_pciercx_cfg462_s cn52xxp1;
struct cvmx_pciercx_cfg462_s cn56xx;
struct cvmx_pciercx_cfg462_s cn56xxp1;
+ struct cvmx_pciercx_cfg462_s cn61xx;
struct cvmx_pciercx_cfg462_s cn63xx;
struct cvmx_pciercx_cfg462_s cn63xxp1;
+ struct cvmx_pciercx_cfg462_s cn66xx;
+ struct cvmx_pciercx_cfg462_s cn68xx;
+ struct cvmx_pciercx_cfg462_s cn68xxp1;
};
union cvmx_pciercx_cfg463 {
@@ -1325,8 +1744,12 @@ union cvmx_pciercx_cfg463 {
struct cvmx_pciercx_cfg463_s cn52xxp1;
struct cvmx_pciercx_cfg463_s cn56xx;
struct cvmx_pciercx_cfg463_s cn56xxp1;
+ struct cvmx_pciercx_cfg463_s cn61xx;
struct cvmx_pciercx_cfg463_s cn63xx;
struct cvmx_pciercx_cfg463_s cn63xxp1;
+ struct cvmx_pciercx_cfg463_s cn66xx;
+ struct cvmx_pciercx_cfg463_s cn68xx;
+ struct cvmx_pciercx_cfg463_s cn68xxp1;
};
union cvmx_pciercx_cfg464 {
@@ -1341,8 +1764,12 @@ union cvmx_pciercx_cfg464 {
struct cvmx_pciercx_cfg464_s cn52xxp1;
struct cvmx_pciercx_cfg464_s cn56xx;
struct cvmx_pciercx_cfg464_s cn56xxp1;
+ struct cvmx_pciercx_cfg464_s cn61xx;
struct cvmx_pciercx_cfg464_s cn63xx;
struct cvmx_pciercx_cfg464_s cn63xxp1;
+ struct cvmx_pciercx_cfg464_s cn66xx;
+ struct cvmx_pciercx_cfg464_s cn68xx;
+ struct cvmx_pciercx_cfg464_s cn68xxp1;
};
union cvmx_pciercx_cfg465 {
@@ -1357,8 +1784,12 @@ union cvmx_pciercx_cfg465 {
struct cvmx_pciercx_cfg465_s cn52xxp1;
struct cvmx_pciercx_cfg465_s cn56xx;
struct cvmx_pciercx_cfg465_s cn56xxp1;
+ struct cvmx_pciercx_cfg465_s cn61xx;
struct cvmx_pciercx_cfg465_s cn63xx;
struct cvmx_pciercx_cfg465_s cn63xxp1;
+ struct cvmx_pciercx_cfg465_s cn66xx;
+ struct cvmx_pciercx_cfg465_s cn68xx;
+ struct cvmx_pciercx_cfg465_s cn68xxp1;
};
union cvmx_pciercx_cfg466 {
@@ -1376,8 +1807,12 @@ union cvmx_pciercx_cfg466 {
struct cvmx_pciercx_cfg466_s cn52xxp1;
struct cvmx_pciercx_cfg466_s cn56xx;
struct cvmx_pciercx_cfg466_s cn56xxp1;
+ struct cvmx_pciercx_cfg466_s cn61xx;
struct cvmx_pciercx_cfg466_s cn63xx;
struct cvmx_pciercx_cfg466_s cn63xxp1;
+ struct cvmx_pciercx_cfg466_s cn66xx;
+ struct cvmx_pciercx_cfg466_s cn68xx;
+ struct cvmx_pciercx_cfg466_s cn68xxp1;
};
union cvmx_pciercx_cfg467 {
@@ -1393,8 +1828,12 @@ union cvmx_pciercx_cfg467 {
struct cvmx_pciercx_cfg467_s cn52xxp1;
struct cvmx_pciercx_cfg467_s cn56xx;
struct cvmx_pciercx_cfg467_s cn56xxp1;
+ struct cvmx_pciercx_cfg467_s cn61xx;
struct cvmx_pciercx_cfg467_s cn63xx;
struct cvmx_pciercx_cfg467_s cn63xxp1;
+ struct cvmx_pciercx_cfg467_s cn66xx;
+ struct cvmx_pciercx_cfg467_s cn68xx;
+ struct cvmx_pciercx_cfg467_s cn68xxp1;
};
union cvmx_pciercx_cfg468 {
@@ -1410,8 +1849,12 @@ union cvmx_pciercx_cfg468 {
struct cvmx_pciercx_cfg468_s cn52xxp1;
struct cvmx_pciercx_cfg468_s cn56xx;
struct cvmx_pciercx_cfg468_s cn56xxp1;
+ struct cvmx_pciercx_cfg468_s cn61xx;
struct cvmx_pciercx_cfg468_s cn63xx;
struct cvmx_pciercx_cfg468_s cn63xxp1;
+ struct cvmx_pciercx_cfg468_s cn66xx;
+ struct cvmx_pciercx_cfg468_s cn68xx;
+ struct cvmx_pciercx_cfg468_s cn68xxp1;
};
union cvmx_pciercx_cfg490 {
@@ -1426,8 +1869,12 @@ union cvmx_pciercx_cfg490 {
struct cvmx_pciercx_cfg490_s cn52xxp1;
struct cvmx_pciercx_cfg490_s cn56xx;
struct cvmx_pciercx_cfg490_s cn56xxp1;
+ struct cvmx_pciercx_cfg490_s cn61xx;
struct cvmx_pciercx_cfg490_s cn63xx;
struct cvmx_pciercx_cfg490_s cn63xxp1;
+ struct cvmx_pciercx_cfg490_s cn66xx;
+ struct cvmx_pciercx_cfg490_s cn68xx;
+ struct cvmx_pciercx_cfg490_s cn68xxp1;
};
union cvmx_pciercx_cfg491 {
@@ -1442,8 +1889,12 @@ union cvmx_pciercx_cfg491 {
struct cvmx_pciercx_cfg491_s cn52xxp1;
struct cvmx_pciercx_cfg491_s cn56xx;
struct cvmx_pciercx_cfg491_s cn56xxp1;
+ struct cvmx_pciercx_cfg491_s cn61xx;
struct cvmx_pciercx_cfg491_s cn63xx;
struct cvmx_pciercx_cfg491_s cn63xxp1;
+ struct cvmx_pciercx_cfg491_s cn66xx;
+ struct cvmx_pciercx_cfg491_s cn68xx;
+ struct cvmx_pciercx_cfg491_s cn68xxp1;
};
union cvmx_pciercx_cfg492 {
@@ -1458,8 +1909,12 @@ union cvmx_pciercx_cfg492 {
struct cvmx_pciercx_cfg492_s cn52xxp1;
struct cvmx_pciercx_cfg492_s cn56xx;
struct cvmx_pciercx_cfg492_s cn56xxp1;
+ struct cvmx_pciercx_cfg492_s cn61xx;
struct cvmx_pciercx_cfg492_s cn63xx;
struct cvmx_pciercx_cfg492_s cn63xxp1;
+ struct cvmx_pciercx_cfg492_s cn66xx;
+ struct cvmx_pciercx_cfg492_s cn68xx;
+ struct cvmx_pciercx_cfg492_s cn68xxp1;
};
union cvmx_pciercx_cfg515 {
@@ -1473,8 +1928,12 @@ union cvmx_pciercx_cfg515 {
uint32_t le:9;
uint32_t n_fts:8;
} s;
+ struct cvmx_pciercx_cfg515_s cn61xx;
struct cvmx_pciercx_cfg515_s cn63xx;
struct cvmx_pciercx_cfg515_s cn63xxp1;
+ struct cvmx_pciercx_cfg515_s cn66xx;
+ struct cvmx_pciercx_cfg515_s cn68xx;
+ struct cvmx_pciercx_cfg515_s cn68xxp1;
};
union cvmx_pciercx_cfg516 {
@@ -1486,8 +1945,12 @@ union cvmx_pciercx_cfg516 {
struct cvmx_pciercx_cfg516_s cn52xxp1;
struct cvmx_pciercx_cfg516_s cn56xx;
struct cvmx_pciercx_cfg516_s cn56xxp1;
+ struct cvmx_pciercx_cfg516_s cn61xx;
struct cvmx_pciercx_cfg516_s cn63xx;
struct cvmx_pciercx_cfg516_s cn63xxp1;
+ struct cvmx_pciercx_cfg516_s cn66xx;
+ struct cvmx_pciercx_cfg516_s cn68xx;
+ struct cvmx_pciercx_cfg516_s cn68xxp1;
};
union cvmx_pciercx_cfg517 {
@@ -1499,8 +1962,12 @@ union cvmx_pciercx_cfg517 {
struct cvmx_pciercx_cfg517_s cn52xxp1;
struct cvmx_pciercx_cfg517_s cn56xx;
struct cvmx_pciercx_cfg517_s cn56xxp1;
+ struct cvmx_pciercx_cfg517_s cn61xx;
struct cvmx_pciercx_cfg517_s cn63xx;
struct cvmx_pciercx_cfg517_s cn63xxp1;
+ struct cvmx_pciercx_cfg517_s cn66xx;
+ struct cvmx_pciercx_cfg517_s cn68xx;
+ struct cvmx_pciercx_cfg517_s cn68xxp1;
};
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pemx-defs.h b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
new file mode 100644
index 0000000..be189a2
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pemx-defs.h
@@ -0,0 +1,509 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PEMX_DEFS_H__
+#define __CVMX_PEMX_DEFS_H__
+
+#define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
+#define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
+#define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
+#define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
+#define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
+
+union cvmx_pemx_bar1_indexx {
+ uint64_t u64;
+ struct cvmx_pemx_bar1_indexx_s {
+ uint64_t reserved_20_63:44;
+ uint64_t addr_idx:16;
+ uint64_t ca:1;
+ uint64_t end_swp:2;
+ uint64_t addr_v:1;
+ } s;
+ struct cvmx_pemx_bar1_indexx_s cn61xx;
+ struct cvmx_pemx_bar1_indexx_s cn63xx;
+ struct cvmx_pemx_bar1_indexx_s cn63xxp1;
+ struct cvmx_pemx_bar1_indexx_s cn66xx;
+ struct cvmx_pemx_bar1_indexx_s cn68xx;
+ struct cvmx_pemx_bar1_indexx_s cn68xxp1;
+};
+
+union cvmx_pemx_bar2_mask {
+ uint64_t u64;
+ struct cvmx_pemx_bar2_mask_s {
+ uint64_t reserved_38_63:26;
+ uint64_t mask:35;
+ uint64_t reserved_0_2:3;
+ } s;
+ struct cvmx_pemx_bar2_mask_s cn61xx;
+ struct cvmx_pemx_bar2_mask_s cn66xx;
+ struct cvmx_pemx_bar2_mask_s cn68xx;
+ struct cvmx_pemx_bar2_mask_s cn68xxp1;
+};
+
+union cvmx_pemx_bar_ctl {
+ uint64_t u64;
+ struct cvmx_pemx_bar_ctl_s {
+ uint64_t reserved_7_63:57;
+ uint64_t bar1_siz:3;
+ uint64_t bar2_enb:1;
+ uint64_t bar2_esx:2;
+ uint64_t bar2_cax:1;
+ } s;
+ struct cvmx_pemx_bar_ctl_s cn61xx;
+ struct cvmx_pemx_bar_ctl_s cn63xx;
+ struct cvmx_pemx_bar_ctl_s cn63xxp1;
+ struct cvmx_pemx_bar_ctl_s cn66xx;
+ struct cvmx_pemx_bar_ctl_s cn68xx;
+ struct cvmx_pemx_bar_ctl_s cn68xxp1;
+};
+
+union cvmx_pemx_bist_status {
+ uint64_t u64;
+ struct cvmx_pemx_bist_status_s {
+ uint64_t reserved_8_63:56;
+ uint64_t retry:1;
+ uint64_t rqdata0:1;
+ uint64_t rqdata1:1;
+ uint64_t rqdata2:1;
+ uint64_t rqdata3:1;
+ uint64_t rqhdr1:1;
+ uint64_t rqhdr0:1;
+ uint64_t sot:1;
+ } s;
+ struct cvmx_pemx_bist_status_s cn61xx;
+ struct cvmx_pemx_bist_status_s cn63xx;
+ struct cvmx_pemx_bist_status_s cn63xxp1;
+ struct cvmx_pemx_bist_status_s cn66xx;
+ struct cvmx_pemx_bist_status_s cn68xx;
+ struct cvmx_pemx_bist_status_s cn68xxp1;
+};
+
+union cvmx_pemx_bist_status2 {
+ uint64_t u64;
+ struct cvmx_pemx_bist_status2_s {
+ uint64_t reserved_10_63:54;
+ uint64_t e2p_cpl:1;
+ uint64_t e2p_n:1;
+ uint64_t e2p_p:1;
+ uint64_t peai_p2e:1;
+ uint64_t pef_tpf1:1;
+ uint64_t pef_tpf0:1;
+ uint64_t pef_tnf:1;
+ uint64_t pef_tcf1:1;
+ uint64_t pef_tc0:1;
+ uint64_t ppf:1;
+ } s;
+ struct cvmx_pemx_bist_status2_s cn61xx;
+ struct cvmx_pemx_bist_status2_s cn63xx;
+ struct cvmx_pemx_bist_status2_s cn63xxp1;
+ struct cvmx_pemx_bist_status2_s cn66xx;
+ struct cvmx_pemx_bist_status2_s cn68xx;
+ struct cvmx_pemx_bist_status2_s cn68xxp1;
+};
+
+union cvmx_pemx_cfg_rd {
+ uint64_t u64;
+ struct cvmx_pemx_cfg_rd_s {
+ uint64_t data:32;
+ uint64_t addr:32;
+ } s;
+ struct cvmx_pemx_cfg_rd_s cn61xx;
+ struct cvmx_pemx_cfg_rd_s cn63xx;
+ struct cvmx_pemx_cfg_rd_s cn63xxp1;
+ struct cvmx_pemx_cfg_rd_s cn66xx;
+ struct cvmx_pemx_cfg_rd_s cn68xx;
+ struct cvmx_pemx_cfg_rd_s cn68xxp1;
+};
+
+union cvmx_pemx_cfg_wr {
+ uint64_t u64;
+ struct cvmx_pemx_cfg_wr_s {
+ uint64_t data:32;
+ uint64_t addr:32;
+ } s;
+ struct cvmx_pemx_cfg_wr_s cn61xx;
+ struct cvmx_pemx_cfg_wr_s cn63xx;
+ struct cvmx_pemx_cfg_wr_s cn63xxp1;
+ struct cvmx_pemx_cfg_wr_s cn66xx;
+ struct cvmx_pemx_cfg_wr_s cn68xx;
+ struct cvmx_pemx_cfg_wr_s cn68xxp1;
+};
+
+union cvmx_pemx_cpl_lut_valid {
+ uint64_t u64;
+ struct cvmx_pemx_cpl_lut_valid_s {
+ uint64_t reserved_32_63:32;
+ uint64_t tag:32;
+ } s;
+ struct cvmx_pemx_cpl_lut_valid_s cn61xx;
+ struct cvmx_pemx_cpl_lut_valid_s cn63xx;
+ struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
+ struct cvmx_pemx_cpl_lut_valid_s cn66xx;
+ struct cvmx_pemx_cpl_lut_valid_s cn68xx;
+ struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
+};
+
+union cvmx_pemx_ctl_status {
+ uint64_t u64;
+ struct cvmx_pemx_ctl_status_s {
+ uint64_t reserved_48_63:16;
+ uint64_t auto_sd:1;
+ uint64_t dnum:5;
+ uint64_t pbus:8;
+ uint64_t reserved_32_33:2;
+ uint64_t cfg_rtry:16;
+ uint64_t reserved_12_15:4;
+ uint64_t pm_xtoff:1;
+ uint64_t pm_xpme:1;
+ uint64_t ob_p_cmd:1;
+ uint64_t reserved_7_8:2;
+ uint64_t nf_ecrc:1;
+ uint64_t dly_one:1;
+ uint64_t lnk_enb:1;
+ uint64_t ro_ctlp:1;
+ uint64_t fast_lm:1;
+ uint64_t inv_ecrc:1;
+ uint64_t inv_lcrc:1;
+ } s;
+ struct cvmx_pemx_ctl_status_s cn61xx;
+ struct cvmx_pemx_ctl_status_s cn63xx;
+ struct cvmx_pemx_ctl_status_s cn63xxp1;
+ struct cvmx_pemx_ctl_status_s cn66xx;
+ struct cvmx_pemx_ctl_status_s cn68xx;
+ struct cvmx_pemx_ctl_status_s cn68xxp1;
+};
+
+union cvmx_pemx_dbg_info {
+ uint64_t u64;
+ struct cvmx_pemx_dbg_info_s {
+ uint64_t reserved_31_63:33;
+ uint64_t ecrc_e:1;
+ uint64_t rawwpp:1;
+ uint64_t racpp:1;
+ uint64_t ramtlp:1;
+ uint64_t rarwdns:1;
+ uint64_t caar:1;
+ uint64_t racca:1;
+ uint64_t racur:1;
+ uint64_t rauc:1;
+ uint64_t rqo:1;
+ uint64_t fcuv:1;
+ uint64_t rpe:1;
+ uint64_t fcpvwt:1;
+ uint64_t dpeoosd:1;
+ uint64_t rtwdle:1;
+ uint64_t rdwdle:1;
+ uint64_t mre:1;
+ uint64_t rte:1;
+ uint64_t acto:1;
+ uint64_t rvdm:1;
+ uint64_t rumep:1;
+ uint64_t rptamrc:1;
+ uint64_t rpmerc:1;
+ uint64_t rfemrc:1;
+ uint64_t rnfemrc:1;
+ uint64_t rcemrc:1;
+ uint64_t rpoison:1;
+ uint64_t recrce:1;
+ uint64_t rtlplle:1;
+ uint64_t rtlpmal:1;
+ uint64_t spoison:1;
+ } s;
+ struct cvmx_pemx_dbg_info_s cn61xx;
+ struct cvmx_pemx_dbg_info_s cn63xx;
+ struct cvmx_pemx_dbg_info_s cn63xxp1;
+ struct cvmx_pemx_dbg_info_s cn66xx;
+ struct cvmx_pemx_dbg_info_s cn68xx;
+ struct cvmx_pemx_dbg_info_s cn68xxp1;
+};
+
+union cvmx_pemx_dbg_info_en {
+ uint64_t u64;
+ struct cvmx_pemx_dbg_info_en_s {
+ uint64_t reserved_31_63:33;
+ uint64_t ecrc_e:1;
+ uint64_t rawwpp:1;
+ uint64_t racpp:1;
+ uint64_t ramtlp:1;
+ uint64_t rarwdns:1;
+ uint64_t caar:1;
+ uint64_t racca:1;
+ uint64_t racur:1;
+ uint64_t rauc:1;
+ uint64_t rqo:1;
+ uint64_t fcuv:1;
+ uint64_t rpe:1;
+ uint64_t fcpvwt:1;
+ uint64_t dpeoosd:1;
+ uint64_t rtwdle:1;
+ uint64_t rdwdle:1;
+ uint64_t mre:1;
+ uint64_t rte:1;
+ uint64_t acto:1;
+ uint64_t rvdm:1;
+ uint64_t rumep:1;
+ uint64_t rptamrc:1;
+ uint64_t rpmerc:1;
+ uint64_t rfemrc:1;
+ uint64_t rnfemrc:1;
+ uint64_t rcemrc:1;
+ uint64_t rpoison:1;
+ uint64_t recrce:1;
+ uint64_t rtlplle:1;
+ uint64_t rtlpmal:1;
+ uint64_t spoison:1;
+ } s;
+ struct cvmx_pemx_dbg_info_en_s cn61xx;
+ struct cvmx_pemx_dbg_info_en_s cn63xx;
+ struct cvmx_pemx_dbg_info_en_s cn63xxp1;
+ struct cvmx_pemx_dbg_info_en_s cn66xx;
+ struct cvmx_pemx_dbg_info_en_s cn68xx;
+ struct cvmx_pemx_dbg_info_en_s cn68xxp1;
+};
+
+union cvmx_pemx_diag_status {
+ uint64_t u64;
+ struct cvmx_pemx_diag_status_s {
+ uint64_t reserved_4_63:60;
+ uint64_t pm_dst:1;
+ uint64_t pm_stat:1;
+ uint64_t pm_en:1;
+ uint64_t aux_en:1;
+ } s;
+ struct cvmx_pemx_diag_status_s cn61xx;
+ struct cvmx_pemx_diag_status_s cn63xx;
+ struct cvmx_pemx_diag_status_s cn63xxp1;
+ struct cvmx_pemx_diag_status_s cn66xx;
+ struct cvmx_pemx_diag_status_s cn68xx;
+ struct cvmx_pemx_diag_status_s cn68xxp1;
+};
+
+union cvmx_pemx_inb_read_credits {
+ uint64_t u64;
+ struct cvmx_pemx_inb_read_credits_s {
+ uint64_t reserved_6_63:58;
+ uint64_t num:6;
+ } s;
+ struct cvmx_pemx_inb_read_credits_s cn61xx;
+ struct cvmx_pemx_inb_read_credits_s cn66xx;
+ struct cvmx_pemx_inb_read_credits_s cn68xx;
+};
+
+union cvmx_pemx_int_enb {
+ uint64_t u64;
+ struct cvmx_pemx_int_enb_s {
+ uint64_t reserved_14_63:50;
+ uint64_t crs_dr:1;
+ uint64_t crs_er:1;
+ uint64_t rdlk:1;
+ uint64_t exc:1;
+ uint64_t un_bx:1;
+ uint64_t un_b2:1;
+ uint64_t un_b1:1;
+ uint64_t up_bx:1;
+ uint64_t up_b2:1;
+ uint64_t up_b1:1;
+ uint64_t pmem:1;
+ uint64_t pmei:1;
+ uint64_t se:1;
+ uint64_t aeri:1;
+ } s;
+ struct cvmx_pemx_int_enb_s cn61xx;
+ struct cvmx_pemx_int_enb_s cn63xx;
+ struct cvmx_pemx_int_enb_s cn63xxp1;
+ struct cvmx_pemx_int_enb_s cn66xx;
+ struct cvmx_pemx_int_enb_s cn68xx;
+ struct cvmx_pemx_int_enb_s cn68xxp1;
+};
+
+union cvmx_pemx_int_enb_int {
+ uint64_t u64;
+ struct cvmx_pemx_int_enb_int_s {
+ uint64_t reserved_14_63:50;
+ uint64_t crs_dr:1;
+ uint64_t crs_er:1;
+ uint64_t rdlk:1;
+ uint64_t exc:1;
+ uint64_t un_bx:1;
+ uint64_t un_b2:1;
+ uint64_t un_b1:1;
+ uint64_t up_bx:1;
+ uint64_t up_b2:1;
+ uint64_t up_b1:1;
+ uint64_t pmem:1;
+ uint64_t pmei:1;
+ uint64_t se:1;
+ uint64_t aeri:1;
+ } s;
+ struct cvmx_pemx_int_enb_int_s cn61xx;
+ struct cvmx_pemx_int_enb_int_s cn63xx;
+ struct cvmx_pemx_int_enb_int_s cn63xxp1;
+ struct cvmx_pemx_int_enb_int_s cn66xx;
+ struct cvmx_pemx_int_enb_int_s cn68xx;
+ struct cvmx_pemx_int_enb_int_s cn68xxp1;
+};
+
+union cvmx_pemx_int_sum {
+ uint64_t u64;
+ struct cvmx_pemx_int_sum_s {
+ uint64_t reserved_14_63:50;
+ uint64_t crs_dr:1;
+ uint64_t crs_er:1;
+ uint64_t rdlk:1;
+ uint64_t exc:1;
+ uint64_t un_bx:1;
+ uint64_t un_b2:1;
+ uint64_t un_b1:1;
+ uint64_t up_bx:1;
+ uint64_t up_b2:1;
+ uint64_t up_b1:1;
+ uint64_t pmem:1;
+ uint64_t pmei:1;
+ uint64_t se:1;
+ uint64_t aeri:1;
+ } s;
+ struct cvmx_pemx_int_sum_s cn61xx;
+ struct cvmx_pemx_int_sum_s cn63xx;
+ struct cvmx_pemx_int_sum_s cn63xxp1;
+ struct cvmx_pemx_int_sum_s cn66xx;
+ struct cvmx_pemx_int_sum_s cn68xx;
+ struct cvmx_pemx_int_sum_s cn68xxp1;
+};
+
+union cvmx_pemx_p2n_bar0_start {
+ uint64_t u64;
+ struct cvmx_pemx_p2n_bar0_start_s {
+ uint64_t addr:50;
+ uint64_t reserved_0_13:14;
+ } s;
+ struct cvmx_pemx_p2n_bar0_start_s cn61xx;
+ struct cvmx_pemx_p2n_bar0_start_s cn63xx;
+ struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
+ struct cvmx_pemx_p2n_bar0_start_s cn66xx;
+ struct cvmx_pemx_p2n_bar0_start_s cn68xx;
+ struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
+};
+
+union cvmx_pemx_p2n_bar1_start {
+ uint64_t u64;
+ struct cvmx_pemx_p2n_bar1_start_s {
+ uint64_t addr:38;
+ uint64_t reserved_0_25:26;
+ } s;
+ struct cvmx_pemx_p2n_bar1_start_s cn61xx;
+ struct cvmx_pemx_p2n_bar1_start_s cn63xx;
+ struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
+ struct cvmx_pemx_p2n_bar1_start_s cn66xx;
+ struct cvmx_pemx_p2n_bar1_start_s cn68xx;
+ struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
+};
+
+union cvmx_pemx_p2n_bar2_start {
+ uint64_t u64;
+ struct cvmx_pemx_p2n_bar2_start_s {
+ uint64_t addr:23;
+ uint64_t reserved_0_40:41;
+ } s;
+ struct cvmx_pemx_p2n_bar2_start_s cn61xx;
+ struct cvmx_pemx_p2n_bar2_start_s cn63xx;
+ struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
+ struct cvmx_pemx_p2n_bar2_start_s cn66xx;
+ struct cvmx_pemx_p2n_bar2_start_s cn68xx;
+ struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
+};
+
+union cvmx_pemx_p2p_barx_end {
+ uint64_t u64;
+ struct cvmx_pemx_p2p_barx_end_s {
+ uint64_t addr:52;
+ uint64_t reserved_0_11:12;
+ } s;
+ struct cvmx_pemx_p2p_barx_end_s cn63xx;
+ struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
+ struct cvmx_pemx_p2p_barx_end_s cn66xx;
+ struct cvmx_pemx_p2p_barx_end_s cn68xx;
+ struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
+};
+
+union cvmx_pemx_p2p_barx_start {
+ uint64_t u64;
+ struct cvmx_pemx_p2p_barx_start_s {
+ uint64_t addr:52;
+ uint64_t reserved_0_11:12;
+ } s;
+ struct cvmx_pemx_p2p_barx_start_s cn63xx;
+ struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
+ struct cvmx_pemx_p2p_barx_start_s cn66xx;
+ struct cvmx_pemx_p2p_barx_start_s cn68xx;
+ struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
+};
+
+union cvmx_pemx_tlp_credits {
+ uint64_t u64;
+ struct cvmx_pemx_tlp_credits_s {
+ uint64_t reserved_56_63:8;
+ uint64_t peai_ppf:8;
+ uint64_t pem_cpl:8;
+ uint64_t pem_np:8;
+ uint64_t pem_p:8;
+ uint64_t sli_cpl:8;
+ uint64_t sli_np:8;
+ uint64_t sli_p:8;
+ } s;
+ struct cvmx_pemx_tlp_credits_cn61xx {
+ uint64_t reserved_56_63:8;
+ uint64_t peai_ppf:8;
+ uint64_t reserved_24_47:24;
+ uint64_t sli_cpl:8;
+ uint64_t sli_np:8;
+ uint64_t sli_p:8;
+ } cn61xx;
+ struct cvmx_pemx_tlp_credits_s cn63xx;
+ struct cvmx_pemx_tlp_credits_s cn63xxp1;
+ struct cvmx_pemx_tlp_credits_s cn66xx;
+ struct cvmx_pemx_tlp_credits_s cn68xx;
+ struct cvmx_pemx_tlp_credits_s cn68xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
index 5ab8679..4438d21 100644
--- a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -4,7 +4,7 @@
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2011 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
@@ -25,13 +25,6 @@
* Contact Cavium Networks for more information
***********************license end**************************************/
-/**
- * cvmx-pexp-defs.h
- *
- * Configuration and status register (CSR) definitions for
- * OCTEON PEXP.
- *
- */
#ifndef __CVMX_PEXP_DEFS_H__
#define __CVMX_PEXP_DEFS_H__
@@ -139,7 +132,7 @@
#define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
#define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
#define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
-#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
#define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
#define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
#define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
@@ -152,7 +145,10 @@
#define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
#define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
#define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
+#define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
#define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
+#define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
#define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
#define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
#define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
@@ -206,6 +202,7 @@
#define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
#define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
#define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
+#define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
#define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
#define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
#define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
@@ -214,12 +211,14 @@
#define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
#define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
#define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
-#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 1) * 16)
+#define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
+#define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
#define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
#define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
#define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
#define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
#define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
+#define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
#define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))
#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
new file mode 100644
index 0000000..7c6c901
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -0,0 +1,2172 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SLI_DEFS_H__
+#define __CVMX_SLI_DEFS_H__
+
+#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
+#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
+#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
+#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
+#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
+#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
+#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
+#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
+#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
+#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
+#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
+#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
+#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
+#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
+#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
+#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
+#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
+#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
+#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
+#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
+#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
+#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
+#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
+#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
+#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
+#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
+#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
+#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
+#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
+#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
+#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
+#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
+#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
+#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
+#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
+#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
+#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
+#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
+#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
+#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
+#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
+#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
+#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
+#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
+#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
+#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
+#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
+#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
+#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
+#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
+#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
+#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
+#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
+#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
+#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
+#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
+#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
+#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
+#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
+#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
+#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
+#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
+#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
+#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
+#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
+#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
+#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
+#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
+#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
+#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
+#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
+#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
+#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
+#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
+#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
+#define CVMX_SLI_STATE1 (0x0000000000000620ull)
+#define CVMX_SLI_STATE2 (0x0000000000000630ull)
+#define CVMX_SLI_STATE3 (0x0000000000000640ull)
+#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
+#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
+#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
+#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
+#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
+#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
+#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
+
+union cvmx_sli_bist_status {
+ uint64_t u64;
+ struct cvmx_sli_bist_status_s {
+ uint64_t reserved_32_63:32;
+ uint64_t ncb_req:1;
+ uint64_t n2p0_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p1_o:1;
+ uint64_t cpl_p0:1;
+ uint64_t cpl_p1:1;
+ uint64_t reserved_19_24:6;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t reserved_6_8:3;
+ uint64_t dsi1_1:1;
+ uint64_t dsi1_0:1;
+ uint64_t dsi0_1:1;
+ uint64_t dsi0_0:1;
+ uint64_t msi:1;
+ uint64_t ncb_cmd:1;
+ } s;
+ struct cvmx_sli_bist_status_cn61xx {
+ uint64_t reserved_31_63:33;
+ uint64_t n2p0_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t reserved_27_28:2;
+ uint64_t cpl_p0:1;
+ uint64_t cpl_p1:1;
+ uint64_t reserved_19_24:6;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t reserved_6_8:3;
+ uint64_t dsi1_1:1;
+ uint64_t dsi1_0:1;
+ uint64_t dsi0_1:1;
+ uint64_t dsi0_0:1;
+ uint64_t msi:1;
+ uint64_t ncb_cmd:1;
+ } cn61xx;
+ struct cvmx_sli_bist_status_cn63xx {
+ uint64_t reserved_31_63:33;
+ uint64_t n2p0_c:1;
+ uint64_t n2p0_o:1;
+ uint64_t n2p1_c:1;
+ uint64_t n2p1_o:1;
+ uint64_t cpl_p0:1;
+ uint64_t cpl_p1:1;
+ uint64_t reserved_19_24:6;
+ uint64_t p2n0_c0:1;
+ uint64_t p2n0_c1:1;
+ uint64_t p2n0_n:1;
+ uint64_t p2n0_p0:1;
+ uint64_t p2n0_p1:1;
+ uint64_t p2n1_c0:1;
+ uint64_t p2n1_c1:1;
+ uint64_t p2n1_n:1;
+ uint64_t p2n1_p0:1;
+ uint64_t p2n1_p1:1;
+ uint64_t reserved_6_8:3;
+ uint64_t dsi1_1:1;
+ uint64_t dsi1_0:1;
+ uint64_t dsi0_1:1;
+ uint64_t dsi0_0:1;
+ uint64_t msi:1;
+ uint64_t ncb_cmd:1;
+ } cn63xx;
+ struct cvmx_sli_bist_status_cn63xx cn63xxp1;
+ struct cvmx_sli_bist_status_cn61xx cn66xx;
+ struct cvmx_sli_bist_status_s cn68xx;
+ struct cvmx_sli_bist_status_s cn68xxp1;
+};
+
+union cvmx_sli_ctl_portx {
+ uint64_t u64;
+ struct cvmx_sli_ctl_portx_s {
+ uint64_t reserved_22_63:42;
+ uint64_t intd:1;
+ uint64_t intc:1;
+ uint64_t intb:1;
+ uint64_t inta:1;
+ uint64_t dis_port:1;
+ uint64_t waitl_com:1;
+ uint64_t intd_map:2;
+ uint64_t intc_map:2;
+ uint64_t intb_map:2;
+ uint64_t inta_map:2;
+ uint64_t ctlp_ro:1;
+ uint64_t reserved_6_6:1;
+ uint64_t ptlp_ro:1;
+ uint64_t reserved_1_4:4;
+ uint64_t wait_com:1;
+ } s;
+ struct cvmx_sli_ctl_portx_s cn61xx;
+ struct cvmx_sli_ctl_portx_s cn63xx;
+ struct cvmx_sli_ctl_portx_s cn63xxp1;
+ struct cvmx_sli_ctl_portx_s cn66xx;
+ struct cvmx_sli_ctl_portx_s cn68xx;
+ struct cvmx_sli_ctl_portx_s cn68xxp1;
+};
+
+union cvmx_sli_ctl_status {
+ uint64_t u64;
+ struct cvmx_sli_ctl_status_s {
+ uint64_t reserved_20_63:44;
+ uint64_t p1_ntags:6;
+ uint64_t p0_ntags:6;
+ uint64_t chip_rev:8;
+ } s;
+ struct cvmx_sli_ctl_status_cn61xx {
+ uint64_t reserved_14_63:50;
+ uint64_t p0_ntags:6;
+ uint64_t chip_rev:8;
+ } cn61xx;
+ struct cvmx_sli_ctl_status_s cn63xx;
+ struct cvmx_sli_ctl_status_s cn63xxp1;
+ struct cvmx_sli_ctl_status_cn61xx cn66xx;
+ struct cvmx_sli_ctl_status_s cn68xx;
+ struct cvmx_sli_ctl_status_s cn68xxp1;
+};
+
+union cvmx_sli_data_out_cnt {
+ uint64_t u64;
+ struct cvmx_sli_data_out_cnt_s {
+ uint64_t reserved_44_63:20;
+ uint64_t p1_ucnt:16;
+ uint64_t p1_fcnt:6;
+ uint64_t p0_ucnt:16;
+ uint64_t p0_fcnt:6;
+ } s;
+ struct cvmx_sli_data_out_cnt_s cn61xx;
+ struct cvmx_sli_data_out_cnt_s cn63xx;
+ struct cvmx_sli_data_out_cnt_s cn63xxp1;
+ struct cvmx_sli_data_out_cnt_s cn66xx;
+ struct cvmx_sli_data_out_cnt_s cn68xx;
+ struct cvmx_sli_data_out_cnt_s cn68xxp1;
+};
+
+union cvmx_sli_dbg_data {
+ uint64_t u64;
+ struct cvmx_sli_dbg_data_s {
+ uint64_t reserved_18_63:46;
+ uint64_t dsel_ext:1;
+ uint64_t data:17;
+ } s;
+ struct cvmx_sli_dbg_data_s cn61xx;
+ struct cvmx_sli_dbg_data_s cn63xx;
+ struct cvmx_sli_dbg_data_s cn63xxp1;
+ struct cvmx_sli_dbg_data_s cn66xx;
+ struct cvmx_sli_dbg_data_s cn68xx;
+ struct cvmx_sli_dbg_data_s cn68xxp1;
+};
+
+union cvmx_sli_dbg_select {
+ uint64_t u64;
+ struct cvmx_sli_dbg_select_s {
+ uint64_t reserved_33_63:31;
+ uint64_t adbg_sel:1;
+ uint64_t dbg_sel:32;
+ } s;
+ struct cvmx_sli_dbg_select_s cn61xx;
+ struct cvmx_sli_dbg_select_s cn63xx;
+ struct cvmx_sli_dbg_select_s cn63xxp1;
+ struct cvmx_sli_dbg_select_s cn66xx;
+ struct cvmx_sli_dbg_select_s cn68xx;
+ struct cvmx_sli_dbg_select_s cn68xxp1;
+};
+
+union cvmx_sli_dmax_cnt {
+ uint64_t u64;
+ struct cvmx_sli_dmax_cnt_s {
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+ } s;
+ struct cvmx_sli_dmax_cnt_s cn61xx;
+ struct cvmx_sli_dmax_cnt_s cn63xx;
+ struct cvmx_sli_dmax_cnt_s cn63xxp1;
+ struct cvmx_sli_dmax_cnt_s cn66xx;
+ struct cvmx_sli_dmax_cnt_s cn68xx;
+ struct cvmx_sli_dmax_cnt_s cn68xxp1;
+};
+
+union cvmx_sli_dmax_int_level {
+ uint64_t u64;
+ struct cvmx_sli_dmax_int_level_s {
+ uint64_t time:32;
+ uint64_t cnt:32;
+ } s;
+ struct cvmx_sli_dmax_int_level_s cn61xx;
+ struct cvmx_sli_dmax_int_level_s cn63xx;
+ struct cvmx_sli_dmax_int_level_s cn63xxp1;
+ struct cvmx_sli_dmax_int_level_s cn66xx;
+ struct cvmx_sli_dmax_int_level_s cn68xx;
+ struct cvmx_sli_dmax_int_level_s cn68xxp1;
+};
+
+union cvmx_sli_dmax_tim {
+ uint64_t u64;
+ struct cvmx_sli_dmax_tim_s {
+ uint64_t reserved_32_63:32;
+ uint64_t tim:32;
+ } s;
+ struct cvmx_sli_dmax_tim_s cn61xx;
+ struct cvmx_sli_dmax_tim_s cn63xx;
+ struct cvmx_sli_dmax_tim_s cn63xxp1;
+ struct cvmx_sli_dmax_tim_s cn66xx;
+ struct cvmx_sli_dmax_tim_s cn68xx;
+ struct cvmx_sli_dmax_tim_s cn68xxp1;
+};
+
+union cvmx_sli_int_enb_ciu {
+ uint64_t u64;
+ struct cvmx_sli_int_enb_ciu_s {
+ uint64_t reserved_62_63:2;
+ uint64_t pipe_err:1;
+ uint64_t ill_pad:1;
+ uint64_t sprt3_err:1;
+ uint64_t sprt2_err:1;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_28_31:4;
+ uint64_t m3_un_wi:1;
+ uint64_t m3_un_b0:1;
+ uint64_t m3_up_wi:1;
+ uint64_t m3_up_b0:1;
+ uint64_t m2_un_wi:1;
+ uint64_t m2_un_b0:1;
+ uint64_t m2_up_wi:1;
+ uint64_t m2_up_b0:1;
+ uint64_t reserved_18_19:2;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } s;
+ struct cvmx_sli_int_enb_ciu_cn61xx {
+ uint64_t reserved_61_63:3;
+ uint64_t ill_pad:1;
+ uint64_t sprt3_err:1;
+ uint64_t sprt2_err:1;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_28_31:4;
+ uint64_t m3_un_wi:1;
+ uint64_t m3_un_b0:1;
+ uint64_t m3_up_wi:1;
+ uint64_t m3_up_b0:1;
+ uint64_t m2_un_wi:1;
+ uint64_t m2_un_b0:1;
+ uint64_t m2_up_wi:1;
+ uint64_t m2_up_b0:1;
+ uint64_t reserved_18_19:2;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } cn61xx;
+ struct cvmx_sli_int_enb_ciu_cn63xx {
+ uint64_t reserved_61_63:3;
+ uint64_t ill_pad:1;
+ uint64_t reserved_58_59:2;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_18_31:14;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } cn63xx;
+ struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
+ struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
+ struct cvmx_sli_int_enb_ciu_cn68xx {
+ uint64_t reserved_62_63:2;
+ uint64_t pipe_err:1;
+ uint64_t ill_pad:1;
+ uint64_t reserved_58_59:2;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t reserved_51_51:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_18_31:14;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } cn68xx;
+ struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_int_enb_portx {
+ uint64_t u64;
+ struct cvmx_sli_int_enb_portx_s {
+ uint64_t reserved_62_63:2;
+ uint64_t pipe_err:1;
+ uint64_t ill_pad:1;
+ uint64_t sprt3_err:1;
+ uint64_t sprt2_err:1;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_28_31:4;
+ uint64_t m3_un_wi:1;
+ uint64_t m3_un_b0:1;
+ uint64_t m3_up_wi:1;
+ uint64_t m3_up_b0:1;
+ uint64_t m2_un_wi:1;
+ uint64_t m2_un_b0:1;
+ uint64_t m2_up_wi:1;
+ uint64_t m2_up_b0:1;
+ uint64_t mac1_int:1;
+ uint64_t mac0_int:1;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } s;
+ struct cvmx_sli_int_enb_portx_cn61xx {
+ uint64_t reserved_61_63:3;
+ uint64_t ill_pad:1;
+ uint64_t sprt3_err:1;
+ uint64_t sprt2_err:1;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_28_31:4;
+ uint64_t m3_un_wi:1;
+ uint64_t m3_un_b0:1;
+ uint64_t m3_up_wi:1;
+ uint64_t m3_up_b0:1;
+ uint64_t m2_un_wi:1;
+ uint64_t m2_un_b0:1;
+ uint64_t m2_up_wi:1;
+ uint64_t m2_up_b0:1;
+ uint64_t mac1_int:1;
+ uint64_t mac0_int:1;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } cn61xx;
+ struct cvmx_sli_int_enb_portx_cn63xx {
+ uint64_t reserved_61_63:3;
+ uint64_t ill_pad:1;
+ uint64_t reserved_58_59:2;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_20_31:12;
+ uint64_t mac1_int:1;
+ uint64_t mac0_int:1;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } cn63xx;
+ struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
+ struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
+ struct cvmx_sli_int_enb_portx_cn68xx {
+ uint64_t reserved_62_63:2;
+ uint64_t pipe_err:1;
+ uint64_t ill_pad:1;
+ uint64_t reserved_58_59:2;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t reserved_51_51:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_20_31:12;
+ uint64_t mac1_int:1;
+ uint64_t mac0_int:1;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } cn68xx;
+ struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_int_sum {
+ uint64_t u64;
+ struct cvmx_sli_int_sum_s {
+ uint64_t reserved_62_63:2;
+ uint64_t pipe_err:1;
+ uint64_t ill_pad:1;
+ uint64_t sprt3_err:1;
+ uint64_t sprt2_err:1;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_28_31:4;
+ uint64_t m3_un_wi:1;
+ uint64_t m3_un_b0:1;
+ uint64_t m3_up_wi:1;
+ uint64_t m3_up_b0:1;
+ uint64_t m2_un_wi:1;
+ uint64_t m2_un_b0:1;
+ uint64_t m2_up_wi:1;
+ uint64_t m2_up_b0:1;
+ uint64_t mac1_int:1;
+ uint64_t mac0_int:1;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } s;
+ struct cvmx_sli_int_sum_cn61xx {
+ uint64_t reserved_61_63:3;
+ uint64_t ill_pad:1;
+ uint64_t sprt3_err:1;
+ uint64_t sprt2_err:1;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_28_31:4;
+ uint64_t m3_un_wi:1;
+ uint64_t m3_un_b0:1;
+ uint64_t m3_up_wi:1;
+ uint64_t m3_up_b0:1;
+ uint64_t m2_un_wi:1;
+ uint64_t m2_un_b0:1;
+ uint64_t m2_up_wi:1;
+ uint64_t m2_up_b0:1;
+ uint64_t mac1_int:1;
+ uint64_t mac0_int:1;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } cn61xx;
+ struct cvmx_sli_int_sum_cn63xx {
+ uint64_t reserved_61_63:3;
+ uint64_t ill_pad:1;
+ uint64_t reserved_58_59:2;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t pin_bp:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_20_31:12;
+ uint64_t mac1_int:1;
+ uint64_t mac0_int:1;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } cn63xx;
+ struct cvmx_sli_int_sum_cn63xx cn63xxp1;
+ struct cvmx_sli_int_sum_cn61xx cn66xx;
+ struct cvmx_sli_int_sum_cn68xx {
+ uint64_t reserved_62_63:2;
+ uint64_t pipe_err:1;
+ uint64_t ill_pad:1;
+ uint64_t reserved_58_59:2;
+ uint64_t sprt1_err:1;
+ uint64_t sprt0_err:1;
+ uint64_t pins_err:1;
+ uint64_t pop_err:1;
+ uint64_t pdi_err:1;
+ uint64_t pgl_err:1;
+ uint64_t reserved_51_51:1;
+ uint64_t pout_err:1;
+ uint64_t psldbof:1;
+ uint64_t pidbof:1;
+ uint64_t reserved_38_47:10;
+ uint64_t dtime:2;
+ uint64_t dcnt:2;
+ uint64_t dmafi:2;
+ uint64_t reserved_20_31:12;
+ uint64_t mac1_int:1;
+ uint64_t mac0_int:1;
+ uint64_t mio_int1:1;
+ uint64_t mio_int0:1;
+ uint64_t m1_un_wi:1;
+ uint64_t m1_un_b0:1;
+ uint64_t m1_up_wi:1;
+ uint64_t m1_up_b0:1;
+ uint64_t m0_un_wi:1;
+ uint64_t m0_un_b0:1;
+ uint64_t m0_up_wi:1;
+ uint64_t m0_up_b0:1;
+ uint64_t reserved_6_7:2;
+ uint64_t ptime:1;
+ uint64_t pcnt:1;
+ uint64_t iob2big:1;
+ uint64_t bar0_to:1;
+ uint64_t reserved_1_1:1;
+ uint64_t rml_to:1;
+ } cn68xx;
+ struct cvmx_sli_int_sum_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_last_win_rdata0 {
+ uint64_t u64;
+ struct cvmx_sli_last_win_rdata0_s {
+ uint64_t data:64;
+ } s;
+ struct cvmx_sli_last_win_rdata0_s cn61xx;
+ struct cvmx_sli_last_win_rdata0_s cn63xx;
+ struct cvmx_sli_last_win_rdata0_s cn63xxp1;
+ struct cvmx_sli_last_win_rdata0_s cn66xx;
+ struct cvmx_sli_last_win_rdata0_s cn68xx;
+ struct cvmx_sli_last_win_rdata0_s cn68xxp1;
+};
+
+union cvmx_sli_last_win_rdata1 {
+ uint64_t u64;
+ struct cvmx_sli_last_win_rdata1_s {
+ uint64_t data:64;
+ } s;
+ struct cvmx_sli_last_win_rdata1_s cn61xx;
+ struct cvmx_sli_last_win_rdata1_s cn63xx;
+ struct cvmx_sli_last_win_rdata1_s cn63xxp1;
+ struct cvmx_sli_last_win_rdata1_s cn66xx;
+ struct cvmx_sli_last_win_rdata1_s cn68xx;
+ struct cvmx_sli_last_win_rdata1_s cn68xxp1;
+};
+
+union cvmx_sli_last_win_rdata2 {
+ uint64_t u64;
+ struct cvmx_sli_last_win_rdata2_s {
+ uint64_t data:64;
+ } s;
+ struct cvmx_sli_last_win_rdata2_s cn61xx;
+ struct cvmx_sli_last_win_rdata2_s cn66xx;
+};
+
+union cvmx_sli_last_win_rdata3 {
+ uint64_t u64;
+ struct cvmx_sli_last_win_rdata3_s {
+ uint64_t data:64;
+ } s;
+ struct cvmx_sli_last_win_rdata3_s cn61xx;
+ struct cvmx_sli_last_win_rdata3_s cn66xx;
+};
+
+union cvmx_sli_mac_credit_cnt {
+ uint64_t u64;
+ struct cvmx_sli_mac_credit_cnt_s {
+ uint64_t reserved_54_63:10;
+ uint64_t p1_c_d:1;
+ uint64_t p1_n_d:1;
+ uint64_t p1_p_d:1;
+ uint64_t p0_c_d:1;
+ uint64_t p0_n_d:1;
+ uint64_t p0_p_d:1;
+ uint64_t p1_ccnt:8;
+ uint64_t p1_ncnt:8;
+ uint64_t p1_pcnt:8;
+ uint64_t p0_ccnt:8;
+ uint64_t p0_ncnt:8;
+ uint64_t p0_pcnt:8;
+ } s;
+ struct cvmx_sli_mac_credit_cnt_s cn61xx;
+ struct cvmx_sli_mac_credit_cnt_s cn63xx;
+ struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
+ uint64_t reserved_48_63:16;
+ uint64_t p1_ccnt:8;
+ uint64_t p1_ncnt:8;
+ uint64_t p1_pcnt:8;
+ uint64_t p0_ccnt:8;
+ uint64_t p0_ncnt:8;
+ uint64_t p0_pcnt:8;
+ } cn63xxp1;
+ struct cvmx_sli_mac_credit_cnt_s cn66xx;
+ struct cvmx_sli_mac_credit_cnt_s cn68xx;
+ struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
+};
+
+union cvmx_sli_mac_credit_cnt2 {
+ uint64_t u64;
+ struct cvmx_sli_mac_credit_cnt2_s {
+ uint64_t reserved_54_63:10;
+ uint64_t p3_c_d:1;
+ uint64_t p3_n_d:1;
+ uint64_t p3_p_d:1;
+ uint64_t p2_c_d:1;
+ uint64_t p2_n_d:1;
+ uint64_t p2_p_d:1;
+ uint64_t p3_ccnt:8;
+ uint64_t p3_ncnt:8;
+ uint64_t p3_pcnt:8;
+ uint64_t p2_ccnt:8;
+ uint64_t p2_ncnt:8;
+ uint64_t p2_pcnt:8;
+ } s;
+ struct cvmx_sli_mac_credit_cnt2_s cn61xx;
+ struct cvmx_sli_mac_credit_cnt2_s cn66xx;
+};
+
+union cvmx_sli_mac_number {
+ uint64_t u64;
+ struct cvmx_sli_mac_number_s {
+ uint64_t reserved_9_63:55;
+ uint64_t a_mode:1;
+ uint64_t num:8;
+ } s;
+ struct cvmx_sli_mac_number_s cn61xx;
+ struct cvmx_sli_mac_number_cn63xx {
+ uint64_t reserved_8_63:56;
+ uint64_t num:8;
+ } cn63xx;
+ struct cvmx_sli_mac_number_s cn66xx;
+ struct cvmx_sli_mac_number_cn63xx cn68xx;
+ struct cvmx_sli_mac_number_cn63xx cn68xxp1;
+};
+
+union cvmx_sli_mem_access_ctl {
+ uint64_t u64;
+ struct cvmx_sli_mem_access_ctl_s {
+ uint64_t reserved_14_63:50;
+ uint64_t max_word:4;
+ uint64_t timer:10;
+ } s;
+ struct cvmx_sli_mem_access_ctl_s cn61xx;
+ struct cvmx_sli_mem_access_ctl_s cn63xx;
+ struct cvmx_sli_mem_access_ctl_s cn63xxp1;
+ struct cvmx_sli_mem_access_ctl_s cn66xx;
+ struct cvmx_sli_mem_access_ctl_s cn68xx;
+ struct cvmx_sli_mem_access_ctl_s cn68xxp1;
+};
+
+union cvmx_sli_mem_access_subidx {
+ uint64_t u64;
+ struct cvmx_sli_mem_access_subidx_s {
+ uint64_t reserved_43_63:21;
+ uint64_t zero:1;
+ uint64_t port:3;
+ uint64_t nmerge:1;
+ uint64_t esr:2;
+ uint64_t esw:2;
+ uint64_t wtype:2;
+ uint64_t rtype:2;
+ uint64_t reserved_0_29:30;
+ } s;
+ struct cvmx_sli_mem_access_subidx_cn61xx {
+ uint64_t reserved_43_63:21;
+ uint64_t zero:1;
+ uint64_t port:3;
+ uint64_t nmerge:1;
+ uint64_t esr:2;
+ uint64_t esw:2;
+ uint64_t wtype:2;
+ uint64_t rtype:2;
+ uint64_t ba:30;
+ } cn61xx;
+ struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
+ struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
+ struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
+ struct cvmx_sli_mem_access_subidx_cn68xx {
+ uint64_t reserved_43_63:21;
+ uint64_t zero:1;
+ uint64_t port:3;
+ uint64_t nmerge:1;
+ uint64_t esr:2;
+ uint64_t esw:2;
+ uint64_t wtype:2;
+ uint64_t rtype:2;
+ uint64_t ba:28;
+ uint64_t reserved_0_1:2;
+ } cn68xx;
+ struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
+};
+
+union cvmx_sli_msi_enb0 {
+ uint64_t u64;
+ struct cvmx_sli_msi_enb0_s {
+ uint64_t enb:64;
+ } s;
+ struct cvmx_sli_msi_enb0_s cn61xx;
+ struct cvmx_sli_msi_enb0_s cn63xx;
+ struct cvmx_sli_msi_enb0_s cn63xxp1;
+ struct cvmx_sli_msi_enb0_s cn66xx;
+ struct cvmx_sli_msi_enb0_s cn68xx;
+ struct cvmx_sli_msi_enb0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_enb1 {
+ uint64_t u64;
+ struct cvmx_sli_msi_enb1_s {
+ uint64_t enb:64;
+ } s;
+ struct cvmx_sli_msi_enb1_s cn61xx;
+ struct cvmx_sli_msi_enb1_s cn63xx;
+ struct cvmx_sli_msi_enb1_s cn63xxp1;
+ struct cvmx_sli_msi_enb1_s cn66xx;
+ struct cvmx_sli_msi_enb1_s cn68xx;
+ struct cvmx_sli_msi_enb1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_enb2 {
+ uint64_t u64;
+ struct cvmx_sli_msi_enb2_s {
+ uint64_t enb:64;
+ } s;
+ struct cvmx_sli_msi_enb2_s cn61xx;
+ struct cvmx_sli_msi_enb2_s cn63xx;
+ struct cvmx_sli_msi_enb2_s cn63xxp1;
+ struct cvmx_sli_msi_enb2_s cn66xx;
+ struct cvmx_sli_msi_enb2_s cn68xx;
+ struct cvmx_sli_msi_enb2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_enb3 {
+ uint64_t u64;
+ struct cvmx_sli_msi_enb3_s {
+ uint64_t enb:64;
+ } s;
+ struct cvmx_sli_msi_enb3_s cn61xx;
+ struct cvmx_sli_msi_enb3_s cn63xx;
+ struct cvmx_sli_msi_enb3_s cn63xxp1;
+ struct cvmx_sli_msi_enb3_s cn66xx;
+ struct cvmx_sli_msi_enb3_s cn68xx;
+ struct cvmx_sli_msi_enb3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv0 {
+ uint64_t u64;
+ struct cvmx_sli_msi_rcv0_s {
+ uint64_t intr:64;
+ } s;
+ struct cvmx_sli_msi_rcv0_s cn61xx;
+ struct cvmx_sli_msi_rcv0_s cn63xx;
+ struct cvmx_sli_msi_rcv0_s cn63xxp1;
+ struct cvmx_sli_msi_rcv0_s cn66xx;
+ struct cvmx_sli_msi_rcv0_s cn68xx;
+ struct cvmx_sli_msi_rcv0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv1 {
+ uint64_t u64;
+ struct cvmx_sli_msi_rcv1_s {
+ uint64_t intr:64;
+ } s;
+ struct cvmx_sli_msi_rcv1_s cn61xx;
+ struct cvmx_sli_msi_rcv1_s cn63xx;
+ struct cvmx_sli_msi_rcv1_s cn63xxp1;
+ struct cvmx_sli_msi_rcv1_s cn66xx;
+ struct cvmx_sli_msi_rcv1_s cn68xx;
+ struct cvmx_sli_msi_rcv1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv2 {
+ uint64_t u64;
+ struct cvmx_sli_msi_rcv2_s {
+ uint64_t intr:64;
+ } s;
+ struct cvmx_sli_msi_rcv2_s cn61xx;
+ struct cvmx_sli_msi_rcv2_s cn63xx;
+ struct cvmx_sli_msi_rcv2_s cn63xxp1;
+ struct cvmx_sli_msi_rcv2_s cn66xx;
+ struct cvmx_sli_msi_rcv2_s cn68xx;
+ struct cvmx_sli_msi_rcv2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rcv3 {
+ uint64_t u64;
+ struct cvmx_sli_msi_rcv3_s {
+ uint64_t intr:64;
+ } s;
+ struct cvmx_sli_msi_rcv3_s cn61xx;
+ struct cvmx_sli_msi_rcv3_s cn63xx;
+ struct cvmx_sli_msi_rcv3_s cn63xxp1;
+ struct cvmx_sli_msi_rcv3_s cn66xx;
+ struct cvmx_sli_msi_rcv3_s cn68xx;
+ struct cvmx_sli_msi_rcv3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_rd_map {
+ uint64_t u64;
+ struct cvmx_sli_msi_rd_map_s {
+ uint64_t reserved_16_63:48;
+ uint64_t rd_int:8;
+ uint64_t msi_int:8;
+ } s;
+ struct cvmx_sli_msi_rd_map_s cn61xx;
+ struct cvmx_sli_msi_rd_map_s cn63xx;
+ struct cvmx_sli_msi_rd_map_s cn63xxp1;
+ struct cvmx_sli_msi_rd_map_s cn66xx;
+ struct cvmx_sli_msi_rd_map_s cn68xx;
+ struct cvmx_sli_msi_rd_map_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb0 {
+ uint64_t u64;
+ struct cvmx_sli_msi_w1c_enb0_s {
+ uint64_t clr:64;
+ } s;
+ struct cvmx_sli_msi_w1c_enb0_s cn61xx;
+ struct cvmx_sli_msi_w1c_enb0_s cn63xx;
+ struct cvmx_sli_msi_w1c_enb0_s cn63xxp1;
+ struct cvmx_sli_msi_w1c_enb0_s cn66xx;
+ struct cvmx_sli_msi_w1c_enb0_s cn68xx;
+ struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb1 {
+ uint64_t u64;
+ struct cvmx_sli_msi_w1c_enb1_s {
+ uint64_t clr:64;
+ } s;
+ struct cvmx_sli_msi_w1c_enb1_s cn61xx;
+ struct cvmx_sli_msi_w1c_enb1_s cn63xx;
+ struct cvmx_sli_msi_w1c_enb1_s cn63xxp1;
+ struct cvmx_sli_msi_w1c_enb1_s cn66xx;
+ struct cvmx_sli_msi_w1c_enb1_s cn68xx;
+ struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb2 {
+ uint64_t u64;
+ struct cvmx_sli_msi_w1c_enb2_s {
+ uint64_t clr:64;
+ } s;
+ struct cvmx_sli_msi_w1c_enb2_s cn61xx;
+ struct cvmx_sli_msi_w1c_enb2_s cn63xx;
+ struct cvmx_sli_msi_w1c_enb2_s cn63xxp1;
+ struct cvmx_sli_msi_w1c_enb2_s cn66xx;
+ struct cvmx_sli_msi_w1c_enb2_s cn68xx;
+ struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1c_enb3 {
+ uint64_t u64;
+ struct cvmx_sli_msi_w1c_enb3_s {
+ uint64_t clr:64;
+ } s;
+ struct cvmx_sli_msi_w1c_enb3_s cn61xx;
+ struct cvmx_sli_msi_w1c_enb3_s cn63xx;
+ struct cvmx_sli_msi_w1c_enb3_s cn63xxp1;
+ struct cvmx_sli_msi_w1c_enb3_s cn66xx;
+ struct cvmx_sli_msi_w1c_enb3_s cn68xx;
+ struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb0 {
+ uint64_t u64;
+ struct cvmx_sli_msi_w1s_enb0_s {
+ uint64_t set:64;
+ } s;
+ struct cvmx_sli_msi_w1s_enb0_s cn61xx;
+ struct cvmx_sli_msi_w1s_enb0_s cn63xx;
+ struct cvmx_sli_msi_w1s_enb0_s cn63xxp1;
+ struct cvmx_sli_msi_w1s_enb0_s cn66xx;
+ struct cvmx_sli_msi_w1s_enb0_s cn68xx;
+ struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb1 {
+ uint64_t u64;
+ struct cvmx_sli_msi_w1s_enb1_s {
+ uint64_t set:64;
+ } s;
+ struct cvmx_sli_msi_w1s_enb1_s cn61xx;
+ struct cvmx_sli_msi_w1s_enb1_s cn63xx;
+ struct cvmx_sli_msi_w1s_enb1_s cn63xxp1;
+ struct cvmx_sli_msi_w1s_enb1_s cn66xx;
+ struct cvmx_sli_msi_w1s_enb1_s cn68xx;
+ struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb2 {
+ uint64_t u64;
+ struct cvmx_sli_msi_w1s_enb2_s {
+ uint64_t set:64;
+ } s;
+ struct cvmx_sli_msi_w1s_enb2_s cn61xx;
+ struct cvmx_sli_msi_w1s_enb2_s cn63xx;
+ struct cvmx_sli_msi_w1s_enb2_s cn63xxp1;
+ struct cvmx_sli_msi_w1s_enb2_s cn66xx;
+ struct cvmx_sli_msi_w1s_enb2_s cn68xx;
+ struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
+};
+
+union cvmx_sli_msi_w1s_enb3 {
+ uint64_t u64;
+ struct cvmx_sli_msi_w1s_enb3_s {
+ uint64_t set:64;
+ } s;
+ struct cvmx_sli_msi_w1s_enb3_s cn61xx;
+ struct cvmx_sli_msi_w1s_enb3_s cn63xx;
+ struct cvmx_sli_msi_w1s_enb3_s cn63xxp1;
+ struct cvmx_sli_msi_w1s_enb3_s cn66xx;
+ struct cvmx_sli_msi_w1s_enb3_s cn68xx;
+ struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
+};
+
+union cvmx_sli_msi_wr_map {
+ uint64_t u64;
+ struct cvmx_sli_msi_wr_map_s {
+ uint64_t reserved_16_63:48;
+ uint64_t ciu_int:8;
+ uint64_t msi_int:8;
+ } s;
+ struct cvmx_sli_msi_wr_map_s cn61xx;
+ struct cvmx_sli_msi_wr_map_s cn63xx;
+ struct cvmx_sli_msi_wr_map_s cn63xxp1;
+ struct cvmx_sli_msi_wr_map_s cn66xx;
+ struct cvmx_sli_msi_wr_map_s cn68xx;
+ struct cvmx_sli_msi_wr_map_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv {
+ uint64_t u64;
+ struct cvmx_sli_pcie_msi_rcv_s {
+ uint64_t reserved_8_63:56;
+ uint64_t intr:8;
+ } s;
+ struct cvmx_sli_pcie_msi_rcv_s cn61xx;
+ struct cvmx_sli_pcie_msi_rcv_s cn63xx;
+ struct cvmx_sli_pcie_msi_rcv_s cn63xxp1;
+ struct cvmx_sli_pcie_msi_rcv_s cn66xx;
+ struct cvmx_sli_pcie_msi_rcv_s cn68xx;
+ struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv_b1 {
+ uint64_t u64;
+ struct cvmx_sli_pcie_msi_rcv_b1_s {
+ uint64_t reserved_16_63:48;
+ uint64_t intr:8;
+ uint64_t reserved_0_7:8;
+ } s;
+ struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
+ struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
+ struct cvmx_sli_pcie_msi_rcv_b1_s cn63xxp1;
+ struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
+ struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
+ struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv_b2 {
+ uint64_t u64;
+ struct cvmx_sli_pcie_msi_rcv_b2_s {
+ uint64_t reserved_24_63:40;
+ uint64_t intr:8;
+ uint64_t reserved_0_15:16;
+ } s;
+ struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
+ struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
+ struct cvmx_sli_pcie_msi_rcv_b2_s cn63xxp1;
+ struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
+ struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
+ struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
+};
+
+union cvmx_sli_pcie_msi_rcv_b3 {
+ uint64_t u64;
+ struct cvmx_sli_pcie_msi_rcv_b3_s {
+ uint64_t reserved_32_63:32;
+ uint64_t intr:8;
+ uint64_t reserved_0_23:24;
+ } s;
+ struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
+ struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
+ struct cvmx_sli_pcie_msi_rcv_b3_s cn63xxp1;
+ struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
+ struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
+ struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_cnts {
+ uint64_t u64;
+ struct cvmx_sli_pktx_cnts_s {
+ uint64_t reserved_54_63:10;
+ uint64_t timer:22;
+ uint64_t cnt:32;
+ } s;
+ struct cvmx_sli_pktx_cnts_s cn61xx;
+ struct cvmx_sli_pktx_cnts_s cn63xx;
+ struct cvmx_sli_pktx_cnts_s cn63xxp1;
+ struct cvmx_sli_pktx_cnts_s cn66xx;
+ struct cvmx_sli_pktx_cnts_s cn68xx;
+ struct cvmx_sli_pktx_cnts_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_in_bp {
+ uint64_t u64;
+ struct cvmx_sli_pktx_in_bp_s {
+ uint64_t wmark:32;
+ uint64_t cnt:32;
+ } s;
+ struct cvmx_sli_pktx_in_bp_s cn61xx;
+ struct cvmx_sli_pktx_in_bp_s cn63xx;
+ struct cvmx_sli_pktx_in_bp_s cn63xxp1;
+ struct cvmx_sli_pktx_in_bp_s cn66xx;
+};
+
+union cvmx_sli_pktx_instr_baddr {
+ uint64_t u64;
+ struct cvmx_sli_pktx_instr_baddr_s {
+ uint64_t addr:61;
+ uint64_t reserved_0_2:3;
+ } s;
+ struct cvmx_sli_pktx_instr_baddr_s cn61xx;
+ struct cvmx_sli_pktx_instr_baddr_s cn63xx;
+ struct cvmx_sli_pktx_instr_baddr_s cn63xxp1;
+ struct cvmx_sli_pktx_instr_baddr_s cn66xx;
+ struct cvmx_sli_pktx_instr_baddr_s cn68xx;
+ struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_instr_baoff_dbell {
+ uint64_t u64;
+ struct cvmx_sli_pktx_instr_baoff_dbell_s {
+ uint64_t aoff:32;
+ uint64_t dbell:32;
+ } s;
+ struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
+ struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
+ struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xxp1;
+ struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
+ struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
+ struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_instr_fifo_rsize {
+ uint64_t u64;
+ struct cvmx_sli_pktx_instr_fifo_rsize_s {
+ uint64_t max:9;
+ uint64_t rrp:9;
+ uint64_t wrp:9;
+ uint64_t fcnt:5;
+ uint64_t rsize:32;
+ } s;
+ struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
+ struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
+ struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xxp1;
+ struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
+ struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
+ struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_instr_header {
+ uint64_t u64;
+ struct cvmx_sli_pktx_instr_header_s {
+ uint64_t reserved_44_63:20;
+ uint64_t pbp:1;
+ uint64_t reserved_38_42:5;
+ uint64_t rparmode:2;
+ uint64_t reserved_35_35:1;
+ uint64_t rskp_len:7;
+ uint64_t rngrpext:2;
+ uint64_t rnqos:1;
+ uint64_t rngrp:1;
+ uint64_t rntt:1;
+ uint64_t rntag:1;
+ uint64_t use_ihdr:1;
+ uint64_t reserved_16_20:5;
+ uint64_t par_mode:2;
+ uint64_t reserved_13_13:1;
+ uint64_t skp_len:7;
+ uint64_t ngrpext:2;
+ uint64_t nqos:1;
+ uint64_t ngrp:1;
+ uint64_t ntt:1;
+ uint64_t ntag:1;
+ } s;
+ struct cvmx_sli_pktx_instr_header_cn61xx {
+ uint64_t reserved_44_63:20;
+ uint64_t pbp:1;
+ uint64_t reserved_38_42:5;
+ uint64_t rparmode:2;
+ uint64_t reserved_35_35:1;
+ uint64_t rskp_len:7;
+ uint64_t reserved_26_27:2;
+ uint64_t rnqos:1;
+ uint64_t rngrp:1;
+ uint64_t rntt:1;
+ uint64_t rntag:1;
+ uint64_t use_ihdr:1;
+ uint64_t reserved_16_20:5;
+ uint64_t par_mode:2;
+ uint64_t reserved_13_13:1;
+ uint64_t skp_len:7;
+ uint64_t reserved_4_5:2;
+ uint64_t nqos:1;
+ uint64_t ngrp:1;
+ uint64_t ntt:1;
+ uint64_t ntag:1;
+ } cn61xx;
+ struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
+ struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
+ struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
+ struct cvmx_sli_pktx_instr_header_s cn68xx;
+ struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
+};
+
+union cvmx_sli_pktx_out_size {
+ uint64_t u64;
+ struct cvmx_sli_pktx_out_size_s {
+ uint64_t reserved_23_63:41;
+ uint64_t isize:7;
+ uint64_t bsize:16;
+ } s;
+ struct cvmx_sli_pktx_out_size_s cn61xx;
+ struct cvmx_sli_pktx_out_size_s cn63xx;
+ struct cvmx_sli_pktx_out_size_s cn63xxp1;
+ struct cvmx_sli_pktx_out_size_s cn66xx;
+ struct cvmx_sli_pktx_out_size_s cn68xx;
+ struct cvmx_sli_pktx_out_size_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_slist_baddr {
+ uint64_t u64;
+ struct cvmx_sli_pktx_slist_baddr_s {
+ uint64_t addr:60;
+ uint64_t reserved_0_3:4;
+ } s;
+ struct cvmx_sli_pktx_slist_baddr_s cn61xx;
+ struct cvmx_sli_pktx_slist_baddr_s cn63xx;
+ struct cvmx_sli_pktx_slist_baddr_s cn63xxp1;
+ struct cvmx_sli_pktx_slist_baddr_s cn66xx;
+ struct cvmx_sli_pktx_slist_baddr_s cn68xx;
+ struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_slist_baoff_dbell {
+ uint64_t u64;
+ struct cvmx_sli_pktx_slist_baoff_dbell_s {
+ uint64_t aoff:32;
+ uint64_t dbell:32;
+ } s;
+ struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
+ struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
+ struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xxp1;
+ struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
+ struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
+ struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
+};
+
+union cvmx_sli_pktx_slist_fifo_rsize {
+ uint64_t u64;
+ struct cvmx_sli_pktx_slist_fifo_rsize_s {
+ uint64_t reserved_32_63:32;
+ uint64_t rsize:32;
+ } s;
+ struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
+ struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
+ struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xxp1;
+ struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
+ struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
+ struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_cnt_int {
+ uint64_t u64;
+ struct cvmx_sli_pkt_cnt_int_s {
+ uint64_t reserved_32_63:32;
+ uint64_t port:32;
+ } s;
+ struct cvmx_sli_pkt_cnt_int_s cn61xx;
+ struct cvmx_sli_pkt_cnt_int_s cn63xx;
+ struct cvmx_sli_pkt_cnt_int_s cn63xxp1;
+ struct cvmx_sli_pkt_cnt_int_s cn66xx;
+ struct cvmx_sli_pkt_cnt_int_s cn68xx;
+ struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_cnt_int_enb {
+ uint64_t u64;
+ struct cvmx_sli_pkt_cnt_int_enb_s {
+ uint64_t reserved_32_63:32;
+ uint64_t port:32;
+ } s;
+ struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
+ struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
+ struct cvmx_sli_pkt_cnt_int_enb_s cn63xxp1;
+ struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
+ struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
+ struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_ctl {
+ uint64_t u64;
+ struct cvmx_sli_pkt_ctl_s {
+ uint64_t reserved_5_63:59;
+ uint64_t ring_en:1;
+ uint64_t pkt_bp:4;
+ } s;
+ struct cvmx_sli_pkt_ctl_s cn61xx;
+ struct cvmx_sli_pkt_ctl_s cn63xx;
+ struct cvmx_sli_pkt_ctl_s cn63xxp1;
+ struct cvmx_sli_pkt_ctl_s cn66xx;
+ struct cvmx_sli_pkt_ctl_s cn68xx;
+ struct cvmx_sli_pkt_ctl_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_data_out_es {
+ uint64_t u64;
+ struct cvmx_sli_pkt_data_out_es_s {
+ uint64_t es:64;
+ } s;
+ struct cvmx_sli_pkt_data_out_es_s cn61xx;
+ struct cvmx_sli_pkt_data_out_es_s cn63xx;
+ struct cvmx_sli_pkt_data_out_es_s cn63xxp1;
+ struct cvmx_sli_pkt_data_out_es_s cn66xx;
+ struct cvmx_sli_pkt_data_out_es_s cn68xx;
+ struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_data_out_ns {
+ uint64_t u64;
+ struct cvmx_sli_pkt_data_out_ns_s {
+ uint64_t reserved_32_63:32;
+ uint64_t nsr:32;
+ } s;
+ struct cvmx_sli_pkt_data_out_ns_s cn61xx;
+ struct cvmx_sli_pkt_data_out_ns_s cn63xx;
+ struct cvmx_sli_pkt_data_out_ns_s cn63xxp1;
+ struct cvmx_sli_pkt_data_out_ns_s cn66xx;
+ struct cvmx_sli_pkt_data_out_ns_s cn68xx;
+ struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_data_out_ror {
+ uint64_t u64;
+ struct cvmx_sli_pkt_data_out_ror_s {
+ uint64_t reserved_32_63:32;
+ uint64_t ror:32;
+ } s;
+ struct cvmx_sli_pkt_data_out_ror_s cn61xx;
+ struct cvmx_sli_pkt_data_out_ror_s cn63xx;
+ struct cvmx_sli_pkt_data_out_ror_s cn63xxp1;
+ struct cvmx_sli_pkt_data_out_ror_s cn66xx;
+ struct cvmx_sli_pkt_data_out_ror_s cn68xx;
+ struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_dpaddr {
+ uint64_t u64;
+ struct cvmx_sli_pkt_dpaddr_s {
+ uint64_t reserved_32_63:32;
+ uint64_t dptr:32;
+ } s;
+ struct cvmx_sli_pkt_dpaddr_s cn61xx;
+ struct cvmx_sli_pkt_dpaddr_s cn63xx;
+ struct cvmx_sli_pkt_dpaddr_s cn63xxp1;
+ struct cvmx_sli_pkt_dpaddr_s cn66xx;
+ struct cvmx_sli_pkt_dpaddr_s cn68xx;
+ struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_in_bp {
+ uint64_t u64;
+ struct cvmx_sli_pkt_in_bp_s {
+ uint64_t reserved_32_63:32;
+ uint64_t bp:32;
+ } s;
+ struct cvmx_sli_pkt_in_bp_s cn61xx;
+ struct cvmx_sli_pkt_in_bp_s cn63xx;
+ struct cvmx_sli_pkt_in_bp_s cn63xxp1;
+ struct cvmx_sli_pkt_in_bp_s cn66xx;
+};
+
+union cvmx_sli_pkt_in_donex_cnts {
+ uint64_t u64;
+ struct cvmx_sli_pkt_in_donex_cnts_s {
+ uint64_t reserved_32_63:32;
+ uint64_t cnt:32;
+ } s;
+ struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
+ struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
+ struct cvmx_sli_pkt_in_donex_cnts_s cn63xxp1;
+ struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
+ struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
+ struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_in_instr_counts {
+ uint64_t u64;
+ struct cvmx_sli_pkt_in_instr_counts_s {
+ uint64_t wr_cnt:32;
+ uint64_t rd_cnt:32;
+ } s;
+ struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
+ struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
+ struct cvmx_sli_pkt_in_instr_counts_s cn63xxp1;
+ struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
+ struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
+ struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_in_pcie_port {
+ uint64_t u64;
+ struct cvmx_sli_pkt_in_pcie_port_s {
+ uint64_t pp:64;
+ } s;
+ struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
+ struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
+ struct cvmx_sli_pkt_in_pcie_port_s cn63xxp1;
+ struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
+ struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
+ struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_input_control {
+ uint64_t u64;
+ struct cvmx_sli_pkt_input_control_s {
+ uint64_t prd_erst:1;
+ uint64_t prd_rds:7;
+ uint64_t gii_erst:1;
+ uint64_t gii_rds:7;
+ uint64_t reserved_41_47:7;
+ uint64_t prc_idle:1;
+ uint64_t reserved_24_39:16;
+ uint64_t pin_rst:1;
+ uint64_t pkt_rr:1;
+ uint64_t pbp_dhi:13;
+ uint64_t d_nsr:1;
+ uint64_t d_esr:2;
+ uint64_t d_ror:1;
+ uint64_t use_csr:1;
+ uint64_t nsr:1;
+ uint64_t esr:2;
+ uint64_t ror:1;
+ } s;
+ struct cvmx_sli_pkt_input_control_s cn61xx;
+ struct cvmx_sli_pkt_input_control_cn63xx {
+ uint64_t reserved_23_63:41;
+ uint64_t pkt_rr:1;
+ uint64_t pbp_dhi:13;
+ uint64_t d_nsr:1;
+ uint64_t d_esr:2;
+ uint64_t d_ror:1;
+ uint64_t use_csr:1;
+ uint64_t nsr:1;
+ uint64_t esr:2;
+ uint64_t ror:1;
+ } cn63xx;
+ struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
+ struct cvmx_sli_pkt_input_control_s cn66xx;
+ struct cvmx_sli_pkt_input_control_s cn68xx;
+ struct cvmx_sli_pkt_input_control_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_instr_enb {
+ uint64_t u64;
+ struct cvmx_sli_pkt_instr_enb_s {
+ uint64_t reserved_32_63:32;
+ uint64_t enb:32;
+ } s;
+ struct cvmx_sli_pkt_instr_enb_s cn61xx;
+ struct cvmx_sli_pkt_instr_enb_s cn63xx;
+ struct cvmx_sli_pkt_instr_enb_s cn63xxp1;
+ struct cvmx_sli_pkt_instr_enb_s cn66xx;
+ struct cvmx_sli_pkt_instr_enb_s cn68xx;
+ struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_instr_rd_size {
+ uint64_t u64;
+ struct cvmx_sli_pkt_instr_rd_size_s {
+ uint64_t rdsize:64;
+ } s;
+ struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
+ struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
+ struct cvmx_sli_pkt_instr_rd_size_s cn63xxp1;
+ struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
+ struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
+ struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_instr_size {
+ uint64_t u64;
+ struct cvmx_sli_pkt_instr_size_s {
+ uint64_t reserved_32_63:32;
+ uint64_t is_64b:32;
+ } s;
+ struct cvmx_sli_pkt_instr_size_s cn61xx;
+ struct cvmx_sli_pkt_instr_size_s cn63xx;
+ struct cvmx_sli_pkt_instr_size_s cn63xxp1;
+ struct cvmx_sli_pkt_instr_size_s cn66xx;
+ struct cvmx_sli_pkt_instr_size_s cn68xx;
+ struct cvmx_sli_pkt_instr_size_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_int_levels {
+ uint64_t u64;
+ struct cvmx_sli_pkt_int_levels_s {
+ uint64_t reserved_54_63:10;
+ uint64_t time:22;
+ uint64_t cnt:32;
+ } s;
+ struct cvmx_sli_pkt_int_levels_s cn61xx;
+ struct cvmx_sli_pkt_int_levels_s cn63xx;
+ struct cvmx_sli_pkt_int_levels_s cn63xxp1;
+ struct cvmx_sli_pkt_int_levels_s cn66xx;
+ struct cvmx_sli_pkt_int_levels_s cn68xx;
+ struct cvmx_sli_pkt_int_levels_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_iptr {
+ uint64_t u64;
+ struct cvmx_sli_pkt_iptr_s {
+ uint64_t reserved_32_63:32;
+ uint64_t iptr:32;
+ } s;
+ struct cvmx_sli_pkt_iptr_s cn61xx;
+ struct cvmx_sli_pkt_iptr_s cn63xx;
+ struct cvmx_sli_pkt_iptr_s cn63xxp1;
+ struct cvmx_sli_pkt_iptr_s cn66xx;
+ struct cvmx_sli_pkt_iptr_s cn68xx;
+ struct cvmx_sli_pkt_iptr_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_out_bmode {
+ uint64_t u64;
+ struct cvmx_sli_pkt_out_bmode_s {
+ uint64_t reserved_32_63:32;
+ uint64_t bmode:32;
+ } s;
+ struct cvmx_sli_pkt_out_bmode_s cn61xx;
+ struct cvmx_sli_pkt_out_bmode_s cn63xx;
+ struct cvmx_sli_pkt_out_bmode_s cn63xxp1;
+ struct cvmx_sli_pkt_out_bmode_s cn66xx;
+ struct cvmx_sli_pkt_out_bmode_s cn68xx;
+ struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_out_bp_en {
+ uint64_t u64;
+ struct cvmx_sli_pkt_out_bp_en_s {
+ uint64_t reserved_32_63:32;
+ uint64_t bp_en:32;
+ } s;
+ struct cvmx_sli_pkt_out_bp_en_s cn68xx;
+ struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_out_enb {
+ uint64_t u64;
+ struct cvmx_sli_pkt_out_enb_s {
+ uint64_t reserved_32_63:32;
+ uint64_t enb:32;
+ } s;
+ struct cvmx_sli_pkt_out_enb_s cn61xx;
+ struct cvmx_sli_pkt_out_enb_s cn63xx;
+ struct cvmx_sli_pkt_out_enb_s cn63xxp1;
+ struct cvmx_sli_pkt_out_enb_s cn66xx;
+ struct cvmx_sli_pkt_out_enb_s cn68xx;
+ struct cvmx_sli_pkt_out_enb_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_output_wmark {
+ uint64_t u64;
+ struct cvmx_sli_pkt_output_wmark_s {
+ uint64_t reserved_32_63:32;
+ uint64_t wmark:32;
+ } s;
+ struct cvmx_sli_pkt_output_wmark_s cn61xx;
+ struct cvmx_sli_pkt_output_wmark_s cn63xx;
+ struct cvmx_sli_pkt_output_wmark_s cn63xxp1;
+ struct cvmx_sli_pkt_output_wmark_s cn66xx;
+ struct cvmx_sli_pkt_output_wmark_s cn68xx;
+ struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_pcie_port {
+ uint64_t u64;
+ struct cvmx_sli_pkt_pcie_port_s {
+ uint64_t pp:64;
+ } s;
+ struct cvmx_sli_pkt_pcie_port_s cn61xx;
+ struct cvmx_sli_pkt_pcie_port_s cn63xx;
+ struct cvmx_sli_pkt_pcie_port_s cn63xxp1;
+ struct cvmx_sli_pkt_pcie_port_s cn66xx;
+ struct cvmx_sli_pkt_pcie_port_s cn68xx;
+ struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_port_in_rst {
+ uint64_t u64;
+ struct cvmx_sli_pkt_port_in_rst_s {
+ uint64_t in_rst:32;
+ uint64_t out_rst:32;
+ } s;
+ struct cvmx_sli_pkt_port_in_rst_s cn61xx;
+ struct cvmx_sli_pkt_port_in_rst_s cn63xx;
+ struct cvmx_sli_pkt_port_in_rst_s cn63xxp1;
+ struct cvmx_sli_pkt_port_in_rst_s cn66xx;
+ struct cvmx_sli_pkt_port_in_rst_s cn68xx;
+ struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_slist_es {
+ uint64_t u64;
+ struct cvmx_sli_pkt_slist_es_s {
+ uint64_t es:64;
+ } s;
+ struct cvmx_sli_pkt_slist_es_s cn61xx;
+ struct cvmx_sli_pkt_slist_es_s cn63xx;
+ struct cvmx_sli_pkt_slist_es_s cn63xxp1;
+ struct cvmx_sli_pkt_slist_es_s cn66xx;
+ struct cvmx_sli_pkt_slist_es_s cn68xx;
+ struct cvmx_sli_pkt_slist_es_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_slist_ns {
+ uint64_t u64;
+ struct cvmx_sli_pkt_slist_ns_s {
+ uint64_t reserved_32_63:32;
+ uint64_t nsr:32;
+ } s;
+ struct cvmx_sli_pkt_slist_ns_s cn61xx;
+ struct cvmx_sli_pkt_slist_ns_s cn63xx;
+ struct cvmx_sli_pkt_slist_ns_s cn63xxp1;
+ struct cvmx_sli_pkt_slist_ns_s cn66xx;
+ struct cvmx_sli_pkt_slist_ns_s cn68xx;
+ struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_slist_ror {
+ uint64_t u64;
+ struct cvmx_sli_pkt_slist_ror_s {
+ uint64_t reserved_32_63:32;
+ uint64_t ror:32;
+ } s;
+ struct cvmx_sli_pkt_slist_ror_s cn61xx;
+ struct cvmx_sli_pkt_slist_ror_s cn63xx;
+ struct cvmx_sli_pkt_slist_ror_s cn63xxp1;
+ struct cvmx_sli_pkt_slist_ror_s cn66xx;
+ struct cvmx_sli_pkt_slist_ror_s cn68xx;
+ struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_time_int {
+ uint64_t u64;
+ struct cvmx_sli_pkt_time_int_s {
+ uint64_t reserved_32_63:32;
+ uint64_t port:32;
+ } s;
+ struct cvmx_sli_pkt_time_int_s cn61xx;
+ struct cvmx_sli_pkt_time_int_s cn63xx;
+ struct cvmx_sli_pkt_time_int_s cn63xxp1;
+ struct cvmx_sli_pkt_time_int_s cn66xx;
+ struct cvmx_sli_pkt_time_int_s cn68xx;
+ struct cvmx_sli_pkt_time_int_s cn68xxp1;
+};
+
+union cvmx_sli_pkt_time_int_enb {
+ uint64_t u64;
+ struct cvmx_sli_pkt_time_int_enb_s {
+ uint64_t reserved_32_63:32;
+ uint64_t port:32;
+ } s;
+ struct cvmx_sli_pkt_time_int_enb_s cn61xx;
+ struct cvmx_sli_pkt_time_int_enb_s cn63xx;
+ struct cvmx_sli_pkt_time_int_enb_s cn63xxp1;
+ struct cvmx_sli_pkt_time_int_enb_s cn66xx;
+ struct cvmx_sli_pkt_time_int_enb_s cn68xx;
+ struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
+};
+
+union cvmx_sli_portx_pkind {
+ uint64_t u64;
+ struct cvmx_sli_portx_pkind_s {
+ uint64_t reserved_25_63:39;
+ uint64_t rpk_enb:1;
+ uint64_t reserved_22_23:2;
+ uint64_t pkindr:6;
+ uint64_t reserved_14_15:2;
+ uint64_t bpkind:6;
+ uint64_t reserved_6_7:2;
+ uint64_t pkind:6;
+ } s;
+ struct cvmx_sli_portx_pkind_s cn68xx;
+ struct cvmx_sli_portx_pkind_cn68xxp1 {
+ uint64_t reserved_14_63:50;
+ uint64_t bpkind:6;
+ uint64_t reserved_6_7:2;
+ uint64_t pkind:6;
+ } cn68xxp1;
+};
+
+union cvmx_sli_s2m_portx_ctl {
+ uint64_t u64;
+ struct cvmx_sli_s2m_portx_ctl_s {
+ uint64_t reserved_5_63:59;
+ uint64_t wind_d:1;
+ uint64_t bar0_d:1;
+ uint64_t mrrs:3;
+ } s;
+ struct cvmx_sli_s2m_portx_ctl_s cn61xx;
+ struct cvmx_sli_s2m_portx_ctl_s cn63xx;
+ struct cvmx_sli_s2m_portx_ctl_s cn63xxp1;
+ struct cvmx_sli_s2m_portx_ctl_s cn66xx;
+ struct cvmx_sli_s2m_portx_ctl_s cn68xx;
+ struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
+};
+
+union cvmx_sli_scratch_1 {
+ uint64_t u64;
+ struct cvmx_sli_scratch_1_s {
+ uint64_t data:64;
+ } s;
+ struct cvmx_sli_scratch_1_s cn61xx;
+ struct cvmx_sli_scratch_1_s cn63xx;
+ struct cvmx_sli_scratch_1_s cn63xxp1;
+ struct cvmx_sli_scratch_1_s cn66xx;
+ struct cvmx_sli_scratch_1_s cn68xx;
+ struct cvmx_sli_scratch_1_s cn68xxp1;
+};
+
+union cvmx_sli_scratch_2 {
+ uint64_t u64;
+ struct cvmx_sli_scratch_2_s {
+ uint64_t data:64;
+ } s;
+ struct cvmx_sli_scratch_2_s cn61xx;
+ struct cvmx_sli_scratch_2_s cn63xx;
+ struct cvmx_sli_scratch_2_s cn63xxp1;
+ struct cvmx_sli_scratch_2_s cn66xx;
+ struct cvmx_sli_scratch_2_s cn68xx;
+ struct cvmx_sli_scratch_2_s cn68xxp1;
+};
+
+union cvmx_sli_state1 {
+ uint64_t u64;
+ struct cvmx_sli_state1_s {
+ uint64_t cpl1:12;
+ uint64_t cpl0:12;
+ uint64_t arb:1;
+ uint64_t csr:39;
+ } s;
+ struct cvmx_sli_state1_s cn61xx;
+ struct cvmx_sli_state1_s cn63xx;
+ struct cvmx_sli_state1_s cn63xxp1;
+ struct cvmx_sli_state1_s cn66xx;
+ struct cvmx_sli_state1_s cn68xx;
+ struct cvmx_sli_state1_s cn68xxp1;
+};
+
+union cvmx_sli_state2 {
+ uint64_t u64;
+ struct cvmx_sli_state2_s {
+ uint64_t reserved_56_63:8;
+ uint64_t nnp1:8;
+ uint64_t reserved_47_47:1;
+ uint64_t rac:1;
+ uint64_t csm1:15;
+ uint64_t csm0:15;
+ uint64_t nnp0:8;
+ uint64_t nnd:8;
+ } s;
+ struct cvmx_sli_state2_s cn61xx;
+ struct cvmx_sli_state2_s cn63xx;
+ struct cvmx_sli_state2_s cn63xxp1;
+ struct cvmx_sli_state2_s cn66xx;
+ struct cvmx_sli_state2_s cn68xx;
+ struct cvmx_sli_state2_s cn68xxp1;
+};
+
+union cvmx_sli_state3 {
+ uint64_t u64;
+ struct cvmx_sli_state3_s {
+ uint64_t reserved_56_63:8;
+ uint64_t psm1:15;
+ uint64_t psm0:15;
+ uint64_t nsm1:13;
+ uint64_t nsm0:13;
+ } s;
+ struct cvmx_sli_state3_s cn61xx;
+ struct cvmx_sli_state3_s cn63xx;
+ struct cvmx_sli_state3_s cn63xxp1;
+ struct cvmx_sli_state3_s cn66xx;
+ struct cvmx_sli_state3_s cn68xx;
+ struct cvmx_sli_state3_s cn68xxp1;
+};
+
+union cvmx_sli_tx_pipe {
+ uint64_t u64;
+ struct cvmx_sli_tx_pipe_s {
+ uint64_t reserved_24_63:40;
+ uint64_t nump:8;
+ uint64_t reserved_7_15:9;
+ uint64_t base:7;
+ } s;
+ struct cvmx_sli_tx_pipe_s cn68xx;
+ struct cvmx_sli_tx_pipe_s cn68xxp1;
+};
+
+union cvmx_sli_win_rd_addr {
+ uint64_t u64;
+ struct cvmx_sli_win_rd_addr_s {
+ uint64_t reserved_51_63:13;
+ uint64_t ld_cmd:2;
+ uint64_t iobit:1;
+ uint64_t rd_addr:48;
+ } s;
+ struct cvmx_sli_win_rd_addr_s cn61xx;
+ struct cvmx_sli_win_rd_addr_s cn63xx;
+ struct cvmx_sli_win_rd_addr_s cn63xxp1;
+ struct cvmx_sli_win_rd_addr_s cn66xx;
+ struct cvmx_sli_win_rd_addr_s cn68xx;
+ struct cvmx_sli_win_rd_addr_s cn68xxp1;
+};
+
+union cvmx_sli_win_rd_data {
+ uint64_t u64;
+ struct cvmx_sli_win_rd_data_s {
+ uint64_t rd_data:64;
+ } s;
+ struct cvmx_sli_win_rd_data_s cn61xx;
+ struct cvmx_sli_win_rd_data_s cn63xx;
+ struct cvmx_sli_win_rd_data_s cn63xxp1;
+ struct cvmx_sli_win_rd_data_s cn66xx;
+ struct cvmx_sli_win_rd_data_s cn68xx;
+ struct cvmx_sli_win_rd_data_s cn68xxp1;
+};
+
+union cvmx_sli_win_wr_addr {
+ uint64_t u64;
+ struct cvmx_sli_win_wr_addr_s {
+ uint64_t reserved_49_63:15;
+ uint64_t iobit:1;
+ uint64_t wr_addr:45;
+ uint64_t reserved_0_2:3;
+ } s;
+ struct cvmx_sli_win_wr_addr_s cn61xx;
+ struct cvmx_sli_win_wr_addr_s cn63xx;
+ struct cvmx_sli_win_wr_addr_s cn63xxp1;
+ struct cvmx_sli_win_wr_addr_s cn66xx;
+ struct cvmx_sli_win_wr_addr_s cn68xx;
+ struct cvmx_sli_win_wr_addr_s cn68xxp1;
+};
+
+union cvmx_sli_win_wr_data {
+ uint64_t u64;
+ struct cvmx_sli_win_wr_data_s {
+ uint64_t wr_data:64;
+ } s;
+ struct cvmx_sli_win_wr_data_s cn61xx;
+ struct cvmx_sli_win_wr_data_s cn63xx;
+ struct cvmx_sli_win_wr_data_s cn63xxp1;
+ struct cvmx_sli_win_wr_data_s cn66xx;
+ struct cvmx_sli_win_wr_data_s cn68xx;
+ struct cvmx_sli_win_wr_data_s cn68xxp1;
+};
+
+union cvmx_sli_win_wr_mask {
+ uint64_t u64;
+ struct cvmx_sli_win_wr_mask_s {
+ uint64_t reserved_8_63:56;
+ uint64_t wr_mask:8;
+ } s;
+ struct cvmx_sli_win_wr_mask_s cn61xx;
+ struct cvmx_sli_win_wr_mask_s cn63xx;
+ struct cvmx_sli_win_wr_mask_s cn63xxp1;
+ struct cvmx_sli_win_wr_mask_s cn66xx;
+ struct cvmx_sli_win_wr_mask_s cn68xx;
+ struct cvmx_sli_win_wr_mask_s cn68xxp1;
+};
+
+union cvmx_sli_window_ctl {
+ uint64_t u64;
+ struct cvmx_sli_window_ctl_s {
+ uint64_t reserved_32_63:32;
+ uint64_t time:32;
+ } s;
+ struct cvmx_sli_window_ctl_s cn61xx;
+ struct cvmx_sli_window_ctl_s cn63xx;
+ struct cvmx_sli_window_ctl_s cn63xxp1;
+ struct cvmx_sli_window_ctl_s cn66xx;
+ struct cvmx_sli_window_ctl_s cn68xx;
+ struct cvmx_sli_window_ctl_s cn68xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-sriox-defs.h b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
new file mode 100644
index 0000000..7be7e9e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sriox-defs.h
@@ -0,0 +1,1036 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2011 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT. See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SRIOX_DEFS_H__
+#define __CVMX_SRIOX_DEFS_H__
+
+#define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
+#define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
+#define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
+#define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
+
+union cvmx_sriox_acc_ctrl {
+ uint64_t u64;
+ struct cvmx_sriox_acc_ctrl_s {
+ uint64_t reserved_7_63:57;
+ uint64_t deny_adr2:1;
+ uint64_t deny_adr1:1;
+ uint64_t deny_adr0:1;
+ uint64_t reserved_3_3:1;
+ uint64_t deny_bar2:1;
+ uint64_t deny_bar1:1;
+ uint64_t deny_bar0:1;
+ } s;
+ struct cvmx_sriox_acc_ctrl_cn63xx {
+ uint64_t reserved_3_63:61;
+ uint64_t deny_bar2:1;
+ uint64_t deny_bar1:1;
+ uint64_t deny_bar0:1;
+ } cn63xx;
+ struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
+ struct cvmx_sriox_acc_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_asmbly_id {
+ uint64_t u64;
+ struct cvmx_sriox_asmbly_id_s {
+ uint64_t reserved_32_63:32;
+ uint64_t assy_id:16;
+ uint64_t assy_ven:16;
+ } s;
+ struct cvmx_sriox_asmbly_id_s cn63xx;
+ struct cvmx_sriox_asmbly_id_s cn63xxp1;
+ struct cvmx_sriox_asmbly_id_s cn66xx;
+};
+
+union cvmx_sriox_asmbly_info {
+ uint64_t u64;
+ struct cvmx_sriox_asmbly_info_s {
+ uint64_t reserved_32_63:32;
+ uint64_t assy_rev:16;
+ uint64_t reserved_0_15:16;
+ } s;
+ struct cvmx_sriox_asmbly_info_s cn63xx;
+ struct cvmx_sriox_asmbly_info_s cn63xxp1;
+ struct cvmx_sriox_asmbly_info_s cn66xx;
+};
+
+union cvmx_sriox_bell_resp_ctrl {
+ uint64_t u64;
+ struct cvmx_sriox_bell_resp_ctrl_s {
+ uint64_t reserved_6_63:58;
+ uint64_t rp1_sid:1;
+ uint64_t rp0_sid:2;
+ uint64_t rp1_pid:1;
+ uint64_t rp0_pid:2;
+ } s;
+ struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
+ struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
+ struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_bist_status {
+ uint64_t u64;
+ struct cvmx_sriox_bist_status_s {
+ uint64_t reserved_45_63:19;
+ uint64_t lram:1;
+ uint64_t mram:2;
+ uint64_t cram:2;
+ uint64_t bell:2;
+ uint64_t otag:2;
+ uint64_t itag:1;
+ uint64_t ofree:1;
+ uint64_t rtn:2;
+ uint64_t obulk:4;
+ uint64_t optrs:4;
+ uint64_t oarb2:2;
+ uint64_t rxbuf2:2;
+ uint64_t oarb:2;
+ uint64_t ispf:1;
+ uint64_t ospf:1;
+ uint64_t txbuf:2;
+ uint64_t rxbuf:2;
+ uint64_t imsg:5;
+ uint64_t omsg:7;
+ } s;
+ struct cvmx_sriox_bist_status_cn63xx {
+ uint64_t reserved_44_63:20;
+ uint64_t mram:2;
+ uint64_t cram:2;
+ uint64_t bell:2;
+ uint64_t otag:2;
+ uint64_t itag:1;
+ uint64_t ofree:1;
+ uint64_t rtn:2;
+ uint64_t obulk:4;
+ uint64_t optrs:4;
+ uint64_t oarb2:2;
+ uint64_t rxbuf2:2;
+ uint64_t oarb:2;
+ uint64_t ispf:1;
+ uint64_t ospf:1;
+ uint64_t txbuf:2;
+ uint64_t rxbuf:2;
+ uint64_t imsg:5;
+ uint64_t omsg:7;
+ } cn63xx;
+ struct cvmx_sriox_bist_status_cn63xxp1 {
+ uint64_t reserved_44_63:20;
+ uint64_t mram:2;
+ uint64_t cram:2;
+ uint64_t bell:2;
+ uint64_t otag:2;
+ uint64_t itag:1;
+ uint64_t ofree:1;
+ uint64_t rtn:2;
+ uint64_t obulk:4;
+ uint64_t optrs:4;
+ uint64_t reserved_20_23:4;
+ uint64_t oarb:2;
+ uint64_t ispf:1;
+ uint64_t ospf:1;
+ uint64_t txbuf:2;
+ uint64_t rxbuf:2;
+ uint64_t imsg:5;
+ uint64_t omsg:7;
+ } cn63xxp1;
+ struct cvmx_sriox_bist_status_s cn66xx;
+};
+
+union cvmx_sriox_imsg_ctrl {
+ uint64_t u64;
+ struct cvmx_sriox_imsg_ctrl_s {
+ uint64_t reserved_32_63:32;
+ uint64_t to_mode:1;
+ uint64_t reserved_30_30:1;
+ uint64_t rsp_thr:6;
+ uint64_t reserved_22_23:2;
+ uint64_t rp1_sid:1;
+ uint64_t rp0_sid:2;
+ uint64_t rp1_pid:1;
+ uint64_t rp0_pid:2;
+ uint64_t reserved_15_15:1;
+ uint64_t prt_sel:3;
+ uint64_t lttr:4;
+ uint64_t prio:4;
+ uint64_t mbox:4;
+ } s;
+ struct cvmx_sriox_imsg_ctrl_s cn63xx;
+ struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
+ struct cvmx_sriox_imsg_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_imsg_inst_hdrx {
+ uint64_t u64;
+ struct cvmx_sriox_imsg_inst_hdrx_s {
+ uint64_t r:1;
+ uint64_t reserved_58_62:5;
+ uint64_t pm:2;
+ uint64_t reserved_55_55:1;
+ uint64_t sl:7;
+ uint64_t reserved_46_47:2;
+ uint64_t nqos:1;
+ uint64_t ngrp:1;
+ uint64_t ntt:1;
+ uint64_t ntag:1;
+ uint64_t reserved_35_41:7;
+ uint64_t rs:1;
+ uint64_t tt:2;
+ uint64_t tag:32;
+ } s;
+ struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
+ struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
+ struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
+};
+
+union cvmx_sriox_imsg_qos_grpx {
+ uint64_t u64;
+ struct cvmx_sriox_imsg_qos_grpx_s {
+ uint64_t reserved_63_63:1;
+ uint64_t qos7:3;
+ uint64_t grp7:4;
+ uint64_t reserved_55_55:1;
+ uint64_t qos6:3;
+ uint64_t grp6:4;
+ uint64_t reserved_47_47:1;
+ uint64_t qos5:3;
+ uint64_t grp5:4;
+ uint64_t reserved_39_39:1;
+ uint64_t qos4:3;
+ uint64_t grp4:4;
+ uint64_t reserved_31_31:1;
+ uint64_t qos3:3;
+ uint64_t grp3:4;
+ uint64_t reserved_23_23:1;
+ uint64_t qos2:3;
+ uint64_t grp2:4;
+ uint64_t reserved_15_15:1;
+ uint64_t qos1:3;
+ uint64_t grp1:4;
+ uint64_t reserved_7_7:1;
+ uint64_t qos0:3;
+ uint64_t grp0:4;
+ } s;
+ struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
+ struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
+ struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
+};
+
+union cvmx_sriox_imsg_statusx {
+ uint64_t u64;
+ struct cvmx_sriox_imsg_statusx_s {
+ uint64_t val1:1;
+ uint64_t err1:1;
+ uint64_t toe1:1;
+ uint64_t toc1:1;
+ uint64_t prt1:1;
+ uint64_t reserved_58_58:1;
+ uint64_t tt1:1;
+ uint64_t dis1:1;
+ uint64_t seg1:4;
+ uint64_t mbox1:2;
+ uint64_t lttr1:2;
+ uint64_t sid1:16;
+ uint64_t val0:1;
+ uint64_t err0:1;
+ uint64_t toe0:1;
+ uint64_t toc0:1;
+ uint64_t prt0:1;
+ uint64_t reserved_26_26:1;
+ uint64_t tt0:1;
+ uint64_t dis0:1;
+ uint64_t seg0:4;
+ uint64_t mbox0:2;
+ uint64_t lttr0:2;
+ uint64_t sid0:16;
+ } s;
+ struct cvmx_sriox_imsg_statusx_s cn63xx;
+ struct cvmx_sriox_imsg_statusx_s cn63xxp1;
+ struct cvmx_sriox_imsg_statusx_s cn66xx;
+};
+
+union cvmx_sriox_imsg_vport_thr {
+ uint64_t u64;
+ struct cvmx_sriox_imsg_vport_thr_s {
+ uint64_t reserved_54_63:10;
+ uint64_t max_tot:6;
+ uint64_t reserved_46_47:2;
+ uint64_t max_s1:6;
+ uint64_t reserved_38_39:2;
+ uint64_t max_s0:6;
+ uint64_t sp_vport:1;
+ uint64_t reserved_20_30:11;
+ uint64_t buf_thr:4;
+ uint64_t reserved_14_15:2;
+ uint64_t max_p1:6;
+ uint64_t reserved_6_7:2;
+ uint64_t max_p0:6;
+ } s;
+ struct cvmx_sriox_imsg_vport_thr_s cn63xx;
+ struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
+ struct cvmx_sriox_imsg_vport_thr_s cn66xx;
+};
+
+union cvmx_sriox_imsg_vport_thr2 {
+ uint64_t u64;
+ struct cvmx_sriox_imsg_vport_thr2_s {
+ uint64_t reserved_46_63:18;
+ uint64_t max_s3:6;
+ uint64_t reserved_38_39:2;
+ uint64_t max_s2:6;
+ uint64_t reserved_0_31:32;
+ } s;
+ struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
+};
+
+union cvmx_sriox_int2_enable {
+ uint64_t u64;
+ struct cvmx_sriox_int2_enable_s {
+ uint64_t reserved_1_63:63;
+ uint64_t pko_rst:1;
+ } s;
+ struct cvmx_sriox_int2_enable_s cn63xx;
+ struct cvmx_sriox_int2_enable_s cn66xx;
+};
+
+union cvmx_sriox_int2_reg {
+ uint64_t u64;
+ struct cvmx_sriox_int2_reg_s {
+ uint64_t reserved_32_63:32;
+ uint64_t int_sum:1;
+ uint64_t reserved_1_30:30;
+ uint64_t pko_rst:1;
+ } s;
+ struct cvmx_sriox_int2_reg_s cn63xx;
+ struct cvmx_sriox_int2_reg_s cn66xx;
+};
+
+union cvmx_sriox_int_enable {
+ uint64_t u64;
+ struct cvmx_sriox_int_enable_s {
+ uint64_t reserved_27_63:37;
+ uint64_t zero_pkt:1;
+ uint64_t ttl_tout:1;
+ uint64_t fail:1;
+ uint64_t degrade:1;
+ uint64_t mac_buf:1;
+ uint64_t f_error:1;
+ uint64_t rtry_err:1;
+ uint64_t pko_err:1;
+ uint64_t omsg_err:1;
+ uint64_t omsg1:1;
+ uint64_t omsg0:1;
+ uint64_t link_up:1;
+ uint64_t link_dwn:1;
+ uint64_t phy_erb:1;
+ uint64_t log_erb:1;
+ uint64_t soft_rx:1;
+ uint64_t soft_tx:1;
+ uint64_t mce_rx:1;
+ uint64_t mce_tx:1;
+ uint64_t wr_done:1;
+ uint64_t sli_err:1;
+ uint64_t deny_wr:1;
+ uint64_t bar_err:1;
+ uint64_t maint_op:1;
+ uint64_t rxbell:1;
+ uint64_t bell_err:1;
+ uint64_t txbell:1;
+ } s;
+ struct cvmx_sriox_int_enable_s cn63xx;
+ struct cvmx_sriox_int_enable_cn63xxp1 {
+ uint64_t reserved_22_63:42;
+ uint64_t f_error:1;
+ uint64_t rtry_err:1;
+ uint64_t pko_err:1;
+ uint64_t omsg_err:1;
+ uint64_t omsg1:1;
+ uint64_t omsg0:1;
+ uint64_t link_up:1;
+ uint64_t link_dwn:1;
+ uint64_t phy_erb:1;
+ uint64_t log_erb:1;
+ uint64_t soft_rx:1;
+ uint64_t soft_tx:1;
+ uint64_t mce_rx:1;
+ uint64_t mce_tx:1;
+ uint64_t wr_done:1;
+ uint64_t sli_err:1;
+ uint64_t deny_wr:1;
+ uint64_t bar_err:1;
+ uint64_t maint_op:1;
+ uint64_t rxbell:1;
+ uint64_t bell_err:1;
+ uint64_t txbell:1;
+ } cn63xxp1;
+ struct cvmx_sriox_int_enable_s cn66xx;
+};
+
+union cvmx_sriox_int_info0 {
+ uint64_t u64;
+ struct cvmx_sriox_int_info0_s {
+ uint64_t cmd:4;
+ uint64_t type:4;
+ uint64_t tag:8;
+ uint64_t reserved_42_47:6;
+ uint64_t length:10;
+ uint64_t status:3;
+ uint64_t reserved_16_28:13;
+ uint64_t be0:8;
+ uint64_t be1:8;
+ } s;
+ struct cvmx_sriox_int_info0_s cn63xx;
+ struct cvmx_sriox_int_info0_s cn63xxp1;
+ struct cvmx_sriox_int_info0_s cn66xx;
+};
+
+union cvmx_sriox_int_info1 {
+ uint64_t u64;
+ struct cvmx_sriox_int_info1_s {
+ uint64_t info1:64;
+ } s;
+ struct cvmx_sriox_int_info1_s cn63xx;
+ struct cvmx_sriox_int_info1_s cn63xxp1;
+ struct cvmx_sriox_int_info1_s cn66xx;
+};
+
+union cvmx_sriox_int_info2 {
+ uint64_t u64;
+ struct cvmx_sriox_int_info2_s {
+ uint64_t prio:2;
+ uint64_t tt:1;
+ uint64_t sis:1;
+ uint64_t ssize:4;
+ uint64_t did:16;
+ uint64_t xmbox:4;
+ uint64_t mbox:2;
+ uint64_t letter:2;
+ uint64_t rsrvd:30;
+ uint64_t lns:1;
+ uint64_t intr:1;
+ } s;
+ struct cvmx_sriox_int_info2_s cn63xx;
+ struct cvmx_sriox_int_info2_s cn63xxp1;
+ struct cvmx_sriox_int_info2_s cn66xx;
+};
+
+union cvmx_sriox_int_info3 {
+ uint64_t u64;
+ struct cvmx_sriox_int_info3_s {
+ uint64_t prio:2;
+ uint64_t tt:2;
+ uint64_t type:4;
+ uint64_t other:48;
+ uint64_t reserved_0_7:8;
+ } s;
+ struct cvmx_sriox_int_info3_s cn63xx;
+ struct cvmx_sriox_int_info3_s cn63xxp1;
+ struct cvmx_sriox_int_info3_s cn66xx;
+};
+
+union cvmx_sriox_int_reg {
+ uint64_t u64;
+ struct cvmx_sriox_int_reg_s {
+ uint64_t reserved_32_63:32;
+ uint64_t int2_sum:1;
+ uint64_t reserved_27_30:4;
+ uint64_t zero_pkt:1;
+ uint64_t ttl_tout:1;
+ uint64_t fail:1;
+ uint64_t degrad:1;
+ uint64_t mac_buf:1;
+ uint64_t f_error:1;
+ uint64_t rtry_err:1;
+ uint64_t pko_err:1;
+ uint64_t omsg_err:1;
+ uint64_t omsg1:1;
+ uint64_t omsg0:1;
+ uint64_t link_up:1;
+ uint64_t link_dwn:1;
+ uint64_t phy_erb:1;
+ uint64_t log_erb:1;
+ uint64_t soft_rx:1;
+ uint64_t soft_tx:1;
+ uint64_t mce_rx:1;
+ uint64_t mce_tx:1;
+ uint64_t wr_done:1;
+ uint64_t sli_err:1;
+ uint64_t deny_wr:1;
+ uint64_t bar_err:1;
+ uint64_t maint_op:1;
+ uint64_t rxbell:1;
+ uint64_t bell_err:1;
+ uint64_t txbell:1;
+ } s;
+ struct cvmx_sriox_int_reg_s cn63xx;
+ struct cvmx_sriox_int_reg_cn63xxp1 {
+ uint64_t reserved_22_63:42;
+ uint64_t f_error:1;
+ uint64_t rtry_err:1;
+ uint64_t pko_err:1;
+ uint64_t omsg_err:1;
+ uint64_t omsg1:1;
+ uint64_t omsg0:1;
+ uint64_t link_up:1;
+ uint64_t link_dwn:1;
+ uint64_t phy_erb:1;
+ uint64_t log_erb:1;
+ uint64_t soft_rx:1;
+ uint64_t soft_tx:1;
+ uint64_t mce_rx:1;
+ uint64_t mce_tx:1;
+ uint64_t wr_done:1;
+ uint64_t sli_err:1;
+ uint64_t deny_wr:1;
+ uint64_t bar_err:1;
+ uint64_t maint_op:1;
+ uint64_t rxbell:1;
+ uint64_t bell_err:1;
+ uint64_t txbell:1;
+ } cn63xxp1;
+ struct cvmx_sriox_int_reg_s cn66xx;
+};
+
+union cvmx_sriox_ip_feature {
+ uint64_t u64;
+ struct cvmx_sriox_ip_feature_s {
+ uint64_t ops:32;
+ uint64_t reserved_15_31:17;
+ uint64_t no_vmin:1;
+ uint64_t a66:1;
+ uint64_t a50:1;
+ uint64_t reserved_11_11:1;
+ uint64_t tx_flow:1;
+ uint64_t pt_width:2;
+ uint64_t tx_pol:4;
+ uint64_t rx_pol:4;
+ } s;
+ struct cvmx_sriox_ip_feature_cn63xx {
+ uint64_t ops:32;
+ uint64_t reserved_14_31:18;
+ uint64_t a66:1;
+ uint64_t a50:1;
+ uint64_t reserved_11_11:1;
+ uint64_t tx_flow:1;
+ uint64_t pt_width:2;
+ uint64_t tx_pol:4;
+ uint64_t rx_pol:4;
+ } cn63xx;
+ struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
+ struct cvmx_sriox_ip_feature_s cn66xx;
+};
+
+union cvmx_sriox_mac_buffers {
+ uint64_t u64;
+ struct cvmx_sriox_mac_buffers_s {
+ uint64_t reserved_56_63:8;
+ uint64_t tx_enb:8;
+ uint64_t reserved_44_47:4;
+ uint64_t tx_inuse:4;
+ uint64_t tx_stat:8;
+ uint64_t reserved_24_31:8;
+ uint64_t rx_enb:8;
+ uint64_t reserved_12_15:4;
+ uint64_t rx_inuse:4;
+ uint64_t rx_stat:8;
+ } s;
+ struct cvmx_sriox_mac_buffers_s cn63xx;
+ struct cvmx_sriox_mac_buffers_s cn66xx;
+};
+
+union cvmx_sriox_maint_op {
+ uint64_t u64;
+ struct cvmx_sriox_maint_op_s {
+ uint64_t wr_data:32;
+ uint64_t reserved_27_31:5;
+ uint64_t fail:1;
+ uint64_t pending:1;
+ uint64_t op:1;
+ uint64_t addr:24;
+ } s;
+ struct cvmx_sriox_maint_op_s cn63xx;
+ struct cvmx_sriox_maint_op_s cn63xxp1;
+ struct cvmx_sriox_maint_op_s cn66xx;
+};
+
+union cvmx_sriox_maint_rd_data {
+ uint64_t u64;
+ struct cvmx_sriox_maint_rd_data_s {
+ uint64_t reserved_33_63:31;
+ uint64_t valid:1;
+ uint64_t rd_data:32;
+ } s;
+ struct cvmx_sriox_maint_rd_data_s cn63xx;
+ struct cvmx_sriox_maint_rd_data_s cn63xxp1;
+ struct cvmx_sriox_maint_rd_data_s cn66xx;
+};
+
+union cvmx_sriox_mce_tx_ctl {
+ uint64_t u64;
+ struct cvmx_sriox_mce_tx_ctl_s {
+ uint64_t reserved_1_63:63;
+ uint64_t mce:1;
+ } s;
+ struct cvmx_sriox_mce_tx_ctl_s cn63xx;
+ struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
+ struct cvmx_sriox_mce_tx_ctl_s cn66xx;
+};
+
+union cvmx_sriox_mem_op_ctrl {
+ uint64_t u64;
+ struct cvmx_sriox_mem_op_ctrl_s {
+ uint64_t reserved_10_63:54;
+ uint64_t rr_ro:1;
+ uint64_t w_ro:1;
+ uint64_t reserved_6_7:2;
+ uint64_t rp1_sid:1;
+ uint64_t rp0_sid:2;
+ uint64_t rp1_pid:1;
+ uint64_t rp0_pid:2;
+ } s;
+ struct cvmx_sriox_mem_op_ctrl_s cn63xx;
+ struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
+ struct cvmx_sriox_mem_op_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_omsg_ctrlx {
+ uint64_t u64;
+ struct cvmx_sriox_omsg_ctrlx_s {
+ uint64_t testmode:1;
+ uint64_t reserved_37_62:26;
+ uint64_t silo_max:5;
+ uint64_t rtry_thr:16;
+ uint64_t rtry_en:1;
+ uint64_t reserved_11_14:4;
+ uint64_t idm_tt:1;
+ uint64_t idm_sis:1;
+ uint64_t idm_did:1;
+ uint64_t lttr_sp:4;
+ uint64_t lttr_mp:4;
+ } s;
+ struct cvmx_sriox_omsg_ctrlx_s cn63xx;
+ struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
+ uint64_t testmode:1;
+ uint64_t reserved_32_62:31;
+ uint64_t rtry_thr:16;
+ uint64_t rtry_en:1;
+ uint64_t reserved_11_14:4;
+ uint64_t idm_tt:1;
+ uint64_t idm_sis:1;
+ uint64_t idm_did:1;
+ uint64_t lttr_sp:4;
+ uint64_t lttr_mp:4;
+ } cn63xxp1;
+ struct cvmx_sriox_omsg_ctrlx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_done_countsx {
+ uint64_t u64;
+ struct cvmx_sriox_omsg_done_countsx_s {
+ uint64_t reserved_32_63:32;
+ uint64_t bad:16;
+ uint64_t good:16;
+ } s;
+ struct cvmx_sriox_omsg_done_countsx_s cn63xx;
+ struct cvmx_sriox_omsg_done_countsx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_fmp_mrx {
+ uint64_t u64;
+ struct cvmx_sriox_omsg_fmp_mrx_s {
+ uint64_t reserved_15_63:49;
+ uint64_t ctlr_sp:1;
+ uint64_t ctlr_fmp:1;
+ uint64_t ctlr_nmp:1;
+ uint64_t id_sp:1;
+ uint64_t id_fmp:1;
+ uint64_t id_nmp:1;
+ uint64_t id_psd:1;
+ uint64_t mbox_sp:1;
+ uint64_t mbox_fmp:1;
+ uint64_t mbox_nmp:1;
+ uint64_t mbox_psd:1;
+ uint64_t all_sp:1;
+ uint64_t all_fmp:1;
+ uint64_t all_nmp:1;
+ uint64_t all_psd:1;
+ } s;
+ struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
+ struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
+ struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_nmp_mrx {
+ uint64_t u64;
+ struct cvmx_sriox_omsg_nmp_mrx_s {
+ uint64_t reserved_15_63:49;
+ uint64_t ctlr_sp:1;
+ uint64_t ctlr_fmp:1;
+ uint64_t ctlr_nmp:1;
+ uint64_t id_sp:1;
+ uint64_t id_fmp:1;
+ uint64_t id_nmp:1;
+ uint64_t reserved_8_8:1;
+ uint64_t mbox_sp:1;
+ uint64_t mbox_fmp:1;
+ uint64_t mbox_nmp:1;
+ uint64_t reserved_4_4:1;
+ uint64_t all_sp:1;
+ uint64_t all_fmp:1;
+ uint64_t all_nmp:1;
+ uint64_t reserved_0_0:1;
+ } s;
+ struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
+ struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
+ struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_portx {
+ uint64_t u64;
+ struct cvmx_sriox_omsg_portx_s {
+ uint64_t reserved_32_63:32;
+ uint64_t enable:1;
+ uint64_t reserved_3_30:28;
+ uint64_t port:3;
+ } s;
+ struct cvmx_sriox_omsg_portx_cn63xx {
+ uint64_t reserved_32_63:32;
+ uint64_t enable:1;
+ uint64_t reserved_2_30:29;
+ uint64_t port:2;
+ } cn63xx;
+ struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
+ struct cvmx_sriox_omsg_portx_s cn66xx;
+};
+
+union cvmx_sriox_omsg_silo_thr {
+ uint64_t u64;
+ struct cvmx_sriox_omsg_silo_thr_s {
+ uint64_t reserved_5_63:59;
+ uint64_t tot_silo:5;
+ } s;
+ struct cvmx_sriox_omsg_silo_thr_s cn63xx;
+ struct cvmx_sriox_omsg_silo_thr_s cn66xx;
+};
+
+union cvmx_sriox_omsg_sp_mrx {
+ uint64_t u64;
+ struct cvmx_sriox_omsg_sp_mrx_s {
+ uint64_t reserved_16_63:48;
+ uint64_t xmbox_sp:1;
+ uint64_t ctlr_sp:1;
+ uint64_t ctlr_fmp:1;
+ uint64_t ctlr_nmp:1;
+ uint64_t id_sp:1;
+ uint64_t id_fmp:1;
+ uint64_t id_nmp:1;
+ uint64_t id_psd:1;
+ uint64_t mbox_sp:1;
+ uint64_t mbox_fmp:1;
+ uint64_t mbox_nmp:1;
+ uint64_t mbox_psd:1;
+ uint64_t all_sp:1;
+ uint64_t all_fmp:1;
+ uint64_t all_nmp:1;
+ uint64_t all_psd:1;
+ } s;
+ struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
+ struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
+ struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
+};
+
+union cvmx_sriox_priox_in_use {
+ uint64_t u64;
+ struct cvmx_sriox_priox_in_use_s {
+ uint64_t reserved_32_63:32;
+ uint64_t end_cnt:16;
+ uint64_t start_cnt:16;
+ } s;
+ struct cvmx_sriox_priox_in_use_s cn63xx;
+ struct cvmx_sriox_priox_in_use_s cn66xx;
+};
+
+union cvmx_sriox_rx_bell {
+ uint64_t u64;
+ struct cvmx_sriox_rx_bell_s {
+ uint64_t reserved_48_63:16;
+ uint64_t data:16;
+ uint64_t src_id:16;
+ uint64_t count:8;
+ uint64_t reserved_5_7:3;
+ uint64_t dest_id:1;
+ uint64_t id16:1;
+ uint64_t reserved_2_2:1;
+ uint64_t priority:2;
+ } s;
+ struct cvmx_sriox_rx_bell_s cn63xx;
+ struct cvmx_sriox_rx_bell_s cn63xxp1;
+ struct cvmx_sriox_rx_bell_s cn66xx;
+};
+
+union cvmx_sriox_rx_bell_seq {
+ uint64_t u64;
+ struct cvmx_sriox_rx_bell_seq_s {
+ uint64_t reserved_40_63:24;
+ uint64_t count:8;
+ uint64_t seq:32;
+ } s;
+ struct cvmx_sriox_rx_bell_seq_s cn63xx;
+ struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
+ struct cvmx_sriox_rx_bell_seq_s cn66xx;
+};
+
+union cvmx_sriox_rx_status {
+ uint64_t u64;
+ struct cvmx_sriox_rx_status_s {
+ uint64_t rtn_pr3:8;
+ uint64_t rtn_pr2:8;
+ uint64_t rtn_pr1:8;
+ uint64_t reserved_28_39:12;
+ uint64_t mbox:4;
+ uint64_t comp:8;
+ uint64_t reserved_13_15:3;
+ uint64_t n_post:5;
+ uint64_t post:8;
+ } s;
+ struct cvmx_sriox_rx_status_s cn63xx;
+ struct cvmx_sriox_rx_status_s cn63xxp1;
+ struct cvmx_sriox_rx_status_s cn66xx;
+};
+
+union cvmx_sriox_s2m_typex {
+ uint64_t u64;
+ struct cvmx_sriox_s2m_typex_s {
+ uint64_t reserved_19_63:45;
+ uint64_t wr_op:3;
+ uint64_t reserved_15_15:1;
+ uint64_t rd_op:3;
+ uint64_t wr_prior:2;
+ uint64_t rd_prior:2;
+ uint64_t reserved_6_7:2;
+ uint64_t src_id:1;
+ uint64_t id16:1;
+ uint64_t reserved_2_3:2;
+ uint64_t iaow_sel:2;
+ } s;
+ struct cvmx_sriox_s2m_typex_s cn63xx;
+ struct cvmx_sriox_s2m_typex_s cn63xxp1;
+ struct cvmx_sriox_s2m_typex_s cn66xx;
+};
+
+union cvmx_sriox_seq {
+ uint64_t u64;
+ struct cvmx_sriox_seq_s {
+ uint64_t reserved_32_63:32;
+ uint64_t seq:32;
+ } s;
+ struct cvmx_sriox_seq_s cn63xx;
+ struct cvmx_sriox_seq_s cn63xxp1;
+ struct cvmx_sriox_seq_s cn66xx;
+};
+
+union cvmx_sriox_status_reg {
+ uint64_t u64;
+ struct cvmx_sriox_status_reg_s {
+ uint64_t reserved_2_63:62;
+ uint64_t access:1;
+ uint64_t srio:1;
+ } s;
+ struct cvmx_sriox_status_reg_s cn63xx;
+ struct cvmx_sriox_status_reg_s cn63xxp1;
+ struct cvmx_sriox_status_reg_s cn66xx;
+};
+
+union cvmx_sriox_tag_ctrl {
+ uint64_t u64;
+ struct cvmx_sriox_tag_ctrl_s {
+ uint64_t reserved_17_63:47;
+ uint64_t o_clr:1;
+ uint64_t reserved_13_15:3;
+ uint64_t otag:5;
+ uint64_t reserved_5_7:3;
+ uint64_t itag:5;
+ } s;
+ struct cvmx_sriox_tag_ctrl_s cn63xx;
+ struct cvmx_sriox_tag_ctrl_s cn63xxp1;
+ struct cvmx_sriox_tag_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_tlp_credits {
+ uint64_t u64;
+ struct cvmx_sriox_tlp_credits_s {
+ uint64_t reserved_28_63:36;
+ uint64_t mbox:4;
+ uint64_t comp:8;
+ uint64_t reserved_13_15:3;
+ uint64_t n_post:5;
+ uint64_t post:8;
+ } s;
+ struct cvmx_sriox_tlp_credits_s cn63xx;
+ struct cvmx_sriox_tlp_credits_s cn63xxp1;
+ struct cvmx_sriox_tlp_credits_s cn66xx;
+};
+
+union cvmx_sriox_tx_bell {
+ uint64_t u64;
+ struct cvmx_sriox_tx_bell_s {
+ uint64_t reserved_48_63:16;
+ uint64_t data:16;
+ uint64_t dest_id:16;
+ uint64_t reserved_9_15:7;
+ uint64_t pending:1;
+ uint64_t reserved_5_7:3;
+ uint64_t src_id:1;
+ uint64_t id16:1;
+ uint64_t reserved_2_2:1;
+ uint64_t priority:2;
+ } s;
+ struct cvmx_sriox_tx_bell_s cn63xx;
+ struct cvmx_sriox_tx_bell_s cn63xxp1;
+ struct cvmx_sriox_tx_bell_s cn66xx;
+};
+
+union cvmx_sriox_tx_bell_info {
+ uint64_t u64;
+ struct cvmx_sriox_tx_bell_info_s {
+ uint64_t reserved_48_63:16;
+ uint64_t data:16;
+ uint64_t dest_id:16;
+ uint64_t reserved_8_15:8;
+ uint64_t timeout:1;
+ uint64_t error:1;
+ uint64_t retry:1;
+ uint64_t src_id:1;
+ uint64_t id16:1;
+ uint64_t reserved_2_2:1;
+ uint64_t priority:2;
+ } s;
+ struct cvmx_sriox_tx_bell_info_s cn63xx;
+ struct cvmx_sriox_tx_bell_info_s cn63xxp1;
+ struct cvmx_sriox_tx_bell_info_s cn66xx;
+};
+
+union cvmx_sriox_tx_ctrl {
+ uint64_t u64;
+ struct cvmx_sriox_tx_ctrl_s {
+ uint64_t reserved_53_63:11;
+ uint64_t tag_th2:5;
+ uint64_t reserved_45_47:3;
+ uint64_t tag_th1:5;
+ uint64_t reserved_37_39:3;
+ uint64_t tag_th0:5;
+ uint64_t reserved_20_31:12;
+ uint64_t tx_th2:4;
+ uint64_t reserved_12_15:4;
+ uint64_t tx_th1:4;
+ uint64_t reserved_4_7:4;
+ uint64_t tx_th0:4;
+ } s;
+ struct cvmx_sriox_tx_ctrl_s cn63xx;
+ struct cvmx_sriox_tx_ctrl_s cn63xxp1;
+ struct cvmx_sriox_tx_ctrl_s cn66xx;
+};
+
+union cvmx_sriox_tx_emphasis {
+ uint64_t u64;
+ struct cvmx_sriox_tx_emphasis_s {
+ uint64_t reserved_4_63:60;
+ uint64_t emph:4;
+ } s;
+ struct cvmx_sriox_tx_emphasis_s cn63xx;
+ struct cvmx_sriox_tx_emphasis_s cn66xx;
+};
+
+union cvmx_sriox_tx_status {
+ uint64_t u64;
+ struct cvmx_sriox_tx_status_s {
+ uint64_t reserved_32_63:32;
+ uint64_t s2m_pr3:8;
+ uint64_t s2m_pr2:8;
+ uint64_t s2m_pr1:8;
+ uint64_t s2m_pr0:8;
+ } s;
+ struct cvmx_sriox_tx_status_s cn63xx;
+ struct cvmx_sriox_tx_status_s cn63xxp1;
+ struct cvmx_sriox_tx_status_s cn66xx;
+};
+
+union cvmx_sriox_wr_done_counts {
+ uint64_t u64;
+ struct cvmx_sriox_wr_done_counts_s {
+ uint64_t reserved_32_63:32;
+ uint64_t bad:16;
+ uint64_t good:16;
+ } s;
+ struct cvmx_sriox_wr_done_counts_s cn63xx;
+ struct cvmx_sriox_wr_done_counts_s cn66xx;
+};
+
+#endif
--
1.7.2.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/5] MIPS: Octeon: Update feature test functions for new chips and features.
2011-11-15 23:46 [PATCH 0/5] MIPS: Octeon: PCI{,e} updates for Octeon II SOCs ddaney.cavm
2011-11-15 23:46 ` [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definitions for new chips ddaney.cavm
@ 2011-11-15 23:46 ` ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 3/5] MIPS: Octeon: Update DMA mapping operations for OCTEON II processors ddaney.cavm
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: ddaney.cavm @ 2011-11-15 23:46 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney
From: David Daney <david.daney@cavium.com>
cvmx.h was rearranged to fix include file ordering problems, but there
is no change other than moving some definitions around.
Signed-off-by: David Daney <david.daney@cavium.com>
---
arch/mips/include/asm/octeon/cvmx.h | 42 +++++-----
arch/mips/include/asm/octeon/octeon-feature.h | 114 +++++++++++++++++++++++--
2 files changed, 126 insertions(+), 30 deletions(-)
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 7e12867..740be97 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -31,6 +31,27 @@
#include <linux/kernel.h>
#include <linux/string.h>
+enum cvmx_mips_space {
+ CVMX_MIPS_SPACE_XKSEG = 3LL,
+ CVMX_MIPS_SPACE_XKPHYS = 2LL,
+ CVMX_MIPS_SPACE_XSSEG = 1LL,
+ CVMX_MIPS_SPACE_XUSEG = 0LL
+};
+
+/* These macros for use when using 32 bit pointers. */
+#define CVMX_MIPS32_SPACE_KSEG0 1l
+#define CVMX_ADD_SEG32(segment, add) \
+ (((int32_t)segment << 31) | (int32_t)(add))
+
+#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
+
+/* These macros simplify the process of creating common IO addresses */
+#define CVMX_ADD_SEG(segment, add) \
+ ((((uint64_t)segment) << 62) | (add))
+#ifndef CVMX_ADD_IO_SEG
+#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
+#endif
+
#include "cvmx-asm.h"
#include "cvmx-packet.h"
#include "cvmx-sysinfo.h"
@@ -129,27 +150,6 @@ static inline uint64_t cvmx_build_bits(uint64_t high_bit,
return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
}
-enum cvmx_mips_space {
- CVMX_MIPS_SPACE_XKSEG = 3LL,
- CVMX_MIPS_SPACE_XKPHYS = 2LL,
- CVMX_MIPS_SPACE_XSSEG = 1LL,
- CVMX_MIPS_SPACE_XUSEG = 0LL
-};
-
-/* These macros for use when using 32 bit pointers. */
-#define CVMX_MIPS32_SPACE_KSEG0 1l
-#define CVMX_ADD_SEG32(segment, add) \
- (((int32_t)segment << 31) | (int32_t)(add))
-
-#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
-
-/* These macros simplify the process of creating common IO addresses */
-#define CVMX_ADD_SEG(segment, add) \
- ((((uint64_t)segment) << 62) | (add))
-#ifndef CVMX_ADD_IO_SEG
-#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
-#endif
-
/**
* Convert a memory pointer (void*) into a hardware compatible
* memory address (uint64_t). Octeon hardware widgets don't
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index cba6fbe..3caa826 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -31,8 +31,14 @@
#ifndef __OCTEON_FEATURE_H__
#define __OCTEON_FEATURE_H__
+#include <asm/octeon/cvmx-mio-defs.h>
+#include <asm/octeon/cvmx-rnm-defs.h>
enum octeon_feature {
+ /* CN68XX uses port kinds for packet interface */
+ OCTEON_FEATURE_PKND,
+ /* CN68XX has different fields in word0 - word2 */
+ OCTEON_FEATURE_CN68XX_WQE,
/*
* Octeon models in the CN5XXX family and higher support
* atomic add instructions to memory (saa/saad).
@@ -42,8 +48,13 @@ enum octeon_feature {
OCTEON_FEATURE_ZIP,
/* Does this Octeon support crypto acceleration using COP2? */
OCTEON_FEATURE_CRYPTO,
+ OCTEON_FEATURE_DORM_CRYPTO,
/* Does this Octeon support PCI express? */
OCTEON_FEATURE_PCIE,
+ /* Does this Octeon support SRIOs */
+ OCTEON_FEATURE_SRIO,
+ /* Does this Octeon support Interlaken */
+ OCTEON_FEATURE_ILK,
/* Some Octeon models support internal memory for storing
* cryptographic keys */
OCTEON_FEATURE_KEY_MEMORY,
@@ -64,6 +75,15 @@ enum octeon_feature {
/* Octeon MDIO block supports clause 45 transactions for 10
* Gig support */
OCTEON_FEATURE_MDIO_CLAUSE_45,
+ /*
+ * CN52XX and CN56XX used a block named NPEI for PCIe
+ * access. Newer chips replaced this with SLI+DPI.
+ */
+ OCTEON_FEATURE_NPEI,
+ OCTEON_FEATURE_HFA,
+ OCTEON_FEATURE_DFM,
+ OCTEON_FEATURE_CIU2,
+ OCTEON_MAX_FEATURE
};
static inline int cvmx_fuse_read(int fuse);
@@ -96,30 +116,78 @@ static inline int octeon_has_feature(enum octeon_feature feature)
return !cvmx_fuse_read(121);
case OCTEON_FEATURE_CRYPTO:
- return !cvmx_fuse_read(90);
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ union cvmx_mio_fus_dat2 fus_2;
+ fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+ if (fus_2.s.nocrypto || fus_2.s.nomul) {
+ return 0;
+ } else if (!fus_2.s.dorm_crypto) {
+ return 1;
+ } else {
+ union cvmx_rnm_ctl_status st;
+ st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS);
+ return st.s.eer_val;
+ }
+ } else {
+ return !cvmx_fuse_read(90);
+ }
+
+ case OCTEON_FEATURE_DORM_CRYPTO:
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ union cvmx_mio_fus_dat2 fus_2;
+ fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
+ return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto;
+ } else {
+ return 0;
+ }
case OCTEON_FEATURE_PCIE:
- case OCTEON_FEATURE_MGMT_PORT:
- case OCTEON_FEATURE_RAID:
return OCTEON_IS_MODEL(OCTEON_CN56XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX);
+ || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
+ case OCTEON_FEATURE_SRIO:
+ return OCTEON_IS_MODEL(OCTEON_CN63XX)
+ || OCTEON_IS_MODEL(OCTEON_CN66XX);
+
+ case OCTEON_FEATURE_ILK:
+ return (OCTEON_IS_MODEL(OCTEON_CN68XX));
case OCTEON_FEATURE_KEY_MEMORY:
+ return OCTEON_IS_MODEL(OCTEON_CN38XX)
+ || OCTEON_IS_MODEL(OCTEON_CN58XX)
+ || OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
case OCTEON_FEATURE_LED_CONTROLLER:
return OCTEON_IS_MODEL(OCTEON_CN38XX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX)
|| OCTEON_IS_MODEL(OCTEON_CN56XX);
+
case OCTEON_FEATURE_TRA:
return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
|| OCTEON_IS_MODEL(OCTEON_CN50XX));
+ case OCTEON_FEATURE_MGMT_PORT:
+ return OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
+ case OCTEON_FEATURE_RAID:
+ return OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN6XXX);
+
case OCTEON_FEATURE_USB:
return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX));
+
case OCTEON_FEATURE_NO_WPTR:
return (OCTEON_IS_MODEL(OCTEON_CN56XX)
- || OCTEON_IS_MODEL(OCTEON_CN52XX))
- && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
- && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+ || OCTEON_IS_MODEL(OCTEON_CN52XX)
+ || OCTEON_IS_MODEL(OCTEON_CN6XXX))
+ && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
+ && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
+
case OCTEON_FEATURE_DFA:
if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
&& !OCTEON_IS_MODEL(OCTEON_CN31XX)
@@ -127,14 +195,42 @@ static inline int octeon_has_feature(enum octeon_feature feature)
return 0;
else if (OCTEON_IS_MODEL(OCTEON_CN3020))
return 0;
- else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
- return 1;
else
return !cvmx_fuse_read(120);
+
+ case OCTEON_FEATURE_HFA:
+ if (!OCTEON_IS_MODEL(OCTEON_CN6XXX))
+ return 0;
+ else
+ return !cvmx_fuse_read(90);
+
+ case OCTEON_FEATURE_DFM:
+ if (!(OCTEON_IS_MODEL(OCTEON_CN63XX)
+ || OCTEON_IS_MODEL(OCTEON_CN66XX)))
+ return 0;
+ else
+ return !cvmx_fuse_read(90);
+
case OCTEON_FEATURE_MDIO_CLAUSE_45:
return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX)
|| OCTEON_IS_MODEL(OCTEON_CN50XX));
+
+ case OCTEON_FEATURE_NPEI:
+ return OCTEON_IS_MODEL(OCTEON_CN56XX)
+ || OCTEON_IS_MODEL(OCTEON_CN52XX);
+
+ case OCTEON_FEATURE_PKND:
+ return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+ case OCTEON_FEATURE_CN68XX_WQE:
+ return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+ case OCTEON_FEATURE_CIU2:
+ return OCTEON_IS_MODEL(OCTEON_CN68XX);
+
+ default:
+ break;
}
return 0;
}
--
1.7.2.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/5] MIPS: Octeon: Update DMA mapping operations for OCTEON II processors.
2011-11-15 23:46 [PATCH 0/5] MIPS: Octeon: PCI{,e} updates for Octeon II SOCs ddaney.cavm
2011-11-15 23:46 ` [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definitions for new chips ddaney.cavm
2011-11-15 23:46 ` [PATCH 2/5] MIPS: Octeon: Update feature test functions for new chips and features ddaney.cavm
@ 2011-11-15 23:46 ` ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 4/5] MIPS: Octeon: Update PCI Latency timer, PCIe payload, and PCIe max read to allow larger transactions ddaney.cavm
2011-11-15 23:46 ` [PATCH 5/5] MIPS: Octeon: Add support for OCTEON II PCIe ddaney.cavm
4 siblings, 1 reply; 11+ messages in thread
From: ddaney.cavm @ 2011-11-15 23:46 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney, David Daney
From: David Daney <david.daney@cavium.com>
OCTEON II has a new dma to phys mapping method for PCIe. Define
OCTEON_DMA_BAR_TYPE_PCIE2 to denote this case, and handle it.
OCTEON II also needs a swiotlb if the OHCI USB driver is enabled, so
allocate this too.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/cavium-octeon/dma-octeon.c | 23 +++++++++++++++++++++--
arch/mips/include/asm/octeon/pci-octeon.h | 3 ++-
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index ea4feba..b6bb92c 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -61,6 +61,16 @@ static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
return daddr;
}
+static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+ return octeon_hole_phys_to_dma(paddr);
+}
+
+static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+ return octeon_hole_dma_to_phys(daddr);
+}
+
static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
{
if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
@@ -262,11 +272,11 @@ void __init plat_swiotlb_setup(void)
for (i = 0 ; i < boot_mem_map.nr_map; i++) {
struct boot_mem_map_entry *e = &boot_mem_map.map[i];
- if (e->type != BOOT_MEM_RAM)
+ if (e->type != BOOT_MEM_RAM && e->type != BOOT_MEM_INIT_RAM)
continue;
/* These addresses map low for PCI. */
- if (e->addr > 0x410000000ull)
+ if (e->addr > 0x410000000ull && !OCTEON_IS_MODEL(OCTEON_CN6XXX))
continue;
addr_size += e->size;
@@ -296,6 +306,11 @@ void __init plat_swiotlb_setup(void)
swiotlbsize = 64 * (1<<20);
}
#endif
+#ifdef CONFIG_USB_OCTEON_OHCI
+ /* OCTEON II ohci is only 32-bit. */
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && max_addr >= 0x100000000ul)
+ swiotlbsize = 64 * (1<<20);
+#endif
swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
@@ -330,6 +345,10 @@ struct dma_map_ops *octeon_pci_dma_map_ops;
void __init octeon_pci_dma_init(void)
{
switch (octeon_dma_bar_type) {
+ case OCTEON_DMA_BAR_TYPE_PCIE2:
+ _octeon_pci_dma_map_ops.phys_to_dma = octeon_gen2_phys_to_dma;
+ _octeon_pci_dma_map_ops.dma_to_phys = octeon_gen2_dma_to_phys;
+ break;
case OCTEON_DMA_BAR_TYPE_PCIE:
_octeon_pci_dma_map_ops.phys_to_dma = octeon_gen1_phys_to_dma;
_octeon_pci_dma_map_ops.dma_to_phys = octeon_gen1_dma_to_phys;
diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index fba2ba2..c66734b 100644
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -56,7 +56,8 @@ enum octeon_dma_bar_type {
OCTEON_DMA_BAR_TYPE_INVALID,
OCTEON_DMA_BAR_TYPE_SMALL,
OCTEON_DMA_BAR_TYPE_BIG,
- OCTEON_DMA_BAR_TYPE_PCIE
+ OCTEON_DMA_BAR_TYPE_PCIE,
+ OCTEON_DMA_BAR_TYPE_PCIE2
};
/*
--
1.7.2.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/5] MIPS: Octeon: Update PCI Latency timer, PCIe payload, and PCIe max read to allow larger transactions
2011-11-15 23:46 [PATCH 0/5] MIPS: Octeon: PCI{,e} updates for Octeon II SOCs ddaney.cavm
` (2 preceding siblings ...)
2011-11-15 23:46 ` [PATCH 3/5] MIPS: Octeon: Update DMA mapping operations for OCTEON II processors ddaney.cavm
@ 2011-11-15 23:46 ` ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 5/5] MIPS: Octeon: Add support for OCTEON II PCIe ddaney.cavm
4 siblings, 1 reply; 11+ messages in thread
From: ddaney.cavm @ 2011-11-15 23:46 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney, David Daney
From: David Daney <david.daney@cavium.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
---
arch/mips/pci/pci-octeon.c | 26 ++++++++++++++++----------
1 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index ed1c542..e2ca7de 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -99,7 +99,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
*/
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
/* Set latency timers for all devices */
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
/* Enable reporting System errors and parity errors on all devices */
/* Enable parity checking and error reporting */
@@ -109,7 +109,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
if (dev->subordinate) {
/* Set latency timers on sub bridges */
- pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
+ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64);
/* More bridge error detection */
pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
@@ -119,16 +119,22 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
/* Enable the PCIe normal error reporting */
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (pos) {
+ pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &dconfig);
/* Update Device Control */
pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
- /* Correctable Error Reporting */
- config |= PCI_EXP_DEVCTL_CERE;
- /* Non-Fatal Error Reporting */
- config |= PCI_EXP_DEVCTL_NFERE;
- /* Fatal Error Reporting */
- config |= PCI_EXP_DEVCTL_FERE;
- /* Unsupported Request */
- config |= PCI_EXP_DEVCTL_URRE;
+ config |= PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
+ config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
+ config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
+ config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
+ /*
+ * Octeon's max payload is 256 bytes. Set the device's
+ * to that unless it can't go that big
+ */
+ if ((dconfig & PCI_EXP_DEVCAP_PAYLOAD) >= 1)
+ config = (config & ~PCI_EXP_DEVCTL_PAYLOAD) | (1 << 5);
+ /* Set the max read size to 4KB, Octeon's max */
+ config = (config & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
+
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
}
--
1.7.2.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 5/5] MIPS: Octeon: Add support for OCTEON II PCIe
2011-11-15 23:46 [PATCH 0/5] MIPS: Octeon: PCI{,e} updates for Octeon II SOCs ddaney.cavm
` (3 preceding siblings ...)
2011-11-15 23:46 ` [PATCH 4/5] MIPS: Octeon: Update PCI Latency timer, PCIe payload, and PCIe max read to allow larger transactions ddaney.cavm
@ 2011-11-15 23:46 ` ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
4 siblings, 1 reply; 11+ messages in thread
From: ddaney.cavm @ 2011-11-15 23:46 UTC (permalink / raw)
To: linux-mips, ralf; +Cc: David Daney
From: David Daney <david.daney@cavium.com>
OCTEON II SOCs have a different PCIe implementation than is present in
OCTEON Plus.
Signed-off-by: David Daney <david.daney@cavium.com>
---
arch/mips/pci/pcie-octeon.c | 1349 ++++++++++++++++++++++++++++++++-----------
1 files changed, 1023 insertions(+), 326 deletions(-)
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index 0583c46..fdb4d55 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2007, 2008 Cavium Networks
+ * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks
*/
#include <linux/kernel.h>
#include <linux/init.h>
@@ -11,15 +11,32 @@
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/delay.h>
+#include <linux/module.h>
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-npei-defs.h>
#include <asm/octeon/cvmx-pciercx-defs.h>
#include <asm/octeon/cvmx-pescx-defs.h>
#include <asm/octeon/cvmx-pexp-defs.h>
+#include <asm/octeon/cvmx-pemx-defs.h>
+#include <asm/octeon/cvmx-dpi-defs.h>
+#include <asm/octeon/cvmx-sli-defs.h>
+#include <asm/octeon/cvmx-sriox-defs.h>
#include <asm/octeon/cvmx-helper-errata.h>
#include <asm/octeon/pci-octeon.h>
+#define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
+#define MPS_CN5XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
+#define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
+#define MPS_CN6XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
+
+/* Module parameter to disable PCI probing */
+static int pcie_disable;
+module_param(pcie_disable, int, S_IRUGO);
+
+static int enable_pcie_14459_war;
+static int enable_pcie_bus_num_war[2];
+
union cvmx_pcie_address {
uint64_t u64;
struct {
@@ -75,6 +92,8 @@ union cvmx_pcie_address {
} mem;
};
+static int cvmx_pcie_rc_initialize(int pcie_port);
+
#include <dma-coherence.h>
/**
@@ -154,12 +173,21 @@ static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
*/
static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
{
- union cvmx_pescx_cfg_rd pescx_cfg_rd;
- pescx_cfg_rd.u64 = 0;
- pescx_cfg_rd.s.addr = cfg_offset;
- cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
- pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
- return pescx_cfg_rd.s.data;
+ if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+ union cvmx_pescx_cfg_rd pescx_cfg_rd;
+ pescx_cfg_rd.u64 = 0;
+ pescx_cfg_rd.s.addr = cfg_offset;
+ cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
+ pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
+ return pescx_cfg_rd.s.data;
+ } else {
+ union cvmx_pemx_cfg_rd pemx_cfg_rd;
+ pemx_cfg_rd.u64 = 0;
+ pemx_cfg_rd.s.addr = cfg_offset;
+ cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
+ pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));
+ return pemx_cfg_rd.s.data;
+ }
}
/**
@@ -173,11 +201,19 @@ static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
uint32_t val)
{
- union cvmx_pescx_cfg_wr pescx_cfg_wr;
- pescx_cfg_wr.u64 = 0;
- pescx_cfg_wr.s.addr = cfg_offset;
- pescx_cfg_wr.s.data = val;
- cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
+ if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+ union cvmx_pescx_cfg_wr pescx_cfg_wr;
+ pescx_cfg_wr.u64 = 0;
+ pescx_cfg_wr.s.addr = cfg_offset;
+ pescx_cfg_wr.s.data = val;
+ cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
+ } else {
+ union cvmx_pemx_cfg_wr pemx_cfg_wr;
+ pemx_cfg_wr.u64 = 0;
+ pemx_cfg_wr.s.addr = cfg_offset;
+ pemx_cfg_wr.s.data = val;
+ cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
+ }
}
/**
@@ -348,7 +384,6 @@ static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
{
union cvmx_pciercx_cfg030 pciercx_cfg030;
- union cvmx_npei_ctl_status2 npei_ctl_status2;
union cvmx_pciercx_cfg070 pciercx_cfg070;
union cvmx_pciercx_cfg001 pciercx_cfg001;
union cvmx_pciercx_cfg032 pciercx_cfg032;
@@ -365,21 +400,21 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
/* Max Read Request Size (PCIE*_CFG030[MRRS]) */
/* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
/* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
- pciercx_cfg030.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
- /*
- * Max payload size = 128 bytes for best Octeon DMA
- * performance.
- */
- pciercx_cfg030.s.mps = 0;
+
+ pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
+ if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
+ pciercx_cfg030.s.mps = MPS_CN5XXX;
+ pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
+ } else {
+ pciercx_cfg030.s.mps = MPS_CN6XXX;
+ pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
+ }
/*
- * Max read request size = 128 bytes for best Octeon DMA
- * performance.
+ * Enable relaxed order processing. This will allow devices to
+ * affect read response ordering.
*/
- pciercx_cfg030.s.mrrs = 0;
- /* Enable relaxed ordering. */
pciercx_cfg030.s.ro_en = 1;
- /* Enable no snoop. */
+ /* Enable no snoop processing. Not used by Octeon */
pciercx_cfg030.s.ns_en = 1;
/* Correctable error reporting enable. */
pciercx_cfg030.s.ce_en = 1;
@@ -389,50 +424,67 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
pciercx_cfg030.s.fe_en = 1;
/* Unsupported request reporting enable. */
pciercx_cfg030.s.ur_en = 1;
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
- pciercx_cfg030.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
- /*
- * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
- * PCIE*_CFG030[MPS]
- *
- * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
- * exceed PCIE*_CFG030[MRRS].
- */
- npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
- /* Max payload size = 128 bytes for best Octeon DMA performance */
- npei_ctl_status2.s.mps = 0;
- /* Max read request size = 128 bytes for best Octeon DMA performance */
- npei_ctl_status2.s.mrrs = 0;
- if (pcie_port)
- npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
- else
- npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
- cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
+
+ if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+ union cvmx_npei_ctl_status2 npei_ctl_status2;
+ /*
+ * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
+ * PCIE*_CFG030[MPS]. Max Read Request Size
+ * (NPEI_CTL_STATUS2[MRRS]) must not exceed
+ * PCIE*_CFG030[MRRS]
+ */
+ npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
+ /* Max payload size = 128 bytes for best Octeon DMA performance */
+ npei_ctl_status2.s.mps = MPS_CN5XXX;
+ /* Max read request size = 128 bytes for best Octeon DMA performance */
+ npei_ctl_status2.s.mrrs = MRRS_CN5XXX;
+ if (pcie_port)
+ npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
+ else
+ npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
+
+ cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
+ } else {
+ /*
+ * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
+ * PCIE*_CFG030[MPS]. Max Read Request Size
+ * (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
+ * PCIE*_CFG030[MRRS].
+ */
+ union cvmx_dpi_sli_prtx_cfg prt_cfg;
+ union cvmx_sli_s2m_portx_ctl sli_s2m_portx_ctl;
+ prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
+ prt_cfg.s.mps = MPS_CN6XXX;
+ prt_cfg.s.mrrs = MRRS_CN6XXX;
+ /* Max outstanding load request. */
+ prt_cfg.s.molr = 32;
+ cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
+
+ sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
+ sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
+ cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
+ }
/* ECRC Generation (PCIE*_CFG070[GE,CE]) */
- pciercx_cfg070.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
+ pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
- pciercx_cfg070.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
/*
- * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
- * always be set.
- *
- * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
- * Message Enable (PCIE*_CFG001[SEE])
+ * Access Enables (PCIE*_CFG001[MSAE,ME])
+ * ME and MSAE should always be set.
+ * Interrupt Disable (PCIE*_CFG001[I_DIS])
+ * System Error Message Enable (PCIE*_CFG001[SEE])
*/
- pciercx_cfg001.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
+ pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
pciercx_cfg001.s.msae = 1; /* Memory space enable. */
pciercx_cfg001.s.me = 1; /* Bus master enable. */
pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
pciercx_cfg001.s.see = 1; /* SERR# enable */
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
- pciercx_cfg001.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
/* Advanced Error Recovery Message Enables */
/* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
@@ -440,14 +492,11 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
/* Use CVMX_PCIERCX_CFG067 hardware default */
cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
- /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
- pciercx_cfg032.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
- pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
- pciercx_cfg032.u32);
- /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
+ /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
+ pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+ pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
/*
* Link Width Mode (PCIERCn_CFG452[LME]) - Set during
@@ -462,8 +511,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
pciercx_cfg006.s.pbnum = 1;
pciercx_cfg006.s.sbnum = 1;
pciercx_cfg006.s.subbnum = 1;
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
- pciercx_cfg006.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
+
/*
* Memory-mapped I/O BAR (PCIERCn_CFG008)
@@ -473,8 +522,8 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
pciercx_cfg008.u32 = 0;
pciercx_cfg008.s.mb_addr = 0x100;
pciercx_cfg008.s.ml_addr = 0;
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
- pciercx_cfg008.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
+
/*
* Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
@@ -482,72 +531,51 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
* PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
* PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
*/
- pciercx_cfg009.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
- pciercx_cfg010.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
- pciercx_cfg011.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
+ pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
+ pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
+ pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
pciercx_cfg009.s.lmem_base = 0x100;
pciercx_cfg009.s.lmem_limit = 0;
pciercx_cfg010.s.umem_base = 0x100;
pciercx_cfg011.s.umem_limit = 0;
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
- pciercx_cfg009.u32);
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
- pciercx_cfg010.u32);
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
- pciercx_cfg011.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
/*
* System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
* PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
- */
- pciercx_cfg035.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
- /* System error on correctable error enable. */
- pciercx_cfg035.s.secee = 1;
- /* System error on fatal error enable. */
- pciercx_cfg035.s.sefee = 1;
- /* System error on non-fatal error enable. */
- pciercx_cfg035.s.senfee = 1;
- /* PME interrupt enable. */
- pciercx_cfg035.s.pmeie = 1;
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
- pciercx_cfg035.u32);
+ */
+ pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
+ pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
+ pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
+ pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
+ pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
/*
* Advanced Error Recovery Interrupt Enables
* (PCIERCn_CFG075[CERE,NFERE,FERE])
*/
- pciercx_cfg075.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
- /* Correctable error reporting enable. */
- pciercx_cfg075.s.cere = 1;
- /* Non-fatal error reporting enable. */
- pciercx_cfg075.s.nfere = 1;
- /* Fatal error reporting enable. */
- pciercx_cfg075.s.fere = 1;
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
- pciercx_cfg075.u32);
+ pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
+ pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
+ pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
+ pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
- /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
+ /*
+ * HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
* PCIERCn_CFG034[DLLS_EN,CCINT_EN])
*/
- pciercx_cfg034.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
- /* Hot-plug interrupt enable. */
- pciercx_cfg034.s.hpint_en = 1;
- /* Data Link Layer state changed enable */
- pciercx_cfg034.s.dlls_en = 1;
- /* Command completed interrupt enable. */
- pciercx_cfg034.s.ccint_en = 1;
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
- pciercx_cfg034.u32);
+ pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
+ pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
+ pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
+ pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
}
/**
- * Initialize a host mode PCIe link. This function takes a PCIe
+ * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
* port from reset to a link up state. Software can then begin
* configuring the rest of the link.
*
@@ -555,7 +583,7 @@ static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
*
* Returns Zero on success
*/
-static int __cvmx_pcie_rc_initialize_link(int pcie_port)
+static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
{
uint64_t start_cycle;
union cvmx_pescx_ctl_status pescx_ctl_status;
@@ -564,18 +592,15 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
union cvmx_pciercx_cfg448 pciercx_cfg448;
/* Set the lane width */
- pciercx_cfg452.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
+ pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
- if (pescx_ctl_status.s.qlm_cfg == 0) {
+ if (pescx_ctl_status.s.qlm_cfg == 0)
/* We're in 8 lane (56XX) or 4 lane (54XX) mode */
pciercx_cfg452.s.lme = 0xf;
- } else {
+ else
/* We're in 4 lane (56XX) or 2 lane (52XX) mode */
pciercx_cfg452.s.lme = 0x7;
- }
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
- pciercx_cfg452.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);
/*
* CN52XX pass 1.x has an errata where length mismatches on UR
@@ -584,19 +609,15 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
*/
if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
union cvmx_pciercx_cfg455 pciercx_cfg455;
- pciercx_cfg455.u32 =
- cvmx_pcie_cfgx_read(pcie_port,
- CVMX_PCIERCX_CFG455(pcie_port));
+ pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));
pciercx_cfg455.s.m_cpl_len_err = 1;
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
- pciercx_cfg455.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);
}
/* Lane swap needs to be manually enabled for CN52XX */
if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
pescx_ctl_status.s.lane_swp = 1;
- cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
- pescx_ctl_status.u64);
+ cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
}
/* Bring up the link */
@@ -612,24 +633,18 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
__cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
/* Wait for the link to come up */
- cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
start_cycle = cvmx_get_cycle();
do {
- if (cvmx_get_cycle() - start_cycle >
- 2 * cvmx_sysinfo_get()->cpu_clock_hz) {
- cvmx_dprintf("PCIe: Port %d link timeout\n",
- pcie_port);
+ if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) {
+ cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
return -1;
}
cvmx_wait(10000);
- pciercx_cfg032.u32 =
- cvmx_pcie_cfgx_read(pcie_port,
- CVMX_PCIERCX_CFG032(pcie_port));
+ pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
} while (pciercx_cfg032.s.dlla == 0);
- /* Display the link status */
- cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
- pciercx_cfg032.s.nlw);
+ /* Clear all pending errors */
+ cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
/*
* Update the Replay Time Limit. Empirically, some PCIe
@@ -639,8 +654,7 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
* our actual 256 byte MPS. The numbers below are directly
* from the PCIe spec table 3-4.
*/
- pciercx_cfg448.u32 =
- cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
+ pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
switch (pciercx_cfg032.s.nlw) {
case 1: /* 1 lane */
pciercx_cfg448.s.rtl = 1677;
@@ -655,21 +669,28 @@ static int __cvmx_pcie_rc_initialize_link(int pcie_port)
pciercx_cfg448.s.rtl = 258;
break;
}
- cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
- pciercx_cfg448.u32);
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
return 0;
}
+static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ pmas->cn68xx.ba++;
+ else
+ pmas->cn63xx.ba++;
+}
+
/**
- * Initialize a PCIe port for use in host(RC) mode. It doesn't
+ * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't
* enumerate the bus.
*
* @pcie_port: PCIe port to initialize
*
* Returns Zero on success
*/
-static int cvmx_pcie_rc_initialize(int pcie_port)
+static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
{
int i;
int base;
@@ -682,16 +703,17 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
union cvmx_npei_mem_access_subidx mem_access_subid;
union cvmx_npei_dbg_data npei_dbg_data;
union cvmx_pescx_ctl_status2 pescx_ctl_status2;
+ union cvmx_pciercx_cfg032 pciercx_cfg032;
union cvmx_npei_bar1_indexx bar1_index;
+retry:
/*
* Make sure we aren't trying to setup a target mode interface
* in host mode.
*/
npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
- cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
- "on port0, but port0 is not in host mode\n");
+ cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);
return -1;
}
@@ -702,9 +724,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
- cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
- "called on port1, but port1 is "
- "disabled\n");
+ cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n");
return -1;
}
}
@@ -733,7 +753,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
* the board. As a workaround for this bug, we bring
* both PCIe ports out of reset at the same time
* instead of on separate calls. So for port 0, we
- * bring both out of reset and do nothing on port 1.
+ * bring both out of reset and do nothing on port 1
*/
if (pcie_port == 0) {
ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
@@ -746,13 +766,10 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
if (ciu_soft_prst.s.soft_prst == 0) {
/* Reset the ports */
ciu_soft_prst.s.soft_prst = 1;
- cvmx_write_csr(CVMX_CIU_SOFT_PRST,
- ciu_soft_prst.u64);
- ciu_soft_prst.u64 =
- cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
ciu_soft_prst.s.soft_prst = 1;
- cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
- ciu_soft_prst.u64);
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
/* Wait until pcie resets the ports. */
udelay(2000);
}
@@ -782,11 +799,9 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
/* Reset the port */
ciu_soft_prst.s.soft_prst = 1;
if (pcie_port)
- cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
- ciu_soft_prst.u64);
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
else
- cvmx_write_csr(CVMX_CIU_SOFT_PRST,
- ciu_soft_prst.u64);
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
/* Wait until pcie resets the ports. */
udelay(2000);
}
@@ -808,25 +823,21 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
*/
cvmx_wait(400000);
- /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
- CN52XX, so we only probe it on newer chips */
- if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
- && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
+ /*
+ * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
+ * CN56XX and CN52XX, so we only probe it on newer chips
+ */
+ if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
/* Clear PCLK_RUN so we can check if the clock is running */
- pescx_ctl_status2.u64 =
- cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
+ pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
pescx_ctl_status2.s.pclk_run = 1;
- cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
- pescx_ctl_status2.u64);
- /*
- * Now that we cleared PCLK_RUN, wait for it to be set
- * again telling us the clock is running.
+ cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);
+ /* Now that we cleared PCLK_RUN, wait for it to be set
+ * again telling us the clock is running
*/
if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
- union cvmx_pescx_ctl_status2,
- pclk_run, ==, 1, 10000)) {
- cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
- pcie_port);
+ union cvmx_pescx_ctl_status2, pclk_run, ==, 1, 10000)) {
+ cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);
return -1;
}
}
@@ -836,30 +847,26 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
* the board probably hasn't wired the clocks up and the
* interface should be skipped.
*/
- pescx_ctl_status2.u64 =
- cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
+ pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
if (pescx_ctl_status2.s.pcierst) {
- cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
- pcie_port);
+ cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
return -1;
}
/*
- * Check BIST2 status. If any bits are set skip this interface. This
- * is an attempt to catch PCIE-813 on pass 1 parts.
+ * Check BIST2 status. If any bits are set skip this
+ * interface. This is an attempt to catch PCIE-813 on pass 1
+ * parts.
*/
- pescx_bist_status2.u64 =
- cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
+ pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
if (pescx_bist_status2.u64) {
- cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
- "port isn't hooked up, skipping.\n",
+ cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n",
pcie_port);
return -1;
}
/* Check BIST status */
- pescx_bist_status.u64 =
- cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
+ pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
if (pescx_bist_status.u64)
cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
pcie_port, CAST64(pescx_bist_status.u64));
@@ -868,50 +875,37 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
__cvmx_pcie_rc_initialize_config_space(pcie_port);
/* Bring the link up */
- if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
- cvmx_dprintf
- ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
+ if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) {
+ cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n",
+ pcie_port);
return -1;
}
/* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
- /* Allow 16 words to combine */
- npei_mem_access_ctl.s.max_word = 0;
- /* Wait up to 127 cycles for more data */
- npei_mem_access_ctl.s.timer = 127;
+ npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
+ npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
/* Setup Mem access SubDIDs */
mem_access_subid.u64 = 0;
- /* Port the request is sent to. */
- mem_access_subid.s.port = pcie_port;
- /* Due to an errata on pass 1 chips, no merging is allowed. */
- mem_access_subid.s.nmerge = 1;
- /* Endian-swap for Reads. */
- mem_access_subid.s.esr = 1;
- /* Endian-swap for Writes. */
- mem_access_subid.s.esw = 1;
- /* No Snoop for Reads. */
- mem_access_subid.s.nsr = 1;
- /* No Snoop for Writes. */
- mem_access_subid.s.nsw = 1;
- /* Disable Relaxed Ordering for Reads. */
- mem_access_subid.s.ror = 0;
- /* Disable Relaxed Ordering for Writes. */
- mem_access_subid.s.row = 0;
- /* PCIe Address Bits <63:34>. */
- mem_access_subid.s.ba = 0;
+ mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
+ mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
+ mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
+ mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
+ mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
+ mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */
+ mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */
+ mem_access_subid.s.row = 0; /* Disable Relaxed Ordering for Writes. */
+ mem_access_subid.s.ba = 0; /* PCIe Adddress Bits <63:34>. */
/*
* Setup mem access 12-15 for port 0, 16-19 for port 1,
* supplying 36 bits of address space.
*/
for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
- cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
- mem_access_subid.u64);
- /* Set each SUBID to extend the addressable range */
- mem_access_subid.s.ba += 1;
+ cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
+ mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
}
/*
@@ -927,7 +921,7 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
/* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
- /* BAR1 follows BAR2 with a gap. */
+ /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */
cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
bar1_index.u32 = 0;
@@ -992,14 +986,474 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
npei_ctl_port.s.waitl_com = 0;
cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
}
+
+ /*
+ * Both pass 1 and pass 2 of CN52XX and CN56XX have an errata
+ * that causes TLP ordering to not be preserved after multiple
+ * PCIe port resets. This code detects this fault and corrects
+ * it by aligning the TLP counters properly. Another link
+ * reset is then performed. See PCIE-13340
+ */
+ if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
+ union cvmx_npei_dbg_data dbg_data;
+ int old_in_fif_p_count;
+ int in_fif_p_count;
+ int out_p_count;
+ int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1;
+ int i;
+
+ /*
+ * Choose a write address of 1MB. It should be
+ * harmless as all bars haven't been setup.
+ */
+ uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);
+
+ /*
+ * Make sure at least in_p_offset have been executed before we try and
+ * read in_fif_p_count
+ */
+ i = in_p_offset;
+ while (i--) {
+ cvmx_write64_uint32(write_address, 0);
+ cvmx_wait(10000);
+ }
+
+ /*
+ * Read the IN_FIF_P_COUNT from the debug
+ * select. IN_FIF_P_COUNT can be unstable sometimes so
+ * read it twice with a write between the reads. This
+ * way we can tell the value is good as it will
+ * increment by one due to the write
+ */
+ cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);
+ cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
+ do {
+ dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+ old_in_fif_p_count = dbg_data.s.data & 0xff;
+ cvmx_write64_uint32(write_address, 0);
+ cvmx_wait(10000);
+ dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+ in_fif_p_count = dbg_data.s.data & 0xff;
+ } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
+
+ /* Update in_fif_p_count for it's offset with respect to out_p_count */
+ in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
+
+ /* Read the OUT_P_COUNT from the debug select */
+ cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);
+ cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
+ dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+ out_p_count = (dbg_data.s.data>>1) & 0xff;
+
+ /* Check that the two counters are aligned */
+ if (out_p_count != in_fif_p_count) {
+ cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
+ while (in_fif_p_count != 0) {
+ cvmx_write64_uint32(write_address, 0);
+ cvmx_wait(10000);
+ in_fif_p_count = (in_fif_p_count + 1) & 0xff;
+ }
+ /*
+ * The EBH5200 board swapped the PCIe reset
+ * lines on the board. This means we must
+ * bring both links down and up, which will
+ * cause the PCIe0 to need alignment
+ * again. Lots of messages will be displayed,
+ * but everything should work
+ */
+ if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
+ (pcie_port == 1))
+ cvmx_pcie_rc_initialize(0);
+ /* Rety bringing this port up */
+ goto retry;
+ }
+ }
+
+ /* Display the link status */
+ pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+ cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
+
return 0;
}
+/**
+ * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
+ * port from reset to a link up state. Software can then begin
+ * configuring the rest of the link.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Return Zero on success.
+ */
+static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
+{
+ uint64_t start_cycle;
+ union cvmx_pemx_ctl_status pem_ctl_status;
+ union cvmx_pciercx_cfg032 pciercx_cfg032;
+ union cvmx_pciercx_cfg448 pciercx_cfg448;
-/* Above was cvmx-pcie.c, below original pcie.c */
+ /* Bring up the link */
+ pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
+ pem_ctl_status.s.lnk_enb = 1;
+ cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
+
+ /* Wait for the link to come up */
+ start_cycle = cvmx_get_cycle();
+ do {
+ if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
+ return -1;
+ cvmx_wait(10000);
+ pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+ } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
+
+ /*
+ * Update the Replay Time Limit. Empirically, some PCIe
+ * devices take a little longer to respond than expected under
+ * load. As a workaround for this we configure the Replay Time
+ * Limit to the value expected for a 512 byte MPS instead of
+ * our actual 256 byte MPS. The numbers below are directly
+ * from the PCIe spec table 3-4
+ */
+ pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
+ switch (pciercx_cfg032.s.nlw) {
+ case 1: /* 1 lane */
+ pciercx_cfg448.s.rtl = 1677;
+ break;
+ case 2: /* 2 lanes */
+ pciercx_cfg448.s.rtl = 867;
+ break;
+ case 4: /* 4 lanes */
+ pciercx_cfg448.s.rtl = 462;
+ break;
+ case 8: /* 8 lanes */
+ pciercx_cfg448.s.rtl = 258;
+ break;
+ }
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
+
+ return 0;
+}
/**
+ * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
+ * the bus.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Returns Zero on success.
+ */
+static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
+{
+ int i;
+ union cvmx_ciu_soft_prst ciu_soft_prst;
+ union cvmx_mio_rst_ctlx mio_rst_ctl;
+ union cvmx_pemx_bar_ctl pemx_bar_ctl;
+ union cvmx_pemx_ctl_status pemx_ctl_status;
+ union cvmx_pemx_bist_status pemx_bist_status;
+ union cvmx_pemx_bist_status2 pemx_bist_status2;
+ union cvmx_pciercx_cfg032 pciercx_cfg032;
+ union cvmx_pciercx_cfg515 pciercx_cfg515;
+ union cvmx_sli_ctl_portx sli_ctl_portx;
+ union cvmx_sli_mem_access_ctl sli_mem_access_ctl;
+ union cvmx_sli_mem_access_subidx mem_access_subid;
+ union cvmx_sriox_status_reg sriox_status_reg;
+ union cvmx_pemx_bar1_indexx bar1_index;
+
+ if (octeon_has_feature(OCTEON_FEATURE_SRIO)) {
+ /* Make sure this interface isn't SRIO */
+ if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
+ /*
+ * The CN66XX requires reading the
+ * MIO_QLMX_CFG register to figure out the
+ * port type.
+ */
+ union cvmx_mio_qlmx_cfg qlmx_cfg;
+ qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));
+
+ if (qlmx_cfg.s.qlm_spd == 15) {
+ pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port);
+ return -1;
+ }
+
+ switch (qlmx_cfg.s.qlm_spd) {
+ case 0x1: /* SRIO 1x4 short */
+ case 0x3: /* SRIO 1x4 long */
+ case 0x4: /* SRIO 2x2 short */
+ case 0x6: /* SRIO 2x2 long */
+ pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
+ return -1;
+ case 0x9: /* SGMII */
+ pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port);
+ return -1;
+ case 0xb: /* XAUI */
+ pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port);
+ return -1;
+ case 0x0: /* PCIE gen2 */
+ case 0x8: /* PCIE gen2 (alias) */
+ case 0x2: /* PCIE gen1 */
+ case 0xa: /* PCIE gen1 (alias) */
+ break;
+ default:
+ pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port);
+ return -1;
+ }
+ } else {
+ sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
+ if (sriox_status_reg.s.srio) {
+ pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
+ return -1;
+ }
+ }
+ }
+
+#if 0
+ /* This code is so that the PCIe analyzer is able to see 63XX traffic */
+ pr_notice("PCIE : init for pcie analyzer.\n");
+ cvmx_helper_qlm_jtag_init();
+ cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+ cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+ cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+ cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+ cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+ cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+ cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+ cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+ cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+ cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
+ cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
+ cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
+ cvmx_helper_qlm_jtag_update(pcie_port);
+#endif
+
+ /* Make sure we aren't trying to setup a target mode interface in host mode */
+ mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
+ if (!mio_rst_ctl.s.host_mode) {
+ pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port);
+ return -1;
+ }
+
+ /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
+ if (pcie_port) {
+ union cvmx_ciu_qlm1 ciu_qlm;
+ ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
+ ciu_qlm.s.txbypass = 1;
+ ciu_qlm.s.txdeemph = 5;
+ ciu_qlm.s.txmargin = 0x17;
+ cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
+ } else {
+ union cvmx_ciu_qlm0 ciu_qlm;
+ ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
+ ciu_qlm.s.txbypass = 1;
+ ciu_qlm.s.txdeemph = 5;
+ ciu_qlm.s.txmargin = 0x17;
+ cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
+ }
+ }
+ /* Bring the PCIe out of reset */
+ if (pcie_port)
+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+ else
+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+ /*
+ * After a chip reset the PCIe will also be in reset. If it
+ * isn't, most likely someone is trying to init it again
+ * without a proper PCIe reset
+ */
+ if (ciu_soft_prst.s.soft_prst == 0) {
+ /* Reset the port */
+ ciu_soft_prst.s.soft_prst = 1;
+ if (pcie_port)
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+ else
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+ /* Wait until pcie resets the ports. */
+ udelay(2000);
+ }
+ if (pcie_port) {
+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
+ ciu_soft_prst.s.soft_prst = 0;
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
+ } else {
+ ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
+ ciu_soft_prst.s.soft_prst = 0;
+ cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
+ }
+
+ /* Wait for PCIe reset to complete */
+ udelay(1000);
+
+ /*
+ * Check and make sure PCIe came out of reset. If it doesn't
+ * the board probably hasn't wired the clocks up and the
+ * interface should be skipped.
+ */
+ if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {
+ pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
+ return -1;
+ }
+
+ /* Check BIST status */
+ pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));
+ if (pemx_bist_status.u64)
+ pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
+ pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
+ /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
+ pemx_bist_status2.u64 &= ~0x3full;
+ if (pemx_bist_status2.u64)
+ pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
+
+ /* Initialize the config space CSRs */
+ __cvmx_pcie_rc_initialize_config_space(pcie_port);
+
+ /* Enable gen2 speed selection */
+ pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
+ pciercx_cfg515.s.dsc = 1;
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
+
+ /* Bring the link up */
+ if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
+ /*
+ * Some gen1 devices don't handle the gen 2 training
+ * correctly. Disable gen2 and try again with only
+ * gen1
+ */
+ union cvmx_pciercx_cfg031 pciercx_cfg031;
+ pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
+ pciercx_cfg031.s.mls = 1;
+ cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
+ if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
+ pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
+ return -1;
+ }
+ }
+
+ /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
+ sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
+ sli_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
+ sli_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
+ cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
+
+ /* Setup Mem access SubDIDs */
+ mem_access_subid.u64 = 0;
+ mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
+ mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
+ mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
+ mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
+ mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
+ mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
+ /* PCIe Adddress Bits <63:34>. */
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ mem_access_subid.cn68xx.ba = 0;
+ else
+ mem_access_subid.cn63xx.ba = 0;
+
+ /*
+ * Setup mem access 12-15 for port 0, 16-19 for port 1,
+ * supplying 36 bits of address space.
+ */
+ for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
+ cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
+ /* Set each SUBID to extend the addressable range */
+ __cvmx_increment_ba(&mem_access_subid);
+ }
+
+ /*
+ * Disable the peer to peer forwarding register. This must be
+ * setup by the OS after it enumerates the bus and assigns
+ * addresses to the PCIe busses.
+ */
+ for (i = 0; i < 4; i++) {
+ cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
+ cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
+ }
+
+ /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
+ cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
+
+ /*
+ * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take
+ * precedence where they overlap. It also overlaps with the
+ * device addresses, so make sure the peer to peer forwarding
+ * is set right.
+ */
+ cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
+
+ /*
+ * Setup BAR2 attributes
+ * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
+ * - PTLP_RO,CTLP_RO should normally be set (except for debug).
+ * - WAIT_COM=0 will likely work for all applications.
+ * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM])
+ */
+ pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
+ pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1*/
+ pemx_bar_ctl.s.bar2_enb = 1;
+ pemx_bar_ctl.s.bar2_esx = 1;
+ pemx_bar_ctl.s.bar2_cax = 0;
+ cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
+ sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
+ sli_ctl_portx.s.ptlp_ro = 1;
+ sli_ctl_portx.s.ctlp_ro = 1;
+ sli_ctl_portx.s.wait_com = 0;
+ sli_ctl_portx.s.waitl_com = 0;
+ cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
+
+ /* BAR1 follows BAR2 */
+ cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
+
+ bar1_index.u64 = 0;
+ bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
+ bar1_index.s.ca = 1; /* Not Cached */
+ bar1_index.s.end_swp = 1; /* Endian Swap mode */
+ bar1_index.s.addr_v = 1; /* Valid entry */
+
+ for (i = 0; i < 16; i++) {
+ cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
+ /* 256MB / 16 >> 22 == 4 */
+ bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
+ }
+
+ /*
+ * Allow config retries for 250ms. Count is based off the 5Ghz
+ * SERDES clock.
+ */
+ pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
+ pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000;
+ cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
+
+ /* Display the link status */
+ pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+ pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
+
+ return 0;
+}
+
+/**
+ * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
+ *
+ * @pcie_port: PCIe port to initialize
+ *
+ * Returns Zero on success
+ */
+static int cvmx_pcie_rc_initialize(int pcie_port)
+{
+ int result;
+ if (octeon_has_feature(OCTEON_FEATURE_NPEI))
+ result = __cvmx_pcie_rc_initialize_gen1(pcie_port);
+ else
+ result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
+ return result;
+}
+
+/* Above was cvmx-pcie.c, below original pcie.c */
+
+/**
* Map a PCI device to the appropriate interrupt line
*
* @dev: The Linux PCI device structure for the device to map
@@ -1027,11 +1481,12 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
*/
while (dev->bus && dev->bus->parent)
dev = to_pci_dev(dev->bus->bridge);
- /* If the root bus is number 0 and the PEX 8114 is the
+ /*
+ * If the root bus is number 0 and the PEX 8114 is the
* root, assume we are behind the miswired bus. We
* need to correct the swizzle level by two. Yuck.
*/
- if ((dev->bus->number == 0) &&
+ if ((dev->bus->number == 1) &&
(dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
/*
* The pin field is one based, not zero. We
@@ -1048,39 +1503,73 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
return pin - 1 + OCTEON_IRQ_PCI_INT0;
}
-/**
+static void set_cfg_read_retry(u32 retry_cnt)
+{
+ union cvmx_pemx_ctl_status pemx_ctl;
+ pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
+ pemx_ctl.s.cfg_rtry = retry_cnt;
+ cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
+}
+
+
+static u32 disable_cfg_read_retry(void)
+{
+ u32 retry_cnt;
+
+ union cvmx_pemx_ctl_status pemx_ctl;
+ pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
+ retry_cnt = pemx_ctl.s.cfg_rtry;
+ pemx_ctl.s.cfg_rtry = 0;
+ cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
+ return retry_cnt;
+}
+
+static int is_cfg_retry(void)
+{
+ union cvmx_pemx_int_sum pemx_int_sum;
+ pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1));
+ if (pemx_int_sum.s.crs_dr)
+ return 1;
+ return 0;
+}
+
+/*
* Read a value from configuration space
*
- * @bus:
- * @devfn:
- * @reg:
- * @size:
- * @val:
- * Returns
*/
-static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
- unsigned int devfn, int reg, int size,
- u32 *val)
+static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus,
+ unsigned int devfn, int reg, int size,
+ u32 *val)
{
union octeon_cvmemctl cvmmemctl;
union octeon_cvmemctl cvmmemctl_save;
int bus_number = bus->number;
+ int cfg_retry = 0;
+ int retry_cnt = 0;
+ int max_retry_cnt = 10;
+ u32 cfg_retry_cnt = 0;
+ cvmmemctl_save.u64 = 0;
+ BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
/*
* For the top level bus make sure our hardware bus number
- * matches the software one.
+ * matches the software one
*/
if (bus->parent == NULL) {
- union cvmx_pciercx_cfg006 pciercx_cfg006;
- pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
- CVMX_PCIERCX_CFG006(pcie_port));
- if (pciercx_cfg006.s.pbnum != bus_number) {
- pciercx_cfg006.s.pbnum = bus_number;
- pciercx_cfg006.s.sbnum = bus_number;
- pciercx_cfg006.s.subbnum = bus_number;
- cvmx_pcie_cfgx_write(pcie_port,
- CVMX_PCIERCX_CFG006(pcie_port),
- pciercx_cfg006.u32);
+ if (enable_pcie_bus_num_war[pcie_port])
+ bus_number = 0;
+ else {
+ union cvmx_pciercx_cfg006 pciercx_cfg006;
+ pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
+ CVMX_PCIERCX_CFG006(pcie_port));
+ if (pciercx_cfg006.s.pbnum != bus_number) {
+ pciercx_cfg006.s.pbnum = bus_number;
+ pciercx_cfg006.s.sbnum = bus_number;
+ pciercx_cfg006.s.subbnum = bus_number;
+ cvmx_pcie_cfgx_write(pcie_port,
+ CVMX_PCIERCX_CFG006(pcie_port),
+ pciercx_cfg006.u32);
+ }
}
}
@@ -1116,29 +1605,52 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
*/
#if 1
/* Use this option if you aren't using either slot */
- if (bus_number == 1)
+ if (bus_number == 2)
return PCIBIOS_FUNC_NOT_SUPPORTED;
#elif 0
/*
* Use this option if you are using the first slot but
* not the second.
*/
- if ((bus_number == 1) && (devfn >> 3 != 2))
+ if ((bus_number == 2) && (devfn >> 3 != 2))
return PCIBIOS_FUNC_NOT_SUPPORTED;
#elif 0
/*
* Use this option if you are using the second slot
* but not the first.
*/
- if ((bus_number == 1) && (devfn >> 3 != 3))
+ if ((bus_number == 2) && (devfn >> 3 != 3))
return PCIBIOS_FUNC_NOT_SUPPORTED;
#elif 0
/* Use this opion if you are using both slots */
- if ((bus_number == 1) &&
+ if ((bus_number == 2) &&
!((devfn == (2 << 3)) || (devfn == (3 << 3))))
return PCIBIOS_FUNC_NOT_SUPPORTED;
#endif
+ /* The following #if gives a more complicated example. This is
+ the required checks for running a Nitrox CN16XX-NHBX in the
+ slot of the EBH5600. This card has a PLX PCIe bridge with
+ four Nitrox PLX parts behind it */
+#if 0
+ /* PLX bridge with 4 ports */
+ if ((bus_number == 4) &&
+ !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ /* Nitrox behind PLX 1 */
+ if ((bus_number == 5) && (devfn >> 3 != 0))
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ /* Nitrox behind PLX 2 */
+ if ((bus_number == 6) && (devfn >> 3 != 0))
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ /* Nitrox behind PLX 3 */
+ if ((bus_number == 7) && (devfn >> 3 != 0))
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ /* Nitrox behind PLX 4 */
+ if ((bus_number == 8) && (devfn >> 3 != 0))
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+#endif
+
/*
* Shorten the DID timeout so bus errors for PCIe
* config reads from non existent devices happen
@@ -1152,26 +1664,48 @@ static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
__write_64bit_c0_register($11, 7, cvmmemctl.u64);
}
- switch (size) {
- case 4:
- *val = cvmx_pcie_config_read32(pcie_port, bus_number,
- devfn >> 3, devfn & 0x7, reg);
+ if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
+ cfg_retry_cnt = disable_cfg_read_retry();
+
+ pr_debug("pcie_cfg_rd port=%d b=%d devfn=0x%03x reg=0x%03x"
+ " size=%d ", pcie_port, bus_number, devfn, reg, size);
+ do {
+ switch (size) {
+ case 4:
+ *val = cvmx_pcie_config_read32(pcie_port, bus_number,
+ devfn >> 3, devfn & 0x7, reg);
break;
- case 2:
- *val = cvmx_pcie_config_read16(pcie_port, bus_number,
- devfn >> 3, devfn & 0x7, reg);
+ case 2:
+ *val = cvmx_pcie_config_read16(pcie_port, bus_number,
+ devfn >> 3, devfn & 0x7, reg);
break;
- case 1:
- *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
- devfn & 0x7, reg);
+ case 1:
+ *val = cvmx_pcie_config_read8(pcie_port, bus_number,
+ devfn >> 3, devfn & 0x7, reg);
break;
- default:
- return PCIBIOS_FUNC_NOT_SUPPORTED;
- }
+ default:
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX))
+ set_cfg_read_retry(cfg_retry_cnt);
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+ }
+ if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) &&
+ (enable_pcie_14459_war)) {
+ cfg_retry = is_cfg_retry();
+ retry_cnt++;
+ if (retry_cnt > max_retry_cnt) {
+ pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n",
+ retry_cnt);
+ cfg_retry = 0;
+ }
+ }
+ } while (cfg_retry);
+ if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
+ set_cfg_read_retry(cfg_retry_cnt);
+ pr_debug("val=%08x : tries=%02d\n", *val, retry_cnt);
if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
- __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
+ write_c0_cvmmemctl(cvmmemctl_save.u64);
return PCIBIOS_SUCCESSFUL;
}
@@ -1187,42 +1721,56 @@ static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
}
+static int octeon_dummy_read_config(struct pci_bus *bus, unsigned int devfn,
+ int reg, int size, u32 *val)
+{
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+}
-
-/**
+/*
* Write a value to PCI configuration space
- *
- * @bus:
- * @devfn:
- * @reg:
- * @size:
- * @val:
- * Returns
*/
-static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
- unsigned int devfn, int reg,
- int size, u32 val)
+static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
+ unsigned int devfn, int reg,
+ int size, u32 val)
{
int bus_number = bus->number;
+ BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
+
+ if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))
+ bus_number = 0;
+
+ pr_debug("pcie_cfg_wr port=%d b=%d devfn=0x%03x"
+ " reg=0x%03x size=%d val=%08x\n", pcie_port, bus_number, devfn,
+ reg, size, val);
+
+
switch (size) {
case 4:
cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
devfn & 0x7, reg, val);
- return PCIBIOS_SUCCESSFUL;
+ break;
case 2:
cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
devfn & 0x7, reg, val);
- return PCIBIOS_SUCCESSFUL;
+ break;
case 1:
cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
devfn & 0x7, reg, val);
- return PCIBIOS_SUCCESSFUL;
+ break;
+ default:
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
}
#if PCI_CONFIG_SPACE_DELAY
+ /*
+ * Delay on writes so that devices have time to come up. Some
+ * bridges need this to allow time for the secondary busses to
+ * work
+ */
udelay(PCI_CONFIG_SPACE_DELAY);
#endif
- return PCIBIOS_FUNC_NOT_SUPPORTED;
+ return PCIBIOS_SUCCESSFUL;
}
static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -1237,6 +1785,12 @@ static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
}
+static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn,
+ int reg, int size, u32 val)
+{
+ return PCIBIOS_FUNC_NOT_SUPPORTED;
+}
+
static struct pci_ops octeon_pcie0_ops = {
octeon_pcie0_read_config,
octeon_pcie0_write_config,
@@ -1279,6 +1833,35 @@ static struct pci_controller octeon_pcie1_controller = {
.io_resource = &octeon_pcie1_io_resource,
};
+static struct pci_ops octeon_dummy_ops = {
+ octeon_dummy_read_config,
+ octeon_dummy_write_config,
+};
+
+static struct resource octeon_dummy_mem_resource = {
+ .name = "Virtual PCIe MEM",
+ .flags = IORESOURCE_MEM,
+};
+
+static struct resource octeon_dummy_io_resource = {
+ .name = "Virtual PCIe IO",
+ .flags = IORESOURCE_IO,
+};
+
+static struct pci_controller octeon_dummy_controller = {
+ .pci_ops = &octeon_dummy_ops,
+ .mem_resource = &octeon_dummy_mem_resource,
+ .io_resource = &octeon_dummy_io_resource,
+};
+
+static int device_needs_bus_num_war(uint32_t deviceid)
+{
+#define IDT_VENDOR_ID 0x111d
+
+ if ((deviceid & 0xffff) == IDT_VENDOR_ID)
+ return 1;
+ return 0;
+}
/**
* Initialize the Octeon PCIe controllers
@@ -1287,19 +1870,27 @@ static struct pci_controller octeon_pcie1_controller = {
*/
static int __init octeon_pcie_setup(void)
{
- union cvmx_npei_ctl_status npei_ctl_status;
int result;
+ int host_mode;
+ int srio_war15205 = 0, port;
+ union cvmx_sli_ctl_portx sli_ctl_portx;
+ union cvmx_sriox_status_reg sriox_status_reg;
/* These chips don't have PCIe */
if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
return 0;
+ /* No PCIe simulation */
+ if (octeon_is_simulation())
+ return 0;
+
+ /* Disable PCI if instructed on the command line */
+ if (pcie_disable)
+ return 0;
+
/* Point pcibios_map_irq() to the PCIe version of it */
octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
- /* Use the PCIe based DMA mappings */
- octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
-
/*
* PCIe I/O range. It is based on port 0 but includes up until
* port 1's end.
@@ -1310,11 +1901,43 @@ static int __init octeon_pcie_setup(void)
cvmx_pcie_get_io_base_address(1) -
cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
- npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
- if (npei_ctl_status.s.host_mode) {
+ /*
+ * Create a dummy PCIe controller to swallow up bus 0. IDT bridges
+ * don't work if the primary bus number is zero. Here we add a fake
+ * PCIe controller that the kernel will give bus 0. This allows
+ * us to not change the normal kernel bus enumeration
+ */
+ octeon_dummy_controller.io_map_base = -1;
+ octeon_dummy_controller.mem_resource->start = (1ull<<48);
+ octeon_dummy_controller.mem_resource->end = (1ull<<48);
+ register_pci_controller(&octeon_dummy_controller);
+
+ if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+ union cvmx_npei_ctl_status npei_ctl_status;
+ npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
+ host_mode = npei_ctl_status.s.host_mode;
+ octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
+ } else {
+ union cvmx_mio_rst_ctlx mio_rst_ctl;
+ mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0));
+ host_mode = mio_rst_ctl.s.host_mode;
+ octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE2;
+ }
+
+ if (host_mode) {
pr_notice("PCIe: Initializing port 0\n");
+ /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+ sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
+ if (sriox_status_reg.s.srio) {
+ srio_war15205 += 1; /* Port is SRIO */
+ port = 0;
+ }
+ }
result = cvmx_pcie_rc_initialize(0);
if (result == 0) {
+ uint32_t device0;
/* Memory offsets are physical addresses */
octeon_pcie0_controller.mem_offset =
cvmx_pcie_get_mem_base_address(0);
@@ -1343,60 +1966,134 @@ static int __init octeon_pcie_setup(void)
octeon_pcie0_controller.io_resource->start = 4 << 10;
octeon_pcie0_controller.io_resource->end =
cvmx_pcie_get_io_size(0) - 1;
+ msleep(100); /* Some devices need extra time */
register_pci_controller(&octeon_pcie0_controller);
+ device0 = cvmx_pcie_config_read32(0, 0, 0, 0, 0);
+ enable_pcie_bus_num_war[0] =
+ device_needs_bus_num_war(device0);
}
} else {
pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
+ /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+ srio_war15205 += 1;
+ port = 0;
+ }
}
- /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
- if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
- union cvmx_npei_dbg_data npei_dbg_data;
- npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
- if (npei_dbg_data.cn52xx.qlm0_link_width)
- return 0;
+ if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
+ host_mode = 1;
+ /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
+ if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+ union cvmx_npei_dbg_data dbg_data;
+ dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
+ if (dbg_data.cn52xx.qlm0_link_width)
+ host_mode = 0;
+ }
+ } else {
+ union cvmx_mio_rst_ctlx mio_rst_ctl;
+ mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1));
+ host_mode = mio_rst_ctl.s.host_mode;
}
- pr_notice("PCIe: Initializing port 1\n");
- result = cvmx_pcie_rc_initialize(1);
- if (result == 0) {
- /* Memory offsets are physical addresses */
- octeon_pcie1_controller.mem_offset =
- cvmx_pcie_get_mem_base_address(1);
- /* IO offsets are Mips virtual addresses */
- octeon_pcie1_controller.io_map_base =
- CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
- octeon_pcie1_controller.io_offset =
- cvmx_pcie_get_io_base_address(1) -
- cvmx_pcie_get_io_base_address(0);
- /*
- * To keep things similar to PCI, we start device
- * addresses at the same place as PCI uisng big bar
- * support. This normally translates to 4GB-256MB,
- * which is the same as most x86 PCs.
- */
- octeon_pcie1_controller.mem_resource->start =
- cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
- (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
- octeon_pcie1_controller.mem_resource->end =
- cvmx_pcie_get_mem_base_address(1) +
- cvmx_pcie_get_mem_size(1) - 1;
- /*
- * Ports must be above 16KB for the ISA bus filtering
- * in the PCI-X to PCI bridge.
- */
- octeon_pcie1_controller.io_resource->start =
- cvmx_pcie_get_io_base_address(1) -
- cvmx_pcie_get_io_base_address(0);
- octeon_pcie1_controller.io_resource->end =
- octeon_pcie1_controller.io_resource->start +
- cvmx_pcie_get_io_size(1) - 1;
- register_pci_controller(&octeon_pcie1_controller);
+ if (host_mode) {
+ pr_notice("PCIe: Initializing port 1\n");
+ /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+ sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
+ if (sriox_status_reg.s.srio) {
+ srio_war15205 += 1; /* Port is SRIO */
+ port = 1;
+ }
+ }
+ result = cvmx_pcie_rc_initialize(1);
+ if (result == 0) {
+ uint32_t device0;
+ /* Memory offsets are physical addresses */
+ octeon_pcie1_controller.mem_offset =
+ cvmx_pcie_get_mem_base_address(1);
+ /*
+ * To calculate the address for accessing the 2nd PCIe device,
+ * either 'io_map_base' (pci_iomap()), or 'mips_io_port_base'
+ * (ioport_map()) value is added to
+ * pci_resource_start(dev,bar)). The 'mips_io_port_base' is set
+ * only once based on first PCIe. Also changing 'io_map_base'
+ * based on first slot's value so that both the routines will
+ * work properly.
+ */
+ octeon_pcie1_controller.io_map_base =
+ CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0));
+ /* IO offsets are Mips virtual addresses */
+ octeon_pcie1_controller.io_offset =
+ cvmx_pcie_get_io_base_address(1) -
+ cvmx_pcie_get_io_base_address(0);
+ /*
+ * To keep things similar to PCI, we start device
+ * addresses at the same place as PCI uisng big bar
+ * support. This normally translates to 4GB-256MB,
+ * which is the same as most x86 PCs.
+ */
+ octeon_pcie1_controller.mem_resource->start =
+ cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
+ (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
+ octeon_pcie1_controller.mem_resource->end =
+ cvmx_pcie_get_mem_base_address(1) +
+ cvmx_pcie_get_mem_size(1) - 1;
+ /*
+ * Ports must be above 16KB for the ISA bus filtering
+ * in the PCI-X to PCI bridge.
+ */
+ octeon_pcie1_controller.io_resource->start =
+ cvmx_pcie_get_io_base_address(1) -
+ cvmx_pcie_get_io_base_address(0);
+ octeon_pcie1_controller.io_resource->end =
+ octeon_pcie1_controller.io_resource->start +
+ cvmx_pcie_get_io_size(1) - 1;
+ msleep(100); /* Some devices need extra time */
+ register_pci_controller(&octeon_pcie1_controller);
+ device0 = cvmx_pcie_config_read32(1, 0, 0, 0, 0);
+ enable_pcie_bus_num_war[1] =
+ device_needs_bus_num_war(device0);
+ }
+ } else {
+ pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n");
+ /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+ srio_war15205 += 1;
+ port = 1;
+ }
+ }
+
+ /*
+ * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all
+ * of SRIO MACs SLI_CTL_PORT*[INT*_MAP] to similar value and
+ * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value
+ * from the previous set values
+ */
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
+ if (srio_war15205 == 1) {
+ sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port));
+ sli_ctl_portx.s.inta_map = 1;
+ sli_ctl_portx.s.intb_map = 1;
+ sli_ctl_portx.s.intc_map = 1;
+ sli_ctl_portx.s.intd_map = 1;
+ cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64);
+
+ sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port));
+ sli_ctl_portx.s.inta_map = 0;
+ sli_ctl_portx.s.intb_map = 0;
+ sli_ctl_portx.s.intc_map = 0;
+ sli_ctl_portx.s.intd_map = 0;
+ cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64);
+ }
}
octeon_pci_dma_init();
return 0;
}
-
arch_initcall(octeon_pcie_setup);
--
1.7.2.3
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definitions for new chips.
2011-11-15 23:46 ` [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definitions for new chips ddaney.cavm
@ 2011-11-16 0:59 ` Ralf Baechle
0 siblings, 0 replies; 11+ messages in thread
From: Ralf Baechle @ 2011-11-16 0:59 UTC (permalink / raw)
To: ddaney.cavm; +Cc: linux-mips, David Daney
Queued for 3.3. Thanks,
Ralf
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/5] MIPS: Octeon: Update feature test functions for new chips and features.
2011-11-15 23:46 ` [PATCH 2/5] MIPS: Octeon: Update feature test functions for new chips and features ddaney.cavm
@ 2011-11-16 1:00 ` Ralf Baechle
0 siblings, 0 replies; 11+ messages in thread
From: Ralf Baechle @ 2011-11-16 1:00 UTC (permalink / raw)
To: ddaney.cavm; +Cc: linux-mips, David Daney
Queued for 3.3. Thanks,
Ralf
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/5] MIPS: Octeon: Update DMA mapping operations for OCTEON II processors.
2011-11-15 23:46 ` [PATCH 3/5] MIPS: Octeon: Update DMA mapping operations for OCTEON II processors ddaney.cavm
@ 2011-11-16 1:00 ` Ralf Baechle
0 siblings, 0 replies; 11+ messages in thread
From: Ralf Baechle @ 2011-11-16 1:00 UTC (permalink / raw)
To: ddaney.cavm; +Cc: linux-mips, David Daney, David Daney
Queued for 3.3. Thanks,
Ralf
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/5] MIPS: Octeon: Update PCI Latency timer, PCIe payload, and PCIe max read to allow larger transactions
2011-11-15 23:46 ` [PATCH 4/5] MIPS: Octeon: Update PCI Latency timer, PCIe payload, and PCIe max read to allow larger transactions ddaney.cavm
@ 2011-11-16 1:00 ` Ralf Baechle
0 siblings, 0 replies; 11+ messages in thread
From: Ralf Baechle @ 2011-11-16 1:00 UTC (permalink / raw)
To: ddaney.cavm; +Cc: linux-mips, David Daney, David Daney
Queued for 3.3. Thanks,
Ralf
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 5/5] MIPS: Octeon: Add support for OCTEON II PCIe
2011-11-15 23:46 ` [PATCH 5/5] MIPS: Octeon: Add support for OCTEON II PCIe ddaney.cavm
@ 2011-11-16 1:00 ` Ralf Baechle
0 siblings, 0 replies; 11+ messages in thread
From: Ralf Baechle @ 2011-11-16 1:00 UTC (permalink / raw)
To: ddaney.cavm; +Cc: linux-mips, David Daney
Queued for 3.3. Thanks,
Ralf
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2011-11-16 1:01 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-11-15 23:46 [PATCH 0/5] MIPS: Octeon: PCI{,e} updates for Octeon II SOCs ddaney.cavm
2011-11-15 23:46 ` [PATCH 1/5] MIPS: Octeon: Update SOC PCI related register definitions for new chips ddaney.cavm
2011-11-16 0:59 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 2/5] MIPS: Octeon: Update feature test functions for new chips and features ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 3/5] MIPS: Octeon: Update DMA mapping operations for OCTEON II processors ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 4/5] MIPS: Octeon: Update PCI Latency timer, PCIe payload, and PCIe max read to allow larger transactions ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
2011-11-15 23:46 ` [PATCH 5/5] MIPS: Octeon: Add support for OCTEON II PCIe ddaney.cavm
2011-11-16 1:00 ` Ralf Baechle
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