From: Dave Martin <dave.martin@linaro.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Russell King <linux@arm.linux.org.uk>,
Nicolas Pitre <nicolas.pitre@linaro.org>,
Colin Cross <ccross@android.com>,
Santosh Shilimkar <santosh.shilimkar@ti.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Amit Kucheria <amit.kucheria@linaro.org>,
Wenzeng Chen <wzch@marvell.com>
Subject: Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
Date: Wed, 19 Sep 2012 14:46:58 +0100 [thread overview]
Message-ID: <20120919134658.GA2111@linaro.org> (raw)
In-Reply-To: <1347986135-17979-4-git-send-email-lorenzo.pieralisi@arm.com>
On Tue, Sep 18, 2012 at 05:35:33PM +0100, Lorenzo Pieralisi wrote:
> In processors like A15/A7 L2 cache is unified and integrated within the
> processor cache hierarchy, so that it is not considered an outer cache
> anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
> all cache levels up to Level of Coherency (LoC) that includes
> the L2 unified cache.
>
> When a single CPU is suspended (CPU idle) a complete L2 clean is not
> required, so generic cpu_suspend code must clean the data cache using the
> newly introduced cache LoUIS function.
For patches 3-5 in this series, we know that the assumption that
flushing LoUIS is sufficient for safely powering the CPU down is not
valid in the general case, though we've agreed it's a sensible
compromise for the CPU variants we know about today.
I think we do need to document this assumption, though.
At this point I don't mind whether it appears in code comments or in the
commit messages.
Cheers
---Dave
>
> The context and stack pointer (context pointer) are cleaned to main memory
> using cache area functions that operate on MVA and guarantee that the data
> is written back to main memory (perform cache cleaning up to the Point of
> Coherency - PoC) so that the processor can fetch the context when the MMU
> is off in the cpu_resume code path.
>
> outer_cache management remains unchanged.
>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> arch/arm/kernel/suspend.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
> index 1794cc3..358bca3 100644
> --- a/arch/arm/kernel/suspend.c
> +++ b/arch/arm/kernel/suspend.c
> @@ -17,6 +17,8 @@ extern void cpu_resume_mmu(void);
> */
> void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
> {
> + u32 *ctx = ptr;
> +
> *save_ptr = virt_to_phys(ptr);
>
> /* This must correspond to the LDM in cpu_resume() assembly */
> @@ -26,7 +28,20 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
>
> cpu_do_suspend(ptr);
>
> - flush_cache_all();
> + flush_cache_louis();
> +
> + /*
> + * flush_cache_louis does not guarantee that
> + * save_ptr and ptr are cleaned to main memory,
> + * just up to the Level of Unification Inner Shareable.
> + * Since the context pointer and context itself
> + * are to be retrieved with the MMU off that
> + * data must be cleaned from all cache levels
> + * to main memory using "area" cache primitives.
> + */
> + __cpuc_flush_dcache_area(ctx, ptrsz);
> + __cpuc_flush_dcache_area(save_ptr, sizeof(*save_ptr));
> +
> outer_clean_range(*save_ptr, *save_ptr + ptrsz);
> outer_clean_range(virt_to_phys(save_ptr),
> virt_to_phys(save_ptr) + sizeof(*save_ptr));
> --
> 1.7.12
>
>
WARNING: multiple messages have this Message-ID (diff)
From: dave.martin@linaro.org (Dave Martin)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
Date: Wed, 19 Sep 2012 14:46:58 +0100 [thread overview]
Message-ID: <20120919134658.GA2111@linaro.org> (raw)
In-Reply-To: <1347986135-17979-4-git-send-email-lorenzo.pieralisi@arm.com>
On Tue, Sep 18, 2012 at 05:35:33PM +0100, Lorenzo Pieralisi wrote:
> In processors like A15/A7 L2 cache is unified and integrated within the
> processor cache hierarchy, so that it is not considered an outer cache
> anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
> all cache levels up to Level of Coherency (LoC) that includes
> the L2 unified cache.
>
> When a single CPU is suspended (CPU idle) a complete L2 clean is not
> required, so generic cpu_suspend code must clean the data cache using the
> newly introduced cache LoUIS function.
For patches 3-5 in this series, we know that the assumption that
flushing LoUIS is sufficient for safely powering the CPU down is not
valid in the general case, though we've agreed it's a sensible
compromise for the CPU variants we know about today.
I think we do need to document this assumption, though.
At this point I don't mind whether it appears in code comments or in the
commit messages.
Cheers
---Dave
>
> The context and stack pointer (context pointer) are cleaned to main memory
> using cache area functions that operate on MVA and guarantee that the data
> is written back to main memory (perform cache cleaning up to the Point of
> Coherency - PoC) so that the processor can fetch the context when the MMU
> is off in the cpu_resume code path.
>
> outer_cache management remains unchanged.
>
> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> arch/arm/kernel/suspend.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
> index 1794cc3..358bca3 100644
> --- a/arch/arm/kernel/suspend.c
> +++ b/arch/arm/kernel/suspend.c
> @@ -17,6 +17,8 @@ extern void cpu_resume_mmu(void);
> */
> void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
> {
> + u32 *ctx = ptr;
> +
> *save_ptr = virt_to_phys(ptr);
>
> /* This must correspond to the LDM in cpu_resume() assembly */
> @@ -26,7 +28,20 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
>
> cpu_do_suspend(ptr);
>
> - flush_cache_all();
> + flush_cache_louis();
> +
> + /*
> + * flush_cache_louis does not guarantee that
> + * save_ptr and ptr are cleaned to main memory,
> + * just up to the Level of Unification Inner Shareable.
> + * Since the context pointer and context itself
> + * are to be retrieved with the MMU off that
> + * data must be cleaned from all cache levels
> + * to main memory using "area" cache primitives.
> + */
> + __cpuc_flush_dcache_area(ctx, ptrsz);
> + __cpuc_flush_dcache_area(save_ptr, sizeof(*save_ptr));
> +
> outer_clean_range(*save_ptr, *save_ptr + ptrsz);
> outer_clean_range(virt_to_phys(save_ptr),
> virt_to_phys(save_ptr) + sizeof(*save_ptr));
> --
> 1.7.12
>
>
next prev parent reply other threads:[~2012-09-19 13:47 UTC|newest]
Thread overview: 97+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-18 16:35 [RFC PATCH v2 0/5] ARM: augment cache flushing API Lorenzo Pieralisi
2012-09-18 16:35 ` Lorenzo Pieralisi
2012-09-18 16:35 ` [RFC PATCH v2 1/5] ARM: mm: implement LoUIS API for cache maintenance ops Lorenzo Pieralisi
2012-09-18 16:35 ` Lorenzo Pieralisi
2012-09-18 18:12 ` Nicolas Pitre
2012-09-18 18:12 ` Nicolas Pitre
2012-09-19 12:30 ` Lorenzo Pieralisi
2012-09-19 12:30 ` Lorenzo Pieralisi
2012-09-18 16:35 ` [RFC PATCH v2 2/5] ARM: mm: rename jump labels in v7_flush_dcache_all function Lorenzo Pieralisi
2012-09-18 16:35 ` Lorenzo Pieralisi
2012-09-18 18:13 ` Nicolas Pitre
2012-09-18 18:13 ` Nicolas Pitre
2012-09-19 13:51 ` Dave Martin
2012-09-19 13:51 ` Dave Martin
2012-09-20 10:32 ` Lorenzo Pieralisi
2012-09-20 10:32 ` Lorenzo Pieralisi
2012-09-20 11:01 ` Dave Martin
2012-09-20 11:01 ` Dave Martin
2012-09-18 16:35 ` [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations Lorenzo Pieralisi
2012-09-18 16:35 ` Lorenzo Pieralisi
2012-09-18 18:18 ` Nicolas Pitre
2012-09-18 18:18 ` Nicolas Pitre
2012-09-19 13:46 ` Dave Martin [this message]
2012-09-19 13:46 ` Dave Martin
2012-09-20 10:25 ` Lorenzo Pieralisi
2012-09-20 10:25 ` Lorenzo Pieralisi
2012-09-20 11:04 ` Dave Martin
2012-09-20 11:04 ` Dave Martin
2012-12-11 16:07 ` Guennadi Liakhovetski
2012-12-11 16:07 ` Guennadi Liakhovetski
2012-12-11 16:07 ` Guennadi Liakhovetski
2012-12-11 16:33 ` Will Deacon
2012-12-11 16:33 ` Will Deacon
2012-12-11 16:33 ` Will Deacon
2012-12-11 16:38 ` Will Deacon
2012-12-11 16:38 ` Will Deacon
2012-12-11 16:38 ` Will Deacon
2012-12-11 17:07 ` Guennadi Liakhovetski
2012-12-11 17:07 ` Guennadi Liakhovetski
2012-12-11 17:07 ` Guennadi Liakhovetski
2012-12-11 17:47 ` Will Deacon
2012-12-11 17:47 ` Will Deacon
2012-12-11 17:47 ` Will Deacon
2012-12-11 17:55 ` Guennadi Liakhovetski
2012-12-11 17:55 ` Guennadi Liakhovetski
2012-12-11 17:55 ` Guennadi Liakhovetski
2012-12-11 23:27 ` Stephen Boyd
2012-12-11 23:27 ` Stephen Boyd
2012-12-11 23:27 ` Stephen Boyd
2012-12-12 10:31 ` Will Deacon
2012-12-12 10:31 ` Will Deacon
2012-12-12 10:31 ` Will Deacon
2012-12-12 16:43 ` Guennadi Liakhovetski
2012-12-12 16:43 ` Guennadi Liakhovetski
2012-12-12 16:43 ` Guennadi Liakhovetski
2012-12-12 10:33 ` Lorenzo Pieralisi
2012-12-12 10:33 ` Lorenzo Pieralisi
2012-12-12 10:33 ` Lorenzo Pieralisi
2012-12-12 13:36 ` Will Deacon
2012-12-12 13:36 ` Will Deacon
2012-12-12 13:36 ` Will Deacon
2012-12-13 8:09 ` Guennadi Liakhovetski
2012-12-13 8:09 ` Guennadi Liakhovetski
2012-12-13 8:09 ` Guennadi Liakhovetski
2012-12-13 10:51 ` Will Deacon
2012-12-13 10:51 ` Will Deacon
2012-12-13 10:51 ` Will Deacon
2012-12-13 14:32 ` Guennadi Liakhovetski
2012-12-13 14:32 ` Guennadi Liakhovetski
2012-12-13 14:32 ` Guennadi Liakhovetski
2012-12-13 14:39 ` Santosh Shilimkar
2012-12-13 14:39 ` Santosh Shilimkar
2012-12-13 14:39 ` Santosh Shilimkar
2012-12-28 11:32 ` [PATCH v2] ARM: sh7372: fix cache clean / invalidate order Guennadi Liakhovetski
2012-12-28 11:32 ` Guennadi Liakhovetski
2012-12-28 11:32 ` Guennadi Liakhovetski
2012-12-28 21:50 ` Simon Horman
2012-12-28 21:50 ` Simon Horman
2012-12-28 21:50 ` Simon Horman
2012-12-13 14:52 ` [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations Will Deacon
2012-12-13 14:52 ` Will Deacon
2012-12-13 14:52 ` Will Deacon
2012-12-12 16:43 ` Guennadi Liakhovetski
2012-12-12 16:43 ` Guennadi Liakhovetski
2012-12-12 16:43 ` Guennadi Liakhovetski
2012-09-18 16:35 ` [RFC PATCH v2 4/5] ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API Lorenzo Pieralisi
2012-09-18 16:35 ` Lorenzo Pieralisi
2012-09-18 18:19 ` Nicolas Pitre
2012-09-18 18:19 ` Nicolas Pitre
2012-09-18 16:35 ` [RFC PATCH v2 5/5] ARM: mm: update __v7_setup() to the new LoUIS cache " Lorenzo Pieralisi
2012-09-18 16:35 ` Lorenzo Pieralisi
2012-09-18 18:20 ` Nicolas Pitre
2012-09-18 18:20 ` Nicolas Pitre
2012-09-20 11:27 ` [RFC PATCH v2 0/5] ARM: augment cache flushing API Lorenzo Pieralisi
2012-09-20 11:27 ` Lorenzo Pieralisi
2012-09-21 8:07 ` Shawn Guo
2012-09-21 8:07 ` Shawn Guo
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