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* [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
@ 2013-02-14 19:53 ville.syrjala
  2013-02-14 22:46 ` Ben Widawsky
  0 siblings, 1 reply; 5+ messages in thread
From: ville.syrjala @ 2013-02-14 19:53 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The bit controlling whether PIPE_CONTROL DW/QW write targets
the global GTT or PPGTT moved moved from DW 2 bit 2 to
DW 1 bit 24 on IVB.

I verified on IVB that the fix is in fact effective. Without the fix
none of the scratch writes actually landed in the pipe control page.
With the fix the writes show up correctly.

v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         | 1 +
 drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d7542cd..69a95c6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -308,6 +308,7 @@
 #define   DISPLAY_PLANE_A           (0<<20)
 #define   DISPLAY_PLANE_B           (1<<20)
 #define GFX_OP_PIPE_CONTROL(len)	((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
+#define   PIPE_CONTROL_GLOBAL_GTT_IVB			(1<<24) /* gen7+ */
 #define   PIPE_CONTROL_CS_STALL				(1<<20)
 #define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
 #define   PIPE_CONTROL_QW_WRITE				(1<<14)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9b8b058..1d5d613 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -318,6 +318,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
 		 * TLB invalidate requires a post-sync write.
 		 */
 		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 
 		/* Workaround: we must issue a pipe_control with CS-stall bit
 		 * set before a pipe_control command that has the state cache
@@ -331,7 +332,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
 
 	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 	intel_ring_emit(ring, flags);
-	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
+	intel_ring_emit(ring, scratch_addr);
 	intel_ring_emit(ring, 0);
 	intel_ring_advance(ring);
 
-- 
1.7.12.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
  2013-02-14 19:53 [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ ville.syrjala
@ 2013-02-14 22:46 ` Ben Widawsky
  2013-02-15 10:10   ` Daniel Vetter
  2013-02-19 23:59   ` Ben Widawsky
  0 siblings, 2 replies; 5+ messages in thread
From: Ben Widawsky @ 2013-02-14 22:46 UTC (permalink / raw)
  To: ville.syrjala; +Cc: intel-gfx

On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The bit controlling whether PIPE_CONTROL DW/QW write targets
> the global GTT or PPGTT moved moved from DW 2 bit 2 to
> DW 1 bit 24 on IVB.
> 
> I verified on IVB that the fix is in fact effective. Without the fix
> none of the scratch writes actually landed in the pipe control page.
> With the fix the writes show up correctly.
> 
> v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[snip]
-- 
Ben Widawsky, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
  2013-02-14 22:46 ` Ben Widawsky
@ 2013-02-15 10:10   ` Daniel Vetter
  2013-02-19 23:59   ` Ben Widawsky
  1 sibling, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2013-02-15 10:10 UTC (permalink / raw)
  To: Ben Widawsky; +Cc: intel-gfx

On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote:
> On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The bit controlling whether PIPE_CONTROL DW/QW write targets
> > the global GTT or PPGTT moved moved from DW 2 bit 2 to
> > DW 1 bit 24 on IVB.
> > 
> > I verified on IVB that the fix is in fact effective. Without the fix
> > none of the scratch writes actually landed in the pipe control page.
> > With the fix the writes show up correctly.
> > 
> > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
  2013-02-14 22:46 ` Ben Widawsky
  2013-02-15 10:10   ` Daniel Vetter
@ 2013-02-19 23:59   ` Ben Widawsky
  2013-02-20 14:32     ` Ville Syrjälä
  1 sibling, 1 reply; 5+ messages in thread
From: Ben Widawsky @ 2013-02-19 23:59 UTC (permalink / raw)
  To: ville.syrjala; +Cc: intel-gfx

On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote:
> On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The bit controlling whether PIPE_CONTROL DW/QW write targets
> > the global GTT or PPGTT moved moved from DW 2 bit 2 to
> > DW 1 bit 24 on IVB.
> > 
> > I verified on IVB that the fix is in fact effective. Without the fix
> > none of the scratch writes actually landed in the pipe control page.
> > With the fix the writes show up correctly.
> > 
> > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
> [snip]

Reading the bspec again... do we want to set bit 21?

-- 
Ben Widawsky, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
  2013-02-19 23:59   ` Ben Widawsky
@ 2013-02-20 14:32     ` Ville Syrjälä
  0 siblings, 0 replies; 5+ messages in thread
From: Ville Syrjälä @ 2013-02-20 14:32 UTC (permalink / raw)
  To: Ben Widawsky; +Cc: intel-gfx

On Tue, Feb 19, 2013 at 03:59:16PM -0800, Ben Widawsky wrote:
> On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote:
> > On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > The bit controlling whether PIPE_CONTROL DW/QW write targets
> > > the global GTT or PPGTT moved moved from DW 2 bit 2 to
> > > DW 1 bit 24 on IVB.
> > > 
> > > I verified on IVB that the fix is in fact effective. Without the fix
> > > none of the scratch writes actually landed in the pipe control page.
> > > With the fix the writes show up correctly.
> > > 
> > > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
> > [snip]
> 
> Reading the bspec again... do we want to set bit 21?

I don't think we want to do that. The scratch address we're using here
is a proper GTT address, not an index into the HWS page.

I have no idea why we're not using the HSW page here as well. I couldn't
dig out any reason from the commit logs either. Anyone?

-- 
Ville Syrjälä
Intel OTC

^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2013-02-20 14:33 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2013-02-14 19:53 [PATCH v2] drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+ ville.syrjala
2013-02-14 22:46 ` Ben Widawsky
2013-02-15 10:10   ` Daniel Vetter
2013-02-19 23:59   ` Ben Widawsky
2013-02-20 14:32     ` Ville Syrjälä

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