[kernel-hardening] Re: [PATCH] x86: make IDT read-only

[Ingo Molnar <mingo@kernel.org>]

* Eric W. Biederman <ebiederm@xmission.com> wrote:

> "H. Peter Anvin" <hpa@zytor.com> writes:
> 
> > On 04/08/2013 03:43 PM, Kees Cook wrote:
> >> This makes the IDT unconditionally read-only. This primarily removes
> >> the IDT from being a target for arbitrary memory write attacks. It has
> >> an added benefit of also not leaking (via the "sidt" instruction) the
> >> kernel base offset, if it has been relocated.
> >> 
> >> Signed-off-by: Kees Cook <keescook@chromium.org>
> >> Cc: Eric Northup <digitaleric@google.com>
> >
> > Also, tglx: does this interfere with your per-cpu IDT efforts?
> 
> Given that we don't change any IDT entries why would anyone want a
> per-cpu IDT?  The cache lines should easily be shared accross all
> processors.

That's true iif they are cached.

If not then it's a remote DRAM access cache miss for all CPUs except the node that 
holds that memory.

> Or are there some giant NUMA machines that trigger cache misses when accessing 
> the IDT and the penalty for pulling the cache line across the NUMA fabric is 
> prohibitive?

IDT accesses for pure userspace execution are pretty rare. So we are not just 
talking about huge NUMA machines here but about ordinary NUMA machines taking a 
remote cache miss hit for the first IRQ or other IDT-accessing operation they do 
after some cache-intense user-space processing.

It's a small effect, but it exists and improving it would be legitimate.

Thanks,

	Ingo