* [PATCH 0/3] Add QSPI support on r8a7791/koelsch
@ 2014-01-03 15:34 ` Geert Uytterhoeven
0 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-03 15:34 UTC (permalink / raw)
To: linux-arm-kernel
This series adds support for the Spansion s25fl512s SPI FLASH on the
r8a7791-based Koelsch board:
[1/3] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
[2/3] ARM: shmobile: r8a7791: add QSPI clock
[3/3] ARM: shmobile: Koelsch: Add QSPI support
This applies to non-multiplatform Koelsch only. Multi-platform Koelsch
support will be added when the spi-rspi driver gains DT support.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 1/3] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
2014-01-03 15:34 ` Geert Uytterhoeven
@ 2014-01-03 15:34 ` Geert Uytterhoeven
-1 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-03 15:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 654bef369ab8..0070243c859e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -2135,6 +2135,25 @@ static const unsigned int msiof2_tx_pins[] = {
static const unsigned int msiof2_tx_mux[] = {
MSIOF2_TXD_MARK,
};
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_pins[] = {
+ /* SPCLK, MOSI_IO0, MISO_IO1, IO2, IO3, SSL */
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int qspi_mux[] = {
+ SPCLK_MARK, MOSI_IO0_MARK, MISO_IO1_MARK,
+ IO2_MARK, IO3_MARK, SSL_MARK
+};
+static const unsigned int qspi_b_pins[] = {
+ /* SPCLK, MOSI_IO0, MISO_IO1, IO2, IO3, SSL */
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
+ RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
+};
+static const unsigned int qspi_b_mux[] = {
+ SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
+ IO2_B_MARK, IO3_B_MARK, SSL_B_MARK
+};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX, TX */
@@ -2877,6 +2896,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(msiof2_ss2),
SH_PFC_PIN_GROUP(msiof2_rx),
SH_PFC_PIN_GROUP(msiof2_tx),
+ SH_PFC_PIN_GROUP(qspi),
+ SH_PFC_PIN_GROUP(qspi_b),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_data_b),
SH_PFC_PIN_GROUP(scif0_data_c),
@@ -3074,6 +3095,11 @@ static const char * const msiof2_groups[] = {
"msiof2_tx",
};
+static const char * const qspi_groups[] = {
+ "qspi",
+ "qspi_b",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_data_b",
@@ -3230,6 +3256,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(qspi),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 1/3] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
@ 2014-01-03 15:34 ` Geert Uytterhoeven
0 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-03 15:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 654bef369ab8..0070243c859e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -2135,6 +2135,25 @@ static const unsigned int msiof2_tx_pins[] = {
static const unsigned int msiof2_tx_mux[] = {
MSIOF2_TXD_MARK,
};
+/* - QSPI ------------------------------------------------------------------- */
+static const unsigned int qspi_pins[] = {
+ /* SPCLK, MOSI_IO0, MISO_IO1, IO2, IO3, SSL */
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int qspi_mux[] = {
+ SPCLK_MARK, MOSI_IO0_MARK, MISO_IO1_MARK,
+ IO2_MARK, IO3_MARK, SSL_MARK
+};
+static const unsigned int qspi_b_pins[] = {
+ /* SPCLK, MOSI_IO0, MISO_IO1, IO2, IO3, SSL */
+ RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
+ RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
+};
+static const unsigned int qspi_b_mux[] = {
+ SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
+ IO2_B_MARK, IO3_B_MARK, SSL_B_MARK
+};
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX, TX */
@@ -2877,6 +2896,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(msiof2_ss2),
SH_PFC_PIN_GROUP(msiof2_rx),
SH_PFC_PIN_GROUP(msiof2_tx),
+ SH_PFC_PIN_GROUP(qspi),
+ SH_PFC_PIN_GROUP(qspi_b),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_data_b),
SH_PFC_PIN_GROUP(scif0_data_c),
@@ -3074,6 +3095,11 @@ static const char * const msiof2_groups[] = {
"msiof2_tx",
};
+static const char * const qspi_groups[] = {
+ "qspi",
+ "qspi_b",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_data_b",
@@ -3230,6 +3256,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(qspi),
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif2),
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 1/3] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
2014-01-03 15:34 ` Geert Uytterhoeven
@ 2014-01-07 14:58 ` Laurent Pinchart
-1 siblings, 0 replies; 22+ messages in thread
From: Laurent Pinchart @ 2014-01-07 14:58 UTC (permalink / raw)
To: linux-arm-kernel
Hi Geert,
Thank you for the patch.
On Friday 03 January 2014 16:34:14 Geert Uytterhoeven wrote:
> From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
> drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 654bef369ab8..0070243c859e
> 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> @@ -2135,6 +2135,25 @@ static const unsigned int msiof2_tx_pins[] = {
> static const unsigned int msiof2_tx_mux[] = {
> MSIOF2_TXD_MARK,
> };
> +/* - QSPI
> ------------------------------------------------------------------- */
> +static const unsigned int qspi_pins[] = {
> + /* SPCLK, MOSI_IO0, MISO_IO1, IO2, IO3, SSL */
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
> + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
> +};
The QSPI controller can be used in 1-bit, 2-bit or 4-mode mode, so you should
split the pins group to allow that. You could use one pin group for the
control signals (SPCLK and SSL), one group for 2-bit data (MOSI + MISO, or IO0
+ IO1 depending on the mode) and one group for 4-bit data (IO0 + IO1 + IO2 +
IO3).
I assume that usage of the SSL signal is always required. If that's not the
case the control signals group should be split in two.
Similarly, if the hardware supports "write-only" mode (where the MISO signal
isn't connected), that should be supported through a 1-bit data signals group.
> +static const unsigned int qspi_mux[] = {
> + SPCLK_MARK, MOSI_IO0_MARK, MISO_IO1_MARK,
> + IO2_MARK, IO3_MARK, SSL_MARK
> +};
> +static const unsigned int qspi_b_pins[] = {
> + /* SPCLK, MOSI_IO0, MISO_IO1, IO2, IO3, SSL */
> + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
> + RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
> +};
> +static const unsigned int qspi_b_mux[] = {
> + SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
> + IO2_B_MARK, IO3_B_MARK, SSL_B_MARK
> +};
> /* - SCIF0
> ------------------------------------------------------------------ */
> static const unsigned int scif0_data_pins[] = {
> /* RX, TX */
> @@ -2877,6 +2896,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] > { SH_PFC_PIN_GROUP(msiof2_ss2),
> SH_PFC_PIN_GROUP(msiof2_rx),
> SH_PFC_PIN_GROUP(msiof2_tx),
> + SH_PFC_PIN_GROUP(qspi),
> + SH_PFC_PIN_GROUP(qspi_b),
> SH_PFC_PIN_GROUP(scif0_data),
> SH_PFC_PIN_GROUP(scif0_data_b),
> SH_PFC_PIN_GROUP(scif0_data_c),
> @@ -3074,6 +3095,11 @@ static const char * const msiof2_groups[] = {
> "msiof2_tx",
> };
>
> +static const char * const qspi_groups[] = {
> + "qspi",
> + "qspi_b",
> +};
> +
> static const char * const scif0_groups[] = {
> "scif0_data",
> "scif0_data_b",
> @@ -3230,6 +3256,7 @@ static const struct sh_pfc_function pinmux_functions[]
> = { SH_PFC_FUNCTION(msiof0),
> SH_PFC_FUNCTION(msiof1),
> SH_PFC_FUNCTION(msiof2),
> + SH_PFC_FUNCTION(qspi),
> SH_PFC_FUNCTION(scif0),
> SH_PFC_FUNCTION(scif1),
> SH_PFC_FUNCTION(scif2),
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 1/3] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
@ 2014-01-07 14:58 ` Laurent Pinchart
0 siblings, 0 replies; 22+ messages in thread
From: Laurent Pinchart @ 2014-01-07 14:58 UTC (permalink / raw)
To: linux-arm-kernel
Hi Geert,
Thank you for the patch.
On Friday 03 January 2014 16:34:14 Geert Uytterhoeven wrote:
> From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> ---
> drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 654bef369ab8..0070243c859e
> 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
> @@ -2135,6 +2135,25 @@ static const unsigned int msiof2_tx_pins[] = {
> static const unsigned int msiof2_tx_mux[] = {
> MSIOF2_TXD_MARK,
> };
> +/* - QSPI
> ------------------------------------------------------------------- */
> +static const unsigned int qspi_pins[] = {
> + /* SPCLK, MOSI_IO0, MISO_IO1, IO2, IO3, SSL */
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
> + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
> +};
The QSPI controller can be used in 1-bit, 2-bit or 4-mode mode, so you should
split the pins group to allow that. You could use one pin group for the
control signals (SPCLK and SSL), one group for 2-bit data (MOSI + MISO, or IO0
+ IO1 depending on the mode) and one group for 4-bit data (IO0 + IO1 + IO2 +
IO3).
I assume that usage of the SSL signal is always required. If that's not the
case the control signals group should be split in two.
Similarly, if the hardware supports "write-only" mode (where the MISO signal
isn't connected), that should be supported through a 1-bit data signals group.
> +static const unsigned int qspi_mux[] = {
> + SPCLK_MARK, MOSI_IO0_MARK, MISO_IO1_MARK,
> + IO2_MARK, IO3_MARK, SSL_MARK
> +};
> +static const unsigned int qspi_b_pins[] = {
> + /* SPCLK, MOSI_IO0, MISO_IO1, IO2, IO3, SSL */
> + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
> + RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
> +};
> +static const unsigned int qspi_b_mux[] = {
> + SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
> + IO2_B_MARK, IO3_B_MARK, SSL_B_MARK
> +};
> /* - SCIF0
> ------------------------------------------------------------------ */
> static const unsigned int scif0_data_pins[] = {
> /* RX, TX */
> @@ -2877,6 +2896,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] =
> { SH_PFC_PIN_GROUP(msiof2_ss2),
> SH_PFC_PIN_GROUP(msiof2_rx),
> SH_PFC_PIN_GROUP(msiof2_tx),
> + SH_PFC_PIN_GROUP(qspi),
> + SH_PFC_PIN_GROUP(qspi_b),
> SH_PFC_PIN_GROUP(scif0_data),
> SH_PFC_PIN_GROUP(scif0_data_b),
> SH_PFC_PIN_GROUP(scif0_data_c),
> @@ -3074,6 +3095,11 @@ static const char * const msiof2_groups[] = {
> "msiof2_tx",
> };
>
> +static const char * const qspi_groups[] = {
> + "qspi",
> + "qspi_b",
> +};
> +
> static const char * const scif0_groups[] = {
> "scif0_data",
> "scif0_data_b",
> @@ -3230,6 +3256,7 @@ static const struct sh_pfc_function pinmux_functions[]
> = { SH_PFC_FUNCTION(msiof0),
> SH_PFC_FUNCTION(msiof1),
> SH_PFC_FUNCTION(msiof2),
> + SH_PFC_FUNCTION(qspi),
> SH_PFC_FUNCTION(scif0),
> SH_PFC_FUNCTION(scif1),
> SH_PFC_FUNCTION(scif2),
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 1/3] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
2014-01-07 14:58 ` Laurent Pinchart
@ 2014-01-07 19:53 ` Geert Uytterhoeven
-1 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-07 19:53 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 7, 2014 at 3:58 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>> +static const unsigned int qspi_pins[] = {
>> + /* SPCLK, MOSI_IO0, MISO_IO1, IO2, IO3, SSL */
>> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
>> + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
>> +};
>
> The QSPI controller can be used in 1-bit, 2-bit or 4-mode mode, so you should
> split the pins group to allow that. You could use one pin group for the
> control signals (SPCLK and SSL), one group for 2-bit data (MOSI + MISO, or IO0
> + IO1 depending on the mode) and one group for 4-bit data (IO0 + IO1 + IO2 +
> IO3).
OK, while you can't mix "real" functions (half of the pins are FN2, the other
half FN3), I forgot you can still configure the SoC to use IO2 and IO3 for GPIO.
Will split in qspi_ctrl (2 control wires), qspi_data2 (2 data wires),
and qspi_data4 (4 data wires).
> I assume that usage of the SSL signal is always required. If that's not the
> case the control signals group should be split in two.
>
> Similarly, if the hardware supports "write-only" mode (where the MISO signal
> isn't connected), that should be supported through a 1-bit data signals group.
No, the hardware doesn't support three-wire mode.
Only four-wire (Single/Dual SPI) and six-wire (Quad SPI) are supported.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 1/3] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
@ 2014-01-07 19:53 ` Geert Uytterhoeven
0 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-07 19:53 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jan 7, 2014 at 3:58 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>> +static const unsigned int qspi_pins[] = {
>> + /* SPCLK, MOSI_IO0, MISO_IO1, IO2, IO3, SSL */
>> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
>> + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
>> +};
>
> The QSPI controller can be used in 1-bit, 2-bit or 4-mode mode, so you should
> split the pins group to allow that. You could use one pin group for the
> control signals (SPCLK and SSL), one group for 2-bit data (MOSI + MISO, or IO0
> + IO1 depending on the mode) and one group for 4-bit data (IO0 + IO1 + IO2 +
> IO3).
OK, while you can't mix "real" functions (half of the pins are FN2, the other
half FN3), I forgot you can still configure the SoC to use IO2 and IO3 for GPIO.
Will split in qspi_ctrl (2 control wires), qspi_data2 (2 data wires),
and qspi_data4 (4 data wires).
> I assume that usage of the SSL signal is always required. If that's not the
> case the control signals group should be split in two.
>
> Similarly, if the hardware supports "write-only" mode (where the MISO signal
> isn't connected), that should be supported through a 1-bit data signals group.
No, the hardware doesn't support three-wire mode.
Only four-wire (Single/Dual SPI) and six-wire (Quad SPI) are supported.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 2/3] ARM: shmobile: r8a7791: add QSPI clock
2014-01-03 15:34 ` Geert Uytterhoeven
@ 2014-01-03 15:34 ` Geert Uytterhoeven
-1 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-03 15:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
arch/arm/mach-shmobile/clock-r8a7791.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index f5461262ee25..740c06968994 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -93,6 +93,7 @@ static struct clk main_clk = {
*/
SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
/* fixed ratio clock */
SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
@@ -114,6 +115,7 @@ static struct clk *main_clks[] = {
&pll3_clk,
&hp_clk,
&p_clk,
+ &qspi_clk,
&rclk_clk,
&mp_clk,
&cp_clk,
@@ -122,6 +124,7 @@ static struct clk *main_clks[] = {
/* MSTP */
enum {
+ MSTP917,
MSTP813,
MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
MSTP719, MSTP718, MSTP715, MSTP714,
@@ -133,6 +136,7 @@ enum {
};
static struct clk mstp_clks[MSTP_NR] = {
+ [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
@@ -167,6 +171,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("pll3", &pll3_clk),
CLKDEV_CON_ID("hp", &hp_clk),
CLKDEV_CON_ID("p", &p_clk),
+ CLKDEV_CON_ID("qspi", &qspi_clk),
CLKDEV_CON_ID("rclk", &rclk_clk),
CLKDEV_CON_ID("mp", &mp_clk),
CLKDEV_CON_ID("cp", &cp_clk),
@@ -192,6 +197,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
+ CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
@@ -232,6 +238,11 @@ void __init r8a7791_clock_init(void)
break;
}
+ if ((mode & (MD(3) | MD(2) | MD(1))) = MD(2))
+ SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+ else
+ SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
+
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 2/3] ARM: shmobile: r8a7791: add QSPI clock
@ 2014-01-03 15:34 ` Geert Uytterhoeven
0 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-03 15:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
arch/arm/mach-shmobile/clock-r8a7791.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index f5461262ee25..740c06968994 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -93,6 +93,7 @@ static struct clk main_clk = {
*/
SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
/* fixed ratio clock */
SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
@@ -114,6 +115,7 @@ static struct clk *main_clks[] = {
&pll3_clk,
&hp_clk,
&p_clk,
+ &qspi_clk,
&rclk_clk,
&mp_clk,
&cp_clk,
@@ -122,6 +124,7 @@ static struct clk *main_clks[] = {
/* MSTP */
enum {
+ MSTP917,
MSTP813,
MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
MSTP719, MSTP718, MSTP715, MSTP714,
@@ -133,6 +136,7 @@ enum {
};
static struct clk mstp_clks[MSTP_NR] = {
+ [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */
[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
@@ -167,6 +171,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("pll3", &pll3_clk),
CLKDEV_CON_ID("hp", &hp_clk),
CLKDEV_CON_ID("p", &p_clk),
+ CLKDEV_CON_ID("qspi", &qspi_clk),
CLKDEV_CON_ID("rclk", &rclk_clk),
CLKDEV_CON_ID("mp", &mp_clk),
CLKDEV_CON_ID("cp", &cp_clk),
@@ -192,6 +197,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
+ CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */
@@ -232,6 +238,11 @@ void __init r8a7791_clock_init(void)
break;
}
+ if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
+ SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+ else
+ SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
+
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/3] ARM: shmobile: Koelsch: Add QSPI support
2014-01-03 15:34 ` Geert Uytterhoeven
@ 2014-01-03 15:34 ` Geert Uytterhoeven
-1 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-03 15:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Enable support for the Spansion s25fl512s SPI FLASH on the Koelsch board:
- Add QSPI platform device, resources, platform data, and pinmux,
- Add FLASH data and MTD partitions.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
arch/arm/mach-shmobile/board-koelsch.c | 61 ++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index de7cc64b1f37..723ed54b38be 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -25,12 +25,17 @@
#include <linux/input.h>
#include <linux/kernel.h>
#include <linux/leds.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
#include <linux/phy.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/rcar-du.h>
#include <linux/platform_device.h>
#include <linux/sh_eth.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/rspi.h>
+#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a7791.h>
@@ -148,6 +153,55 @@ static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = {
.nbuttons = ARRAY_SIZE(gpio_buttons),
};
+/* QSPI */
+static const struct resource qspi_resources[] __initconst = {
+ DEFINE_RES_MEM(0xe6b10000, 0x1000),
+ DEFINE_RES_IRQ(gic_spi(184)),
+};
+
+static const struct rspi_plat_data qspi_pdata __initconst = {
+ .num_chipselect = 1,
+};
+
+/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64 MiB) */
+static struct mtd_partition spi_flash_part[] = {
+ {
+ .name = "loader",
+ .offset = 0x00000000,
+ .size = 512 * 1024,
+ .mask_flags = MTD_WRITEABLE,
+ },
+ {
+ .name = "bootenv",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 512 * 1024,
+ .mask_flags = MTD_WRITEABLE,
+ },
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static const struct flash_platform_data spi_flash_data = {
+ .name = "m25p80",
+ .parts = spi_flash_part,
+ .nr_parts = ARRAY_SIZE(spi_flash_part),
+ .type = "s25fl512s",
+};
+
+static const struct spi_board_info spi_info[] __initconst = {
+ {
+ .modalias = "m25p80",
+ .platform_data = &spi_flash_data,
+ .mode = SPI_MODE_0,
+ .max_speed_hz = 30000000,
+ .bus_num = 0,
+ .chip_select = 0,
+ },
+};
+
static const struct pinctrl_map koelsch_pinctrl_map[] = {
/* DU */
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
@@ -165,6 +219,8 @@ static const struct pinctrl_map koelsch_pinctrl_map[] = {
"eth_rmii", "eth"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
"intc_irq0", "intc"),
+ /* QSPI */
+ PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791", "qspi", "qspi"),
/* SCIF0 (CN19: DEBUG SERIAL0) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7791",
"scif0_data_d", "scif0"),
@@ -190,6 +246,11 @@ static void __init koelsch_add_standard_devices(void)
platform_device_register_data(&platform_bus, "gpio-keys", -1,
&koelsch_keys_pdata,
sizeof(koelsch_keys_pdata));
+ platform_device_register_resndata(&platform_bus, "qspi", 0,
+ qspi_resources,
+ ARRAY_SIZE(qspi_resources),
+ &qspi_pdata, sizeof(qspi_pdata));
+ spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
koelsch_add_du_device();
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 3/3] ARM: shmobile: Koelsch: Add QSPI support
@ 2014-01-03 15:34 ` Geert Uytterhoeven
0 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-03 15:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Enable support for the Spansion s25fl512s SPI FLASH on the Koelsch board:
- Add QSPI platform device, resources, platform data, and pinmux,
- Add FLASH data and MTD partitions.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
---
arch/arm/mach-shmobile/board-koelsch.c | 61 ++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index de7cc64b1f37..723ed54b38be 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -25,12 +25,17 @@
#include <linux/input.h>
#include <linux/kernel.h>
#include <linux/leds.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
#include <linux/phy.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/rcar-du.h>
#include <linux/platform_device.h>
#include <linux/sh_eth.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/rspi.h>
+#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <mach/r8a7791.h>
@@ -148,6 +153,55 @@ static const struct gpio_keys_platform_data koelsch_keys_pdata __initconst = {
.nbuttons = ARRAY_SIZE(gpio_buttons),
};
+/* QSPI */
+static const struct resource qspi_resources[] __initconst = {
+ DEFINE_RES_MEM(0xe6b10000, 0x1000),
+ DEFINE_RES_IRQ(gic_spi(184)),
+};
+
+static const struct rspi_plat_data qspi_pdata __initconst = {
+ .num_chipselect = 1,
+};
+
+/* SPI Flash memory (Spansion S25FL512SAGMFIG11 64 MiB) */
+static struct mtd_partition spi_flash_part[] = {
+ {
+ .name = "loader",
+ .offset = 0x00000000,
+ .size = 512 * 1024,
+ .mask_flags = MTD_WRITEABLE,
+ },
+ {
+ .name = "bootenv",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 512 * 1024,
+ .mask_flags = MTD_WRITEABLE,
+ },
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+static const struct flash_platform_data spi_flash_data = {
+ .name = "m25p80",
+ .parts = spi_flash_part,
+ .nr_parts = ARRAY_SIZE(spi_flash_part),
+ .type = "s25fl512s",
+};
+
+static const struct spi_board_info spi_info[] __initconst = {
+ {
+ .modalias = "m25p80",
+ .platform_data = &spi_flash_data,
+ .mode = SPI_MODE_0,
+ .max_speed_hz = 30000000,
+ .bus_num = 0,
+ .chip_select = 0,
+ },
+};
+
static const struct pinctrl_map koelsch_pinctrl_map[] = {
/* DU */
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7791", "pfc-r8a7791",
@@ -165,6 +219,8 @@ static const struct pinctrl_map koelsch_pinctrl_map[] = {
"eth_rmii", "eth"),
PIN_MAP_MUX_GROUP_DEFAULT("r8a7791-ether", "pfc-r8a7791",
"intc_irq0", "intc"),
+ /* QSPI */
+ PIN_MAP_MUX_GROUP_DEFAULT("qspi.0", "pfc-r8a7791", "qspi", "qspi"),
/* SCIF0 (CN19: DEBUG SERIAL0) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7791",
"scif0_data_d", "scif0"),
@@ -190,6 +246,11 @@ static void __init koelsch_add_standard_devices(void)
platform_device_register_data(&platform_bus, "gpio-keys", -1,
&koelsch_keys_pdata,
sizeof(koelsch_keys_pdata));
+ platform_device_register_resndata(&platform_bus, "qspi", 0,
+ qspi_resources,
+ ARRAY_SIZE(qspi_resources),
+ &qspi_pdata, sizeof(qspi_pdata));
+ spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
koelsch_add_du_device();
}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 3/3] ARM: shmobile: Koelsch: Add QSPI support
2014-01-03 15:34 ` Geert Uytterhoeven
@ 2014-01-03 16:51 ` Sergei Shtylyov
-1 siblings, 0 replies; 22+ messages in thread
From: Sergei Shtylyov @ 2014-01-03 15:51 UTC (permalink / raw)
To: linux-arm-kernel
Hello.
On 01/03/2014 06:34 PM, Geert Uytterhoeven wrote:
> From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> Enable support for the Spansion s25fl512s SPI FLASH on the Koelsch board:
> - Add QSPI platform device, resources, platform data, and pinmux,
> - Add FLASH data and MTD partitions.
> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> ---
> arch/arm/mach-shmobile/board-koelsch.c | 61 ++++++++++++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
> diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
> index de7cc64b1f37..723ed54b38be 100644
> --- a/arch/arm/mach-shmobile/board-koelsch.c
> +++ b/arch/arm/mach-shmobile/board-koelsch.c
[...]
> @@ -190,6 +246,11 @@ static void __init koelsch_add_standard_devices(void)
> platform_device_register_data(&platform_bus, "gpio-keys", -1,
> &koelsch_keys_pdata,
> sizeof(koelsch_keys_pdata));
> + platform_device_register_resndata(&platform_bus, "qspi", 0,
As I understood, there's single QSPI controller, so why you pass 0, and
not -1 here?
> + qspi_resources,
> + ARRAY_SIZE(qspi_resources),
> + &qspi_pdata, sizeof(qspi_pdata));
> + spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
WBR, Sergei
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 3/3] ARM: shmobile: Koelsch: Add QSPI support
@ 2014-01-03 16:51 ` Sergei Shtylyov
0 siblings, 0 replies; 22+ messages in thread
From: Sergei Shtylyov @ 2014-01-03 16:51 UTC (permalink / raw)
To: linux-arm-kernel
Hello.
On 01/03/2014 06:34 PM, Geert Uytterhoeven wrote:
> From: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> Enable support for the Spansion s25fl512s SPI FLASH on the Koelsch board:
> - Add QSPI platform device, resources, platform data, and pinmux,
> - Add FLASH data and MTD partitions.
> Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
> ---
> arch/arm/mach-shmobile/board-koelsch.c | 61 ++++++++++++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
> diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
> index de7cc64b1f37..723ed54b38be 100644
> --- a/arch/arm/mach-shmobile/board-koelsch.c
> +++ b/arch/arm/mach-shmobile/board-koelsch.c
[...]
> @@ -190,6 +246,11 @@ static void __init koelsch_add_standard_devices(void)
> platform_device_register_data(&platform_bus, "gpio-keys", -1,
> &koelsch_keys_pdata,
> sizeof(koelsch_keys_pdata));
> + platform_device_register_resndata(&platform_bus, "qspi", 0,
As I understood, there's single QSPI controller, so why you pass 0, and
not -1 here?
> + qspi_resources,
> + ARRAY_SIZE(qspi_resources),
> + &qspi_pdata, sizeof(qspi_pdata));
> + spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
WBR, Sergei
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 3/3] ARM: shmobile: Koelsch: Add QSPI support
2014-01-03 16:51 ` Sergei Shtylyov
@ 2014-01-03 16:07 ` Geert Uytterhoeven
-1 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-03 16:07 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 3, 2014 at 5:51 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
>> + platform_device_register_resndata(&platform_bus, "qspi", 0,
>
> As I understood, there's single QSPI controller, so why you pass 0, and
> not -1 here?
Indeed, there's only a single QSPI instance.
However, I choose to use "0" for consistency with Lager.
Mach-shmobile seems to use a mix of 0 and -1.
If the maintainer prefers -1, I can change that.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread* [PATCH 3/3] ARM: shmobile: Koelsch: Add QSPI support
@ 2014-01-03 16:07 ` Geert Uytterhoeven
0 siblings, 0 replies; 22+ messages in thread
From: Geert Uytterhoeven @ 2014-01-03 16:07 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 3, 2014 at 5:51 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
>> + platform_device_register_resndata(&platform_bus, "qspi", 0,
>
> As I understood, there's single QSPI controller, so why you pass 0, and
> not -1 here?
Indeed, there's only a single QSPI instance.
However, I choose to use "0" for consistency with Lager.
Mach-shmobile seems to use a mix of 0 and -1.
If the maintainer prefers -1, I can change that.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 3/3] ARM: shmobile: Koelsch: Add QSPI support
2014-01-03 16:07 ` Geert Uytterhoeven
@ 2014-01-06 0:39 ` Kuninori Morimoto
-1 siblings, 0 replies; 22+ messages in thread
From: Kuninori Morimoto @ 2014-01-06 0:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi
> <sergei.shtylyov@cogentembedded.com> wrote:
> >> + platform_device_register_resndata(&platform_bus, "qspi", 0,
> >
> > As I understood, there's single QSPI controller, so why you pass 0, and
> > not -1 here?
>
> Indeed, there's only a single QSPI instance.
> However, I choose to use "0" for consistency with Lager.
> Mach-shmobile seems to use a mix of 0 and -1.
>
> If the maintainer prefers -1, I can change that.
In SPI driver case, spi master will use dynamic
bus_num value if ID was -1 (in spi_register_master()).
Then, slave device can't be detected.
So, ID = 0 is reasonable even though single QSPI.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/3] ARM: shmobile: Koelsch: Add QSPI support
@ 2014-01-06 0:39 ` Kuninori Morimoto
0 siblings, 0 replies; 22+ messages in thread
From: Kuninori Morimoto @ 2014-01-06 0:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi
> <sergei.shtylyov@cogentembedded.com> wrote:
> >> + platform_device_register_resndata(&platform_bus, "qspi", 0,
> >
> > As I understood, there's single QSPI controller, so why you pass 0, and
> > not -1 here?
>
> Indeed, there's only a single QSPI instance.
> However, I choose to use "0" for consistency with Lager.
> Mach-shmobile seems to use a mix of 0 and -1.
>
> If the maintainer prefers -1, I can change that.
In SPI driver case, spi master will use dynamic
bus_num value if ID was -1 (in spi_register_master()).
Then, slave device can't be detected.
So, ID = 0 is reasonable even though single QSPI.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 3/3] ARM: shmobile: Koelsch: Add QSPI support
2014-01-06 0:39 ` Kuninori Morimoto
@ 2014-01-06 2:24 ` Simon Horman
-1 siblings, 0 replies; 22+ messages in thread
From: Simon Horman @ 2014-01-06 2:24 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Jan 05, 2014 at 04:39:14PM -0800, Kuninori Morimoto wrote:
> Hi
>
> > <sergei.shtylyov@cogentembedded.com> wrote:
> > >> + platform_device_register_resndata(&platform_bus, "qspi", 0,
> > >
> > > As I understood, there's single QSPI controller, so why you pass 0, and
> > > not -1 here?
> >
> > Indeed, there's only a single QSPI instance.
> > However, I choose to use "0" for consistency with Lager.
> > Mach-shmobile seems to use a mix of 0 and -1.
> >
> > If the maintainer prefers -1, I can change that.
>
> In SPI driver case, spi master will use dynamic
> bus_num value if ID was -1 (in spi_register_master()).
> Then, slave device can't be detected.
> So, ID = 0 is reasonable even though single QSPI.
When it makes sense I prefer -1, however, in this case it
seems that 0 is a better choice.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/3] ARM: shmobile: Koelsch: Add QSPI support
@ 2014-01-06 2:24 ` Simon Horman
0 siblings, 0 replies; 22+ messages in thread
From: Simon Horman @ 2014-01-06 2:24 UTC (permalink / raw)
To: linux-arm-kernel
On Sun, Jan 05, 2014 at 04:39:14PM -0800, Kuninori Morimoto wrote:
> Hi
>
> > <sergei.shtylyov@cogentembedded.com> wrote:
> > >> + platform_device_register_resndata(&platform_bus, "qspi", 0,
> > >
> > > As I understood, there's single QSPI controller, so why you pass 0, and
> > > not -1 here?
> >
> > Indeed, there's only a single QSPI instance.
> > However, I choose to use "0" for consistency with Lager.
> > Mach-shmobile seems to use a mix of 0 and -1.
> >
> > If the maintainer prefers -1, I can change that.
>
> In SPI driver case, spi master will use dynamic
> bus_num value if ID was -1 (in spi_register_master()).
> Then, slave device can't be detected.
> So, ID = 0 is reasonable even though single QSPI.
When it makes sense I prefer -1, however, in this case it
seems that 0 is a better choice.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 0/3] Add QSPI support on r8a7791/koelsch
2014-01-03 15:34 ` Geert Uytterhoeven
@ 2014-01-07 1:20 ` Simon Horman
-1 siblings, 0 replies; 22+ messages in thread
From: Simon Horman @ 2014-01-07 1:20 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 03, 2014 at 04:34:13PM +0100, Geert Uytterhoeven wrote:
> This series adds support for the Spansion s25fl512s SPI FLASH on the
> r8a7791-based Koelsch board:
>
> [1/3] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
I believe that Laurent should handle patch 1/3.
> [2/3] ARM: shmobile: r8a7791: add QSPI clock
> [3/3] ARM: shmobile: Koelsch: Add QSPI support
I believe that patch 3/3 depends on patch 1/3.
So I would like to wait for Laurent to handle patch 1/3.
Also, please post a patch to update the koelsch defconfig.
> This applies to non-multiplatform Koelsch only. Multi-platform Koelsch
> support will be added when the spi-rspi driver gains DT support.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 0/3] Add QSPI support on r8a7791/koelsch
@ 2014-01-07 1:20 ` Simon Horman
0 siblings, 0 replies; 22+ messages in thread
From: Simon Horman @ 2014-01-07 1:20 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 03, 2014 at 04:34:13PM +0100, Geert Uytterhoeven wrote:
> This series adds support for the Spansion s25fl512s SPI FLASH on the
> r8a7791-based Koelsch board:
>
> [1/3] pinctrl: sh-pfc: r8a7791: Add QSPI pin groups
I believe that Laurent should handle patch 1/3.
> [2/3] ARM: shmobile: r8a7791: add QSPI clock
> [3/3] ARM: shmobile: Koelsch: Add QSPI support
I believe that patch 3/3 depends on patch 1/3.
So I would like to wait for Laurent to handle patch 1/3.
Also, please post a patch to update the koelsch defconfig.
> This applies to non-multiplatform Koelsch only. Multi-platform Koelsch
> support will be added when the spi-rspi driver gains DT support.
^ permalink raw reply [flat|nested] 22+ messages in thread