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From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: Tomasz Figa <t.figa@samsung.com>
Cc: linux-samsung-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Kukjin Kim <kgene.kim@samsung.com>,
	lauraa@codeaurora.org, linux-omap@vger.kernel.org,
	linus.walleij@linaro.org, santosh.shilimkar@ti.com,
	tony@atomide.com, drake@endlessm.com,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Tomasz Figa <tomasz.figa@gmail.com>,
	loeliger@gmail.com
Subject: Re: [PATCH v4 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume
Date: Mon, 15 Sep 2014 10:03:53 +0100	[thread overview]
Message-ID: <20140915090353.GD12379@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <1409062680-15906-7-git-send-email-t.figa@samsung.com>

On Tue, Aug 26, 2014 at 04:17:59PM +0200, Tomasz Figa wrote:
> On Exynos SoCs it is necessary to resume operation of L2C early in
> assembly code, because otherwise certain systems will crash. This patch
> adds necessary code to non-secure resume handler.
> 
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> ---
>  arch/arm/mach-exynos/common.h   |  1 +
>  arch/arm/mach-exynos/firmware.c |  4 +++-
>  arch/arm/mach-exynos/sleep.S    | 41 +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index c218200..e88c0f9 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -113,6 +113,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
>  
>  extern u32 cp15_save_diag;
>  extern u32 cp15_save_power;
> +extern unsigned long l2x0_regs_phys;
>  
>  extern void __iomem *sysram_ns_base_addr;
>  extern void __iomem *sysram_base_addr;
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index 554b350..71bcfbd 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -102,7 +102,9 @@ static int exynos_suspend(void)
>  	writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
>  	writel(virt_to_phys(exynos_cpu_resume_ns),
>  		sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
> -
> +#ifdef CONFIG_CACHE_L2X0
> +	l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
> +#endif

NAK.  Please look at how arch/arm/mm/l2c-l2x0-resume.S gets the address
of this structure in assembly code.  The name of this variable is crap
in any case.  It's not the registers, it's the saved registers.  So even
more reason to kill this abomination, which incidentally, I've already
killed off once before in the exynos code.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.

WARNING: multiple messages have this Message-ID (diff)
From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume
Date: Mon, 15 Sep 2014 10:03:53 +0100	[thread overview]
Message-ID: <20140915090353.GD12379@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <1409062680-15906-7-git-send-email-t.figa@samsung.com>

On Tue, Aug 26, 2014 at 04:17:59PM +0200, Tomasz Figa wrote:
> On Exynos SoCs it is necessary to resume operation of L2C early in
> assembly code, because otherwise certain systems will crash. This patch
> adds necessary code to non-secure resume handler.
> 
> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> ---
>  arch/arm/mach-exynos/common.h   |  1 +
>  arch/arm/mach-exynos/firmware.c |  4 +++-
>  arch/arm/mach-exynos/sleep.S    | 41 +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 45 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
> index c218200..e88c0f9 100644
> --- a/arch/arm/mach-exynos/common.h
> +++ b/arch/arm/mach-exynos/common.h
> @@ -113,6 +113,7 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
>  
>  extern u32 cp15_save_diag;
>  extern u32 cp15_save_power;
> +extern unsigned long l2x0_regs_phys;
>  
>  extern void __iomem *sysram_ns_base_addr;
>  extern void __iomem *sysram_base_addr;
> diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
> index 554b350..71bcfbd 100644
> --- a/arch/arm/mach-exynos/firmware.c
> +++ b/arch/arm/mach-exynos/firmware.c
> @@ -102,7 +102,9 @@ static int exynos_suspend(void)
>  	writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
>  	writel(virt_to_phys(exynos_cpu_resume_ns),
>  		sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
> -
> +#ifdef CONFIG_CACHE_L2X0
> +	l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
> +#endif

NAK.  Please look at how arch/arm/mm/l2c-l2x0-resume.S gets the address
of this structure in assembly code.  The name of this variable is crap
in any case.  It's not the registers, it's the saved registers.  So even
more reason to kill this abomination, which incidentally, I've already
killed off once before in the exynos code.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.

  reply	other threads:[~2014-09-15  9:03 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-26 14:17 [PATCH v4 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs Tomasz Figa
2014-08-26 14:17 ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 1/7] ARM: l2c: Refactor the driver to use commit-like interface Tomasz Figa
2014-08-26 14:17   ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C Tomasz Figa
2014-08-26 14:17   ` Tomasz Figa
2014-08-26 14:17   ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL Tomasz Figa
2014-08-26 14:17   ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 4/7] ARM: l2c: Add support for overriding prefetch settings Tomasz Figa
2014-08-26 14:17   ` Tomasz Figa
2014-08-26 14:17   ` Tomasz Figa
2014-09-19  9:50   ` Alexandre Belloni
2014-09-19  9:50     ` Alexandre Belloni
2014-09-19 16:39     ` Russell King - ARM Linux
2014-09-19 16:39       ` Russell King - ARM Linux
2014-09-19 18:30       ` Alexandre Belloni
2014-09-19 18:30         ` Alexandre Belloni
2014-09-20  8:31         ` Russell King - ARM Linux
2014-09-20  8:31           ` Russell King - ARM Linux
2014-08-26 14:17 ` [PATCH v4 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310 Tomasz Figa
2014-08-26 14:17   ` Tomasz Figa
2014-09-15  8:58   ` Russell King - ARM Linux
2014-09-15  8:58     ` Russell King - ARM Linux
2014-09-15 21:27     ` Tomasz Figa
2014-09-15 21:27       ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume Tomasz Figa
2014-08-26 14:17   ` Tomasz Figa
2014-09-15  9:03   ` Russell King - ARM Linux [this message]
2014-09-15  9:03     ` Russell King - ARM Linux
2014-09-15 21:31     ` Tomasz Figa
2014-09-15 21:31       ` Tomasz Figa
2014-08-26 14:18 ` [PATCH v4 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller Tomasz Figa
2014-08-26 14:18   ` Tomasz Figa
2014-09-14 17:50 ` [PATCH v4 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs Tomasz Figa
2014-09-14 17:50   ` Tomasz Figa

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