From: Alexandre Belloni <alexandre.belloni@free-electrons.com>
To: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: Tomasz Figa <t.figa@samsung.com>,
linux-samsung-soc@vger.kernel.org,
Kukjin Kim <kgene.kim@samsung.com>,
lauraa@codeaurora.org, tony@atomide.com,
linus.walleij@linaro.org, linux-kernel@vger.kernel.org,
drake@endlessm.com, loeliger@gmail.com, santosh.shilimkar@ti.com,
linux-omap@vger.kernel.org, Tomasz Figa <tomasz.figa@gmail.com>,
linux-arm-kernel@lists.infradead.org,
Marek Szyprowski <m.szyprowski@samsung.com>
Subject: Re: [PATCH v4 4/7] ARM: l2c: Add support for overriding prefetch settings
Date: Fri, 19 Sep 2014 20:30:07 +0200 [thread overview]
Message-ID: <20140919183007.GG29620@piout.net> (raw)
In-Reply-To: <20140919163932.GH12379@n2100.arm.linux.org.uk>
On 19/09/2014 at 17:39:32 +0100, Russell King - ARM Linux wrote :
> On Fri, Sep 19, 2014 at 11:50:01AM +0200, Alexandre Belloni wrote:
> > On 26/08/2014 at 16:17:57 +0200, Tomasz Figa wrote :
> > > Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
> > > settings configured in registers leading to crashes if L2C is enabled
> > > without overriding them. This patch introduces bindings to enable
> > > prefetch settings to be specified from DT and necessary support in the
> > > driver.
> > >
> > > Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> >
> > Tested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> >
> > It is working and useful on Atmel's sama5d4 were the bootloader is not
> > configuring the L2C prefetch. However, I'm wondering whether we should
> > add support for setting L310_PREFETCH_CTRL_DATA_PREFETCH and
> > L310_PREFETCH_CTRL_INSTR_PREFETCH. I'm currently doing it by using
> > ".l2c_aux_val = L310_AUX_CTRL_DATA_PREFETCH |
> > L310_AUX_CTRL_INSTR_PREFETCH" (those are the same bits) but this has the
> > disadvantage of displaying the "L2C: platform modifies aux control
> > register:" twice.
>
> The L2C documentation, freely available from the ARM infocentre website,
> has the answer to this for you.
>
> The two bits in the prefetch control register which control the data
> and instruction prefetching are aliases of the aux control register.
> If you set them to a value in one register, they are reflected in the
> other.
>
> The reason for that is that once the L2 cache is enabled, writes to
> the aux control register are no longer permitted, but it's safe to
> enable and disable the prefetching with the cache already enabled.
> This reason is even stated in the documentation.
>
Yeah, so my question still holds, should we have an other way to
enable/disable I/D prefetch by adding two other DT bindings ?
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
WARNING: multiple messages have this Message-ID (diff)
From: alexandre.belloni@free-electrons.com (Alexandre Belloni)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 4/7] ARM: l2c: Add support for overriding prefetch settings
Date: Fri, 19 Sep 2014 20:30:07 +0200 [thread overview]
Message-ID: <20140919183007.GG29620@piout.net> (raw)
In-Reply-To: <20140919163932.GH12379@n2100.arm.linux.org.uk>
On 19/09/2014 at 17:39:32 +0100, Russell King - ARM Linux wrote :
> On Fri, Sep 19, 2014 at 11:50:01AM +0200, Alexandre Belloni wrote:
> > On 26/08/2014 at 16:17:57 +0200, Tomasz Figa wrote :
> > > Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
> > > settings configured in registers leading to crashes if L2C is enabled
> > > without overriding them. This patch introduces bindings to enable
> > > prefetch settings to be specified from DT and necessary support in the
> > > driver.
> > >
> > > Signed-off-by: Tomasz Figa <t.figa@samsung.com>
> >
> > Tested-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> >
> > It is working and useful on Atmel's sama5d4 were the bootloader is not
> > configuring the L2C prefetch. However, I'm wondering whether we should
> > add support for setting L310_PREFETCH_CTRL_DATA_PREFETCH and
> > L310_PREFETCH_CTRL_INSTR_PREFETCH. I'm currently doing it by using
> > ".l2c_aux_val = L310_AUX_CTRL_DATA_PREFETCH |
> > L310_AUX_CTRL_INSTR_PREFETCH" (those are the same bits) but this has the
> > disadvantage of displaying the "L2C: platform modifies aux control
> > register:" twice.
>
> The L2C documentation, freely available from the ARM infocentre website,
> has the answer to this for you.
>
> The two bits in the prefetch control register which control the data
> and instruction prefetching are aliases of the aux control register.
> If you set them to a value in one register, they are reflected in the
> other.
>
> The reason for that is that once the L2 cache is enabled, writes to
> the aux control register are no longer permitted, but it's safe to
> enable and disable the prefetching with the cache already enabled.
> This reason is even stated in the documentation.
>
Yeah, so my question still holds, should we have an other way to
enable/disable I/D prefetch by adding two other DT bindings ?
--
Alexandre Belloni, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
next prev parent reply other threads:[~2014-09-19 18:30 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-26 14:17 [PATCH v4 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs Tomasz Figa
2014-08-26 14:17 ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 1/7] ARM: l2c: Refactor the driver to use commit-like interface Tomasz Figa
2014-08-26 14:17 ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 2/7] ARM: l2c: Add interface to ask hypervisor to configure L2C Tomasz Figa
2014-08-26 14:17 ` Tomasz Figa
2014-08-26 14:17 ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 3/7] ARM: l2c: Get outer cache .write_sec callback from mach_desc only if not NULL Tomasz Figa
2014-08-26 14:17 ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 4/7] ARM: l2c: Add support for overriding prefetch settings Tomasz Figa
2014-08-26 14:17 ` Tomasz Figa
2014-08-26 14:17 ` Tomasz Figa
2014-09-19 9:50 ` Alexandre Belloni
2014-09-19 9:50 ` Alexandre Belloni
2014-09-19 16:39 ` Russell King - ARM Linux
2014-09-19 16:39 ` Russell King - ARM Linux
2014-09-19 18:30 ` Alexandre Belloni [this message]
2014-09-19 18:30 ` Alexandre Belloni
2014-09-20 8:31 ` Russell King - ARM Linux
2014-09-20 8:31 ` Russell King - ARM Linux
2014-08-26 14:17 ` [PATCH v4 5/7] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310 Tomasz Figa
2014-08-26 14:17 ` Tomasz Figa
2014-09-15 8:58 ` Russell King - ARM Linux
2014-09-15 8:58 ` Russell King - ARM Linux
2014-09-15 21:27 ` Tomasz Figa
2014-09-15 21:27 ` Tomasz Figa
2014-08-26 14:17 ` [PATCH v4 6/7] ARM: EXYNOS: Add support for non-secure L2X0 resume Tomasz Figa
2014-08-26 14:17 ` Tomasz Figa
2014-09-15 9:03 ` Russell King - ARM Linux
2014-09-15 9:03 ` Russell King - ARM Linux
2014-09-15 21:31 ` Tomasz Figa
2014-09-15 21:31 ` Tomasz Figa
2014-08-26 14:18 ` [PATCH v4 7/7] ARM: dts: exynos4: Add nodes for L2 cache controller Tomasz Figa
2014-08-26 14:18 ` Tomasz Figa
2014-09-14 17:50 ` [PATCH v4 0/7] Enable L2 cache support on Exynos4210/4x12 SoCs Tomasz Figa
2014-09-14 17:50 ` Tomasz Figa
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