Re: [Qemu-devel] [PATCH pic32 v2 4/5] Two new processor variants: M4K and microAptivP.

[Aurelien Jarno <aurelien@aurel32.net>]

On 2015-07-05 20:48, Serge Vakulenko wrote:
> On Wed, Jul 1, 2015 at 6:37 AM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> > On 2015-06-30 21:12, Serge Vakulenko wrote:
> >> Signed-off-by: Serge Vakulenko <serge.vakulenko@gmail.com>
> >> ---
> >>  target-mips/cpu.h            |  2 ++
> >>  target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
> >>  2 files changed, 48 insertions(+)
> >>
> >> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> >> index ab830ee..9f5890c 100644
> >> --- a/target-mips/cpu.h
> >> +++ b/target-mips/cpu.h
> >> @@ -394,6 +394,7 @@ struct CPUMIPSState {
> >>  #define CP0C0_M    31
> >>  #define CP0C0_K23  28
> >>  #define CP0C0_KU   25
> >> +#define CP0C0_SB   21
> >
> > Bits in the range 16:24 are implementation specific, so I do wonder if
> > we want to have this bit there. At least we should mark it as
> > implementation specific.
> 
> I tried to make the configuration as close as possible to a real PIC32
> microcontroller - that's why I added Config0.SB and Config7.WII bits.
> These bits are described in appropriate Microchip docs. As they are
> not relevant for the simulation purposes, I'll better remove them for
> simplicity.

It's fine if they are needed, but I suggest in that case to chose a name
showing it's PIC32 specific, something like CP0C0_PIC32_SB.

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net