* [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-14 15:46 ` Claudiu Manoil
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-14 15:46 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, shawn.guo; +Cc: Alison Wang
This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Enable support for the second interrupt group register block
and the corresponding Rx/Tx/Err interrupt sources, for each
eTSEC node. DT binding documentation updates.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2:
- register block size is 0x1000 (4kB memory page), not 0x8000;
- reg property has 2 "address" and resp. 2 "size" cells;
- remove optional/ obsoleted properties;
- use register block address as queue-group id for consistency;
- binding documentation updates for missing vendor properties;
.../devicetree/bindings/net/fsl-tsec-phy.txt | 6 +-
arch/arm/boot/dts/ls1021a-qds.dts | 20 +++++
arch/arm/boot/dts/ls1021a-twr.dts | 20 +++++
arch/arm/boot/dts/ls1021a.dtsi | 92 ++++++++++++++++++++++
4 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..b3291c7 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,7 +45,7 @@ Properties:
- device_type : Should be "network"
- model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
- - compatible : Should be "gianfar"
+ - compatible : "gianfar", "fsl-etsec2"
- reg : Offset and length of the register set for the device
- interrupts : For FEC devices, the first interrupt is the device's
interrupt. For TSEC and eTSEC devices, the first interrupt is
@@ -57,6 +57,10 @@ Properties:
"rgmii-id", as all other connection types are detected by hardware.
- fsl,magic-packet : If present, indicates that the hardware supports
waking up via magic packet.
+ - fsl,wake-on-filer: Indicates that the device can wake up the system
+ by generating a filer interrupt. Depending on the wake-on-lan mode
+ set for this device, the filer interrupt can be triggered by certain
+ user-defined ethernet packets (usually ARP or L2 unicast packets).
- bd-stash : If present, indicates that the hardware supports stashing
buffer descriptors in the L2.
- rx-stash-len : Denotes the number of bytes of a received buffer to stash
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1c>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1d>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy3>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy0>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..cc48d56 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
serial3 = &lpuart3;
serial4 = &lpuart4;
serial5 = &lpuart5;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
sysclk = &sysclk;
};
@@ -391,6 +394,95 @@
reg = <0x0 0x2d24000 0x0 0x4000>;
};
+ enet0: ethernet@2d10000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ fsl,magic-packet;
+ fsl,wake-on-filer;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@2d10000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d14000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ enet1: ethernet@2d50000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@2d50000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d50000 0x0 0x1000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d54000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d54000 0x0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ enet2: ethernet@2d90000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@2d90000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d90000 0x0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d94000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d94000 0x0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
usb@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
--
1.7.11.7
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-14 15:46 ` Claudiu Manoil
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-14 15:46 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A
Cc: Alison Wang
This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
Signed-off-by: Alison Wang <alison.wang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Enable support for the second interrupt group register block
and the corresponding Rx/Tx/Err interrupt sources, for each
eTSEC node. DT binding documentation updates.
Signed-off-by: Claudiu Manoil <claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
v2:
- register block size is 0x1000 (4kB memory page), not 0x8000;
- reg property has 2 "address" and resp. 2 "size" cells;
- remove optional/ obsoleted properties;
- use register block address as queue-group id for consistency;
- binding documentation updates for missing vendor properties;
.../devicetree/bindings/net/fsl-tsec-phy.txt | 6 +-
arch/arm/boot/dts/ls1021a-qds.dts | 20 +++++
arch/arm/boot/dts/ls1021a-twr.dts | 20 +++++
arch/arm/boot/dts/ls1021a.dtsi | 92 ++++++++++++++++++++++
4 files changed, 137 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..b3291c7 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,7 +45,7 @@ Properties:
- device_type : Should be "network"
- model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
- - compatible : Should be "gianfar"
+ - compatible : "gianfar", "fsl-etsec2"
- reg : Offset and length of the register set for the device
- interrupts : For FEC devices, the first interrupt is the device's
interrupt. For TSEC and eTSEC devices, the first interrupt is
@@ -57,6 +57,10 @@ Properties:
"rgmii-id", as all other connection types are detected by hardware.
- fsl,magic-packet : If present, indicates that the hardware supports
waking up via magic packet.
+ - fsl,wake-on-filer: Indicates that the device can wake up the system
+ by generating a filer interrupt. Depending on the wake-on-lan mode
+ set for this device, the filer interrupt can be triggered by certain
+ user-defined ethernet packets (usually ARP or L2 unicast packets).
- bd-stash : If present, indicates that the hardware supports stashing
buffer descriptors in the L2.
- rx-stash-len : Denotes the number of bytes of a received buffer to stash
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1c>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1d>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy3>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy0>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c70bb27..cc48d56 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
serial3 = &lpuart3;
serial4 = &lpuart4;
serial5 = &lpuart5;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
sysclk = &sysclk;
};
@@ -391,6 +394,95 @@
reg = <0x0 0x2d24000 0x0 0x4000>;
};
+ enet0: ethernet@2d10000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ fsl,magic-packet;
+ fsl,wake-on-filer;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@2d10000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d14000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ enet1: ethernet@2d50000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@2d50000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d50000 0x0 0x1000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d54000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d54000 0x0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ enet2: ethernet@2d90000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ ranges;
+
+ queue-group@2d90000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d90000 0x0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d94000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d94000 0x0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
usb@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
--
1.7.11.7
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^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-14 15:57 ` Fabio Estevam
0 siblings, 0 replies; 43+ messages in thread
From: Fabio Estevam @ 2015-07-14 15:57 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
<claudiu.manoil@freescale.com> wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
>
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node. DT binding documentation updates.
>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
It seems you missed to put Alison in the From field.
You should also put his Signed-off-by tag just before yours.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-14 15:57 ` Fabio Estevam
0 siblings, 0 replies; 43+ messages in thread
From: Fabio Estevam @ 2015-07-14 15:57 UTC (permalink / raw)
To: Claudiu Manoil
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel, Shawn Guo, Alison Wang
On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
<claudiu.manoil@freescale.com> wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
>
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node. DT binding documentation updates.
>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
It seems you missed to put Alison in the From field.
You should also put his Signed-off-by tag just before yours.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-14 15:57 ` Fabio Estevam
0 siblings, 0 replies; 43+ messages in thread
From: Fabio Estevam @ 2015-07-14 15:57 UTC (permalink / raw)
To: Claudiu Manoil
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel, Shawn Guo, Alison Wang
On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
<claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org> wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
>
> Signed-off-by: Alison Wang <alison.wang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
>
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node. DT binding documentation updates.
>
> Signed-off-by: Claudiu Manoil <claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
It seems you missed to put Alison in the From field.
You should also put his Signed-off-by tag just before yours.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
2015-07-14 15:57 ` Fabio Estevam
(?)
@ 2015-07-14 16:13 ` Manoil Claudiu
-1 siblings, 0 replies; 43+ messages in thread
From: Manoil Claudiu @ 2015-07-14 16:13 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Fabio Estevam [mailto:festevam at gmail.com]
> Sent: Tuesday, July 14, 2015 6:57 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> kernel; Shawn Guo; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
>
> On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
> <claudiu.manoil@freescale.com> wrote:
> > This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
> >
> > Signed-off-by: Alison Wang <alison.wang@freescale.com>
> >
> > Enable support for the second interrupt group register block
> > and the corresponding Rx/Tx/Err interrupt sources, for each
> > eTSEC node. DT binding documentation updates.
> >
> > Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
>
> It seems you missed to put Alison in the From field.
>
> You should also put his Signed-off-by tag just before yours.
Is this a rule invented by you? Last time I checked this was a
valid patch format. Also, this time I sent the (updated) patch,
not Alison, which should explain the "From" part. Thanks.
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-14 16:13 ` Manoil Claudiu
0 siblings, 0 replies; 43+ messages in thread
From: Manoil Claudiu @ 2015-07-14 16:13 UTC (permalink / raw)
To: Fabio Estevam
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel, Shawn Guo, Huan Wang
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8", Size: 1301 bytes --]
> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Tuesday, July 14, 2015 6:57 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel; Shawn Guo; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
>
> On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
> <claudiu.manoil@freescale.com> wrote:
> > This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
> >
> > Signed-off-by: Alison Wang <alison.wang@freescale.com>
> >
> > Enable support for the second interrupt group register block
> > and the corresponding Rx/Tx/Err interrupt sources, for each
> > eTSEC node. DT binding documentation updates.
> >
> > Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
>
> It seems you missed to put Alison in the From field.
>
> You should also put his Signed-off-by tag just before yours.
Is this a rule invented by you? Last time I checked this was a
valid patch format. Also, this time I sent the (updated) patch,
not Alison, which should explain the "From" part. Thanks.
ÿôèº{.nÇ+‰·Ÿ®‰†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a¢f£¢·hšïêÿ‘êçz_è®\x03(階ŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨èÚ&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥
^ permalink raw reply [flat|nested] 43+ messages in thread* RE: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-14 16:13 ` Manoil Claudiu
0 siblings, 0 replies; 43+ messages in thread
From: Manoil Claudiu @ 2015-07-14 16:13 UTC (permalink / raw)
To: Fabio Estevam
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel, Shawn Guo, Huan Wang
> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Tuesday, July 14, 2015 6:57 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel; Shawn Guo; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
>
> On Tue, Jul 14, 2015 at 12:46 PM, Claudiu Manoil
> <claudiu.manoil@freescale.com> wrote:
> > This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
> >
> > Signed-off-by: Alison Wang <alison.wang@freescale.com>
> >
> > Enable support for the second interrupt group register block
> > and the corresponding Rx/Tx/Err interrupt sources, for each
> > eTSEC node. DT binding documentation updates.
> >
> > Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
>
> It seems you missed to put Alison in the From field.
>
> You should also put his Signed-off-by tag just before yours.
Is this a rule invented by you? Last time I checked this was a
valid patch format. Also, this time I sent the (updated) patch,
not Alison, which should explain the "From" part. Thanks.
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-14 16:17 ` Fabio Estevam
0 siblings, 0 replies; 43+ messages in thread
From: Fabio Estevam @ 2015-07-14 16:17 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 14, 2015 at 1:13 PM, Manoil Claudiu
<claudiu.manoil@freescale.com> wrote:
>> You should also put his Signed-off-by tag just before yours.
>
> Is this a rule invented by you? Last time I checked this was a
No, just usual practice.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-14 16:17 ` Fabio Estevam
0 siblings, 0 replies; 43+ messages in thread
From: Fabio Estevam @ 2015-07-14 16:17 UTC (permalink / raw)
To: Manoil Claudiu
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel, Shawn Guo, Huan Wang
On Tue, Jul 14, 2015 at 1:13 PM, Manoil Claudiu
<claudiu.manoil@freescale.com> wrote:
>> You should also put his Signed-off-by tag just before yours.
>
> Is this a rule invented by you? Last time I checked this was a
No, just usual practice.
^ permalink raw reply [flat|nested] 43+ messages in thread
* Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-14 16:17 ` Fabio Estevam
0 siblings, 0 replies; 43+ messages in thread
From: Fabio Estevam @ 2015-07-14 16:17 UTC (permalink / raw)
To: Manoil Claudiu
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel, Shawn Guo, Huan Wang
On Tue, Jul 14, 2015 at 1:13 PM, Manoil Claudiu
<claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org> wrote:
>> You should also put his Signed-off-by tag just before yours.
>
> Is this a rule invented by you? Last time I checked this was a
No, just usual practice.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
2015-07-14 15:46 ` Claudiu Manoil
@ 2015-07-27 14:28 ` Shawn Guo
-1 siblings, 0 replies; 43+ messages in thread
From: Shawn Guo @ 2015-07-27 14:28 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 14, 2015 at 06:46:17PM +0300, Claudiu Manoil wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
SoBs should be put together.
>
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node. DT binding documentation updates.
>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Please use "ARM: dts: ls1021a: ..." as subject prefix.
> ---
> v2:
> - register block size is 0x1000 (4kB memory page), not 0x8000;
> - reg property has 2 "address" and resp. 2 "size" cells;
> - remove optional/ obsoleted properties;
> - use register block address as queue-group id for consistency;
> - binding documentation updates for missing vendor properties;
>
>
> .../devicetree/bindings/net/fsl-tsec-phy.txt | 6 +-
Bindings doc should be a separate patch reviewed by device tree
maintainers.
> arch/arm/boot/dts/ls1021a-qds.dts | 20 +++++
> arch/arm/boot/dts/ls1021a-twr.dts | 20 +++++
> arch/arm/boot/dts/ls1021a.dtsi | 92 ++++++++++++++++++++++
Please separate soc level dts changes from board level changes.
> 4 files changed, 137 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> index 1e97532..b3291c7 100644
> --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> @@ -45,7 +45,7 @@ Properties:
>
> - device_type : Should be "network"
> - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
> - - compatible : Should be "gianfar"
> + - compatible : "gianfar", "fsl-etsec2"
You meant "fsl,etsec2", which is what I see from dts changes?
> - reg : Offset and length of the register set for the device
> - interrupts : For FEC devices, the first interrupt is the device's
> interrupt. For TSEC and eTSEC devices, the first interrupt is
> @@ -57,6 +57,10 @@ Properties:
> "rgmii-id", as all other connection types are detected by hardware.
> - fsl,magic-packet : If present, indicates that the hardware supports
> waking up via magic packet.
> + - fsl,wake-on-filer: Indicates that the device can wake up the system
> + by generating a filer interrupt. Depending on the wake-on-lan mode
> + set for this device, the filer interrupt can be triggered by certain
> + user-defined ethernet packets (usually ARP or L2 unicast packets).
> - bd-stash : If present, indicates that the hardware supports stashing
> buffer descriptors in the L2.
> - rx-stash-len : Denotes the number of bytes of a received buffer to stash
> diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
> index 9c5e16b..f16a061 100644
> --- a/arch/arm/boot/dts/ls1021a-qds.dts
> +++ b/arch/arm/boot/dts/ls1021a-qds.dts
> @@ -75,6 +75,26 @@
> };
> };
>
> +&enet0 {
> + tbi-handle = <&tbi0>;
tbi-handle is undocumented.
> + phy-handle = <&sgmii_phy1c>;
> + phy-connection-type = "sgmii";
> + status = "okay";
> +};
> +
> +&enet1 {
> + tbi-handle = <&tbi0>;
> + phy-handle = <&sgmii_phy1d>;
> + phy-connection-type = "sgmii";
> + status = "okay";
> +};
> +
> +&enet2 {
> + phy-handle = <&rgmii_phy3>;
> + phy-connection-type = "rgmii-id";
> + status = "okay";
> +};
> +
> &i2c0 {
> status = "okay";
>
> diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
> index a2c591e..4b61766 100644
> --- a/arch/arm/boot/dts/ls1021a-twr.dts
> +++ b/arch/arm/boot/dts/ls1021a-twr.dts
> @@ -73,6 +73,26 @@
> };
> };
>
> +&enet0 {
> + tbi-handle = <&tbi1>;
> + phy-handle = <&sgmii_phy2>;
> + phy-connection-type = "sgmii";
> + status = "okay";
> +};
> +
> +&enet1 {
> + tbi-handle = <&tbi1>;
> + phy-handle = <&sgmii_phy0>;
> + phy-connection-type = "sgmii";
> + status = "okay";
> +};
> +
> +&enet2 {
> + phy-handle = <&rgmii_phy1>;
> + phy-connection-type = "rgmii-id";
> + status = "okay";
> +};
> +
> &i2c0 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index c70bb27..cc48d56 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
> serial3 = &lpuart3;
> serial4 = &lpuart4;
> serial5 = &lpuart5;
> + ethernet0 = &enet0;
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
> sysclk = &sysclk;
> };
>
> @@ -391,6 +394,95 @@
> reg = <0x0 0x2d24000 0x0 0x4000>;
> };
>
> + enet0: ethernet at 2d10000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + fsl,magic-packet;
> + fsl,wake-on-filer;
> + local-mac-address = [ 00 00 00 00 00 00 ];
What is this all zero local-mac-address used for?
Shawn
> + ranges;
> +
> + queue-group at 2d10000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d10000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group at 2d14000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d14000 0x0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet1: ethernet at 2d50000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + ranges;
> +
> + queue-group at 2d50000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d50000 0x0 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group at 2d54000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d54000 0x0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet2: ethernet at 2d90000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + ranges;
> +
> + queue-group at 2d90000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d90000 0x0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group at 2d94000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d94000 0x0 0x1000>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> usb at 8600000 {
> compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> reg = <0x0 0x8600000 0x0 0x1000>;
> --
> 1.7.11.7
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-27 14:28 ` Shawn Guo
0 siblings, 0 replies; 43+ messages in thread
From: Shawn Guo @ 2015-07-27 14:28 UTC (permalink / raw)
To: Claudiu Manoil
Cc: devicetree, linux-arm-kernel, linux-kernel, shawn.guo,
Alison Wang
On Tue, Jul 14, 2015 at 06:46:17PM +0300, Claudiu Manoil wrote:
> This patch adds generic dts nodes for eTSEC0, eTSEC1 and eTSEC2.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
SoBs should be put together.
>
> Enable support for the second interrupt group register block
> and the corresponding Rx/Tx/Err interrupt sources, for each
> eTSEC node. DT binding documentation updates.
>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Please use "ARM: dts: ls1021a: ..." as subject prefix.
> ---
> v2:
> - register block size is 0x1000 (4kB memory page), not 0x8000;
> - reg property has 2 "address" and resp. 2 "size" cells;
> - remove optional/ obsoleted properties;
> - use register block address as queue-group id for consistency;
> - binding documentation updates for missing vendor properties;
>
>
> .../devicetree/bindings/net/fsl-tsec-phy.txt | 6 +-
Bindings doc should be a separate patch reviewed by device tree
maintainers.
> arch/arm/boot/dts/ls1021a-qds.dts | 20 +++++
> arch/arm/boot/dts/ls1021a-twr.dts | 20 +++++
> arch/arm/boot/dts/ls1021a.dtsi | 92 ++++++++++++++++++++++
Please separate soc level dts changes from board level changes.
> 4 files changed, 137 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> index 1e97532..b3291c7 100644
> --- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> +++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
> @@ -45,7 +45,7 @@ Properties:
>
> - device_type : Should be "network"
> - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
> - - compatible : Should be "gianfar"
> + - compatible : "gianfar", "fsl-etsec2"
You meant "fsl,etsec2", which is what I see from dts changes?
> - reg : Offset and length of the register set for the device
> - interrupts : For FEC devices, the first interrupt is the device's
> interrupt. For TSEC and eTSEC devices, the first interrupt is
> @@ -57,6 +57,10 @@ Properties:
> "rgmii-id", as all other connection types are detected by hardware.
> - fsl,magic-packet : If present, indicates that the hardware supports
> waking up via magic packet.
> + - fsl,wake-on-filer: Indicates that the device can wake up the system
> + by generating a filer interrupt. Depending on the wake-on-lan mode
> + set for this device, the filer interrupt can be triggered by certain
> + user-defined ethernet packets (usually ARP or L2 unicast packets).
> - bd-stash : If present, indicates that the hardware supports stashing
> buffer descriptors in the L2.
> - rx-stash-len : Denotes the number of bytes of a received buffer to stash
> diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
> index 9c5e16b..f16a061 100644
> --- a/arch/arm/boot/dts/ls1021a-qds.dts
> +++ b/arch/arm/boot/dts/ls1021a-qds.dts
> @@ -75,6 +75,26 @@
> };
> };
>
> +&enet0 {
> + tbi-handle = <&tbi0>;
tbi-handle is undocumented.
> + phy-handle = <&sgmii_phy1c>;
> + phy-connection-type = "sgmii";
> + status = "okay";
> +};
> +
> +&enet1 {
> + tbi-handle = <&tbi0>;
> + phy-handle = <&sgmii_phy1d>;
> + phy-connection-type = "sgmii";
> + status = "okay";
> +};
> +
> +&enet2 {
> + phy-handle = <&rgmii_phy3>;
> + phy-connection-type = "rgmii-id";
> + status = "okay";
> +};
> +
> &i2c0 {
> status = "okay";
>
> diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
> index a2c591e..4b61766 100644
> --- a/arch/arm/boot/dts/ls1021a-twr.dts
> +++ b/arch/arm/boot/dts/ls1021a-twr.dts
> @@ -73,6 +73,26 @@
> };
> };
>
> +&enet0 {
> + tbi-handle = <&tbi1>;
> + phy-handle = <&sgmii_phy2>;
> + phy-connection-type = "sgmii";
> + status = "okay";
> +};
> +
> +&enet1 {
> + tbi-handle = <&tbi1>;
> + phy-handle = <&sgmii_phy0>;
> + phy-connection-type = "sgmii";
> + status = "okay";
> +};
> +
> +&enet2 {
> + phy-handle = <&rgmii_phy1>;
> + phy-connection-type = "rgmii-id";
> + status = "okay";
> +};
> +
> &i2c0 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index c70bb27..cc48d56 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
> serial3 = &lpuart3;
> serial4 = &lpuart4;
> serial5 = &lpuart5;
> + ethernet0 = &enet0;
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
> sysclk = &sysclk;
> };
>
> @@ -391,6 +394,95 @@
> reg = <0x0 0x2d24000 0x0 0x4000>;
> };
>
> + enet0: ethernet@2d10000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + fsl,magic-packet;
> + fsl,wake-on-filer;
> + local-mac-address = [ 00 00 00 00 00 00 ];
What is this all zero local-mac-address used for?
Shawn
> + ranges;
> +
> + queue-group@2d10000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d10000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d14000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d14000 0x0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet1: ethernet@2d50000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + ranges;
> +
> + queue-group@2d50000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d50000 0x0 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d54000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d54000 0x0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet2: ethernet@2d90000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + ranges;
> +
> + queue-group@2d90000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d90000 0x0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d94000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d94000 0x0 0x1000>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> usb@8600000 {
> compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> reg = <0x0 0x8600000 0x0 0x1000>;
> --
> 1.7.11.7
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
2015-07-27 14:28 ` Shawn Guo
(?)
@ 2015-07-27 16:09 ` Manoil Claudiu
-1 siblings, 0 replies; 43+ messages in thread
From: Manoil Claudiu @ 2015-07-27 16:09 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo at kernel.org]
> Sent: Monday, July 27, 2015 5:28 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> kernel at vger.kernel.org; shawn.guo at linaro.org; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
>
[...]
> >
> > .../devicetree/bindings/net/fsl-tsec-phy.txt | 6 +-
>
> Bindings doc should be a separate patch reviewed by device tree
> maintainers.
>
> > arch/arm/boot/dts/ls1021a-qds.dts | 20 +++++
> > arch/arm/boot/dts/ls1021a-twr.dts | 20 +++++
> > arch/arm/boot/dts/ls1021a.dtsi | 92
> ++++++++++++++++++++++
>
> Please separate soc level dts changes from board level changes.
>
Ok, will break this in 3 patches (soc, boards, bindings), trimmed down as much as possible,
with remaining findings addressed. Thanks.
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-27 16:09 ` Manoil Claudiu
0 siblings, 0 replies; 43+ messages in thread
From: Manoil Claudiu @ 2015-07-27 16:09 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, shawn.guo@linaro.org, Huan Wang
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo@kernel.org]
> Sent: Monday, July 27, 2015 5:28 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; shawn.guo@linaro.org; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
>
[...]
> >
> > .../devicetree/bindings/net/fsl-tsec-phy.txt | 6 +-
>
> Bindings doc should be a separate patch reviewed by device tree
> maintainers.
>
> > arch/arm/boot/dts/ls1021a-qds.dts | 20 +++++
> > arch/arm/boot/dts/ls1021a-twr.dts | 20 +++++
> > arch/arm/boot/dts/ls1021a.dtsi | 92
> ++++++++++++++++++++++
>
> Please separate soc level dts changes from board level changes.
>
Ok, will break this in 3 patches (soc, boards, bindings), trimmed down as much as possible,
with remaining findings addressed. Thanks.
^ permalink raw reply [flat|nested] 43+ messages in thread
* RE: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and eTSEC2
@ 2015-07-27 16:09 ` Manoil Claudiu
0 siblings, 0 replies; 43+ messages in thread
From: Manoil Claudiu @ 2015-07-27 16:09 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, Huan Wang
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> Sent: Monday, July 27, 2015 5:28 PM
> To: Manoil Claudiu-B08782
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; linux-
> kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org; Wang Huan-B18965
> Subject: Re: [PATCH v2] dts: ls1021a: Add dts nodes for eTSEC0, eTSEC1 and
> eTSEC2
>
[...]
> >
> > .../devicetree/bindings/net/fsl-tsec-phy.txt | 6 +-
>
> Bindings doc should be a separate patch reviewed by device tree
> maintainers.
>
> > arch/arm/boot/dts/ls1021a-qds.dts | 20 +++++
> > arch/arm/boot/dts/ls1021a-twr.dts | 20 +++++
> > arch/arm/boot/dts/ls1021a.dtsi | 92
> ++++++++++++++++++++++
>
> Please separate soc level dts changes from board level changes.
>
Ok, will break this in 3 patches (soc, boards, bindings), trimmed down as much as possible,
with remaining findings addressed. Thanks.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH,v3 1/3] doc: dt: Update eTSEC bindings doc
2015-07-27 14:28 ` Shawn Guo
(?)
@ 2015-07-28 14:43 ` Claudiu Manoil
-1 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-28 14:43 UTC (permalink / raw)
To: linux-arm-kernel
Update the eTSEC bindings document with missing info on
properties that are already in use for the PPC platforms:
* "tbi-phy" property;
* "fsl,etsec2" compatibility string;
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2 - none;
v3 - added "tbi-handle" documentation;
- fixed typo ("fsl,etsec2" is the correct string);
Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..325c07d 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,12 +45,15 @@ Properties:
- device_type : Should be "network"
- model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
- - compatible : Should be "gianfar"
+ - compatible : "gianfar", "fsl,etsec2"
- reg : Offset and length of the register set for the device
- interrupts : For FEC devices, the first interrupt is the device's
interrupt. For TSEC and eTSEC devices, the first interrupt is
transmit, the second is receive, and the third is error.
- phy-handle : See ethernet.txt file in the same directory.
+ - tbi-handle : Handle to a tbi-phy node containing information about
+ the TBIPA register needed to initialize the TBI PHY. See
+ "TBI Internal MDIO bus", this document.
- fixed-link : See fixed-link.txt in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory.
This property is only really needed if the connection is of type
--
1.7.11.7
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH,v3 1/3] doc: dt: Update eTSEC bindings doc
@ 2015-07-28 14:43 ` Claudiu Manoil
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-28 14:43 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, shawnguo; +Cc: shawn.guo, galak
Update the eTSEC bindings document with missing info on
properties that are already in use for the PPC platforms:
* "tbi-phy" property;
* "fsl,etsec2" compatibility string;
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2 - none;
v3 - added "tbi-handle" documentation;
- fixed typo ("fsl,etsec2" is the correct string);
Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..325c07d 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,12 +45,15 @@ Properties:
- device_type : Should be "network"
- model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
- - compatible : Should be "gianfar"
+ - compatible : "gianfar", "fsl,etsec2"
- reg : Offset and length of the register set for the device
- interrupts : For FEC devices, the first interrupt is the device's
interrupt. For TSEC and eTSEC devices, the first interrupt is
transmit, the second is receive, and the third is error.
- phy-handle : See ethernet.txt file in the same directory.
+ - tbi-handle : Handle to a tbi-phy node containing information about
+ the TBIPA register needed to initialize the TBI PHY. See
+ "TBI Internal MDIO bus", this document.
- fixed-link : See fixed-link.txt in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory.
This property is only really needed if the connection is of type
--
1.7.11.7
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH,v3 1/3] doc: dt: Update eTSEC bindings doc
@ 2015-07-28 14:43 ` Claudiu Manoil
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-28 14:43 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, shawnguo; +Cc: shawn.guo, galak
Update the eTSEC bindings document with missing info on
properties that are already in use for the PPC platforms:
* "tbi-phy" property;
* "fsl,etsec2" compatibility string;
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2 - none;
v3 - added "tbi-handle" documentation;
- fixed typo ("fsl,etsec2" is the correct string);
Documentation/devicetree/bindings/net/fsl-tsec-phy.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index 1e97532..325c07d 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -45,12 +45,15 @@ Properties:
- device_type : Should be "network"
- model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
- - compatible : Should be "gianfar"
+ - compatible : "gianfar", "fsl,etsec2"
- reg : Offset and length of the register set for the device
- interrupts : For FEC devices, the first interrupt is the device's
interrupt. For TSEC and eTSEC devices, the first interrupt is
transmit, the second is receive, and the third is error.
- phy-handle : See ethernet.txt file in the same directory.
+ - tbi-handle : Handle to a tbi-phy node containing information about
+ the TBIPA register needed to initialize the TBI PHY. See
+ "TBI Internal MDIO bus", this document.
- fixed-link : See fixed-link.txt in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory.
This property is only really needed if the connection is of type
--
1.7.11.7
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes
2015-07-28 14:43 ` Claudiu Manoil
(?)
@ 2015-07-28 14:43 ` Claudiu Manoil
-1 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-28 14:43 UTC (permalink / raw)
To: linux-arm-kernel
Add basic support for all the eTSEC controllers on the
ls1021a SoC. Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2: various findings, added 2nd interrupt group;
v3: addressed findings from Shawn Guo -
- initial patch split in soc, boards and bindings patches;
- removed redundant all zero local-mac-address;
- subject prefix;
arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 1b306c7..0638cda 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
serial3 = &lpuart3;
serial4 = &lpuart4;
serial5 = &lpuart5;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
sysclk = &sysclk;
};
@@ -391,6 +394,91 @@
reg = <0x0 0x2d24000 0x0 0x4000>;
};
+ enet0: ethernet at 2d10000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ fsl,magic-packet;
+ ranges;
+
+ queue-group at 2d10000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group at 2d14000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ enet1: ethernet at 2d50000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ ranges;
+
+ queue-group at 2d50000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d50000 0x0 0x1000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group at 2d54000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d54000 0x0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ enet2: ethernet at 2d90000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ ranges;
+
+ queue-group at 2d90000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d90000 0x0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group at 2d94000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d94000 0x0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
usb at 8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
--
1.7.11.7
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes
@ 2015-07-28 14:43 ` Claudiu Manoil
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-28 14:43 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, shawnguo
Cc: shawn.guo, galak, Alison Wang
Add basic support for all the eTSEC controllers on the
ls1021a SoC. Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2: various findings, added 2nd interrupt group;
v3: addressed findings from Shawn Guo -
- initial patch split in soc, boards and bindings patches;
- removed redundant all zero local-mac-address;
- subject prefix;
arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 1b306c7..0638cda 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
serial3 = &lpuart3;
serial4 = &lpuart4;
serial5 = &lpuart5;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
sysclk = &sysclk;
};
@@ -391,6 +394,91 @@
reg = <0x0 0x2d24000 0x0 0x4000>;
};
+ enet0: ethernet@2d10000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ fsl,magic-packet;
+ ranges;
+
+ queue-group@2d10000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d14000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ enet1: ethernet@2d50000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ ranges;
+
+ queue-group@2d50000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d50000 0x0 0x1000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d54000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d54000 0x0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ enet2: ethernet@2d90000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ ranges;
+
+ queue-group@2d90000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d90000 0x0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d94000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d94000 0x0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
usb@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
--
1.7.11.7
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes
@ 2015-07-28 14:43 ` Claudiu Manoil
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-28 14:43 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, shawnguo
Cc: shawn.guo, galak, Alison Wang
Add basic support for all the eTSEC controllers on the
ls1021a SoC. Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2: various findings, added 2nd interrupt group;
v3: addressed findings from Shawn Guo -
- initial patch split in soc, boards and bindings patches;
- removed redundant all zero local-mac-address;
- subject prefix;
arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 1b306c7..0638cda 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -59,6 +59,9 @@
serial3 = &lpuart3;
serial4 = &lpuart4;
serial5 = &lpuart5;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
sysclk = &sysclk;
};
@@ -391,6 +394,91 @@
reg = <0x0 0x2d24000 0x0 0x4000>;
};
+ enet0: ethernet@2d10000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ fsl,magic-packet;
+ ranges;
+
+ queue-group@2d10000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d10000 0x0 0x1000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d14000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ enet1: ethernet@2d50000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ ranges;
+
+ queue-group@2d50000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d50000 0x0 0x1000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d54000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d54000 0x0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ enet2: ethernet@2d90000 {
+ compatible = "fsl,etsec2";
+ device_type = "network";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+ model = "eTSEC";
+ ranges;
+
+ queue-group@2d90000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d90000 0x0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ queue-group@2d94000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d94000 0x0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
usb@8600000 {
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
reg = <0x0 0x8600000 0x0 0x1000>;
--
1.7.11.7
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes
@ 2015-08-05 11:57 ` Shawn Guo
0 siblings, 0 replies; 43+ messages in thread
From: Shawn Guo @ 2015-08-05 11:57 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 28, 2015 at 05:43:55PM +0300, Claudiu Manoil wrote:
> Add basic support for all the eTSEC controllers on the
> ls1021a SoC. Second interrupt group register blocks
> and their corresponding Rx/Tx/Err interrupt sources are
> included as well for each eTSEC node.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Applied both with a minor change below.
> ---
> v2: various findings, added 2nd interrupt group;
> v3: addressed findings from Shawn Guo -
> - initial patch split in soc, boards and bindings patches;
> - removed redundant all zero local-mac-address;
> - subject prefix;
>
> arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 1b306c7..0638cda 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
> serial3 = &lpuart3;
> serial4 = &lpuart4;
> serial5 = &lpuart5;
> + ethernet0 = &enet0;
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
I moved these above serial to keep them sort alphabetically.
Shawn
> sysclk = &sysclk;
> };
>
> @@ -391,6 +394,91 @@
> reg = <0x0 0x2d24000 0x0 0x4000>;
> };
>
> + enet0: ethernet at 2d10000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + fsl,magic-packet;
> + ranges;
> +
> + queue-group at 2d10000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d10000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group at 2d14000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d14000 0x0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet1: ethernet at 2d50000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group at 2d50000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d50000 0x0 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group at 2d54000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d54000 0x0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet2: ethernet at 2d90000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group at 2d90000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d90000 0x0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group at 2d94000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d94000 0x0 0x1000>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> usb at 8600000 {
> compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> reg = <0x0 0x8600000 0x0 0x1000>;
> --
> 1.7.11.7
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes
@ 2015-08-05 11:57 ` Shawn Guo
0 siblings, 0 replies; 43+ messages in thread
From: Shawn Guo @ 2015-08-05 11:57 UTC (permalink / raw)
To: Claudiu Manoil
Cc: devicetree, linux-arm-kernel, linux-kernel, Alison Wang,
shawn.guo, galak
On Tue, Jul 28, 2015 at 05:43:55PM +0300, Claudiu Manoil wrote:
> Add basic support for all the eTSEC controllers on the
> ls1021a SoC. Second interrupt group register blocks
> and their corresponding Rx/Tx/Err interrupt sources are
> included as well for each eTSEC node.
>
> Signed-off-by: Alison Wang <alison.wang@freescale.com>
> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Applied both with a minor change below.
> ---
> v2: various findings, added 2nd interrupt group;
> v3: addressed findings from Shawn Guo -
> - initial patch split in soc, boards and bindings patches;
> - removed redundant all zero local-mac-address;
> - subject prefix;
>
> arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 1b306c7..0638cda 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
> serial3 = &lpuart3;
> serial4 = &lpuart4;
> serial5 = &lpuart5;
> + ethernet0 = &enet0;
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
I moved these above serial to keep them sort alphabetically.
Shawn
> sysclk = &sysclk;
> };
>
> @@ -391,6 +394,91 @@
> reg = <0x0 0x2d24000 0x0 0x4000>;
> };
>
> + enet0: ethernet@2d10000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + fsl,magic-packet;
> + ranges;
> +
> + queue-group@2d10000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d10000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d14000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d14000 0x0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet1: ethernet@2d50000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group@2d50000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d50000 0x0 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d54000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d54000 0x0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet2: ethernet@2d90000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group@2d90000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d90000 0x0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d94000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d94000 0x0 0x1000>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> usb@8600000 {
> compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> reg = <0x0 0x8600000 0x0 0x1000>;
> --
> 1.7.11.7
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply [flat|nested] 43+ messages in thread* Re: [PATCH,v3 2/3] ARM: dts: ls1021a: Add the eTSEC controller nodes
@ 2015-08-05 11:57 ` Shawn Guo
0 siblings, 0 replies; 43+ messages in thread
From: Shawn Guo @ 2015-08-05 11:57 UTC (permalink / raw)
To: Claudiu Manoil
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Alison Wang,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A, galak-sgV2jX0FEOL9JmXXK+q4OQ
On Tue, Jul 28, 2015 at 05:43:55PM +0300, Claudiu Manoil wrote:
> Add basic support for all the eTSEC controllers on the
> ls1021a SoC. Second interrupt group register blocks
> and their corresponding Rx/Tx/Err interrupt sources are
> included as well for each eTSEC node.
>
> Signed-off-by: Alison Wang <alison.wang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Claudiu Manoil <claudiu.manoil-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Applied both with a minor change below.
> ---
> v2: various findings, added 2nd interrupt group;
> v3: addressed findings from Shawn Guo -
> - initial patch split in soc, boards and bindings patches;
> - removed redundant all zero local-mac-address;
> - subject prefix;
>
> arch/arm/boot/dts/ls1021a.dtsi | 88 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 1b306c7..0638cda 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -59,6 +59,9 @@
> serial3 = &lpuart3;
> serial4 = &lpuart4;
> serial5 = &lpuart5;
> + ethernet0 = &enet0;
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
I moved these above serial to keep them sort alphabetically.
Shawn
> sysclk = &sysclk;
> };
>
> @@ -391,6 +394,91 @@
> reg = <0x0 0x2d24000 0x0 0x4000>;
> };
>
> + enet0: ethernet@2d10000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + fsl,magic-packet;
> + ranges;
> +
> + queue-group@2d10000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d10000 0x0 0x1000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d14000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d14000 0x0 0x1000>;
> + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet1: ethernet@2d50000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group@2d50000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d50000 0x0 0x1000>;
> + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d54000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d54000 0x0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + enet2: ethernet@2d90000 {
> + compatible = "fsl,etsec2";
> + device_type = "network";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + model = "eTSEC";
> + ranges;
> +
> + queue-group@2d90000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d90000 0x0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + queue-group@2d94000 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0x0 0x2d94000 0x0 0x1000>;
> + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> usb@8600000 {
> compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
> reg = <0x0 0x8600000 0x0 0x1000>;
> --
> 1.7.11.7
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH, v3 3/3] ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR
2015-07-28 14:43 ` Claudiu Manoil
(?)
@ 2015-07-28 14:43 ` Claudiu Manoil
-1 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-28 14:43 UTC (permalink / raw)
To: linux-arm-kernel
This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2, v3 - none;
arch/arm/boot/dts/ls1021a-qds.dts | 20 ++++++++++++++++++++
arch/arm/boot/dts/ls1021a-twr.dts | 20 ++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1c>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1d>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy3>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy0>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
--
1.7.11.7
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH,v3 3/3] ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR
@ 2015-07-28 14:43 ` Claudiu Manoil
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-28 14:43 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, shawnguo
Cc: shawn.guo, galak, Alison Wang
This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2, v3 - none;
arch/arm/boot/dts/ls1021a-qds.dts | 20 ++++++++++++++++++++
arch/arm/boot/dts/ls1021a-twr.dts | 20 ++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1c>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1d>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy3>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy0>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
--
1.7.11.7
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH,v3 3/3] ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR
@ 2015-07-28 14:43 ` Claudiu Manoil
0 siblings, 0 replies; 43+ messages in thread
From: Claudiu Manoil @ 2015-07-28 14:43 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel, shawnguo
Cc: shawn.guo, galak, Alison Wang
This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
v2, v3 - none;
arch/arm/boot/dts/ls1021a-qds.dts | 20 ++++++++++++++++++++
arch/arm/boot/dts/ls1021a-twr.dts | 20 ++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 9c5e16b..f16a061 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -75,6 +75,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1c>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&sgmii_phy1d>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy3>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index a2c591e..4b61766 100644
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -73,6 +73,26 @@
};
};
+&enet0 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy2>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet1 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&sgmii_phy0>;
+ phy-connection-type = "sgmii";
+ status = "okay";
+};
+
+&enet2 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
--
1.7.11.7
^ permalink raw reply related [flat|nested] 43+ messages in thread