From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 01/11] arm-cci: Define CCI counter period
Date: Mon, 4 Jan 2016 18:27:52 +0000 [thread overview]
Message-ID: <20160104181940.GA17127@leverpostej> (raw)
In-Reply-To: <1451908490-2615-2-git-send-email-suzuki.poulose@arm.com>
On Mon, Jan 04, 2016 at 11:54:40AM +0000, Suzuki K. Poulose wrote:
> Instead of hard coding the period we program on the PMU
> counters, define a symbol.
>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Punit Agrawal <punit.agrawal@arm.com>
> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
> ---
> drivers/bus/arm-cci.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
> index ee47e6b..3786879 100644
> --- a/drivers/bus/arm-cci.c
> +++ b/drivers/bus/arm-cci.c
> @@ -85,6 +85,14 @@ static const struct of_device_id arm_cci_matches[] = {
> #define CCI_PMU_CNTR_MASK ((1ULL << 32) -1)
> #define CCI_PMU_CNTR_LAST(cci_pmu) (cci_pmu->num_cntrs - 1)
>
> +/*
> + * The CCI PMU counters have a period of 2^32. To account for the
> + * possiblity of extreme interrupt latency we program for a period of
> + * half that. Hopefully we can handle the interrupt before another 2^31
> + * events occur and the counter overtakes its previous value.
> + */
> +#define CCI_CNTR_PERIOD (1UL << 31)
> +
> #define CCI_PMU_MAX_HW_CNTRS(model) \
> ((model)->num_hw_cntrs + (model)->fixed_hw_cntrs)
>
> @@ -797,15 +805,8 @@ static void pmu_read(struct perf_event *event)
> void pmu_event_set_period(struct perf_event *event)
> {
> struct hw_perf_event *hwc = &event->hw;
> - /*
> - * The CCI PMU counters have a period of 2^32. To account for the
> - * possiblity of extreme interrupt latency we program for a period of
> - * half that. Hopefully we can handle the interrupt before another 2^31
> - * events occur and the counter overtakes its previous value.
> - */
> - u64 val = 1ULL << 31;
> - local64_set(&hwc->prev_count, val);
> - pmu_write_counter(event, val);
> + local64_set(&hwc->prev_count, CCI_CNTR_PERIOD);
> + pmu_write_counter(event, CCI_CNTR_PERIOD);
I think this is a little misleading (and confusing), as we're conflating
the period with its inverse. This wouldn't work for any other value of
CCI_CNTR_PERIOD.
Perhaps s/PERIOD/START_VAL/, leaving everything else as-is?
Thanks,
Mark.
WARNING: multiple messages have this Message-ID (diff)
From: Mark Rutland <mark.rutland@arm.com>
To: "Suzuki K. Poulose" <suzuki.poulose@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, arm@kernel.org,
punit.agrawal@arm.com, peterz@infradead.org
Subject: Re: [PATCH v5 01/11] arm-cci: Define CCI counter period
Date: Mon, 4 Jan 2016 18:27:52 +0000 [thread overview]
Message-ID: <20160104181940.GA17127@leverpostej> (raw)
In-Reply-To: <1451908490-2615-2-git-send-email-suzuki.poulose@arm.com>
On Mon, Jan 04, 2016 at 11:54:40AM +0000, Suzuki K. Poulose wrote:
> Instead of hard coding the period we program on the PMU
> counters, define a symbol.
>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Punit Agrawal <punit.agrawal@arm.com>
> Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
> ---
> drivers/bus/arm-cci.c | 19 ++++++++++---------
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
> index ee47e6b..3786879 100644
> --- a/drivers/bus/arm-cci.c
> +++ b/drivers/bus/arm-cci.c
> @@ -85,6 +85,14 @@ static const struct of_device_id arm_cci_matches[] = {
> #define CCI_PMU_CNTR_MASK ((1ULL << 32) -1)
> #define CCI_PMU_CNTR_LAST(cci_pmu) (cci_pmu->num_cntrs - 1)
>
> +/*
> + * The CCI PMU counters have a period of 2^32. To account for the
> + * possiblity of extreme interrupt latency we program for a period of
> + * half that. Hopefully we can handle the interrupt before another 2^31
> + * events occur and the counter overtakes its previous value.
> + */
> +#define CCI_CNTR_PERIOD (1UL << 31)
> +
> #define CCI_PMU_MAX_HW_CNTRS(model) \
> ((model)->num_hw_cntrs + (model)->fixed_hw_cntrs)
>
> @@ -797,15 +805,8 @@ static void pmu_read(struct perf_event *event)
> void pmu_event_set_period(struct perf_event *event)
> {
> struct hw_perf_event *hwc = &event->hw;
> - /*
> - * The CCI PMU counters have a period of 2^32. To account for the
> - * possiblity of extreme interrupt latency we program for a period of
> - * half that. Hopefully we can handle the interrupt before another 2^31
> - * events occur and the counter overtakes its previous value.
> - */
> - u64 val = 1ULL << 31;
> - local64_set(&hwc->prev_count, val);
> - pmu_write_counter(event, val);
> + local64_set(&hwc->prev_count, CCI_CNTR_PERIOD);
> + pmu_write_counter(event, CCI_CNTR_PERIOD);
I think this is a little misleading (and confusing), as we're conflating
the period with its inverse. This wouldn't work for any other value of
CCI_CNTR_PERIOD.
Perhaps s/PERIOD/START_VAL/, leaving everything else as-is?
Thanks,
Mark.
next prev parent reply other threads:[~2016-01-04 18:27 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-04 11:54 [PATCH v5 00/11] arm-cci: PMU updates Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 01/11] arm-cci: Define CCI counter period Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-04 18:27 ` Mark Rutland [this message]
2016-01-04 18:27 ` Mark Rutland
2016-01-05 9:50 ` Suzuki K. Poulose
2016-01-05 9:50 ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 02/11] arm-cci: Refactor pmu_write_counter Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-04 19:01 ` Mark Rutland
2016-01-04 19:01 ` Mark Rutland
2016-01-04 11:54 ` [PATCH v5 03/11] arm-cci: Group writes to counter Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-04 19:03 ` Mark Rutland
2016-01-04 19:03 ` Mark Rutland
2016-01-05 10:51 ` Suzuki K. Poulose
2016-01-05 10:51 ` Suzuki K. Poulose
2016-01-11 10:44 ` Mark Rutland
2016-01-11 10:44 ` Mark Rutland
2016-01-11 10:48 ` Suzuki K. Poulose
2016-01-11 10:48 ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 04/11] arm-cci: Refactor CCI PMU enable/disable methods Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 05/11] arm-cci PMU: Delay counter writes to pmu_enable Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-04 19:24 ` Mark Rutland
2016-01-04 19:24 ` Mark Rutland
2016-01-05 9:59 ` Suzuki K. Poulose
2016-01-05 9:59 ` Suzuki K. Poulose
2016-01-11 10:46 ` Mark Rutland
2016-01-11 10:46 ` Mark Rutland
2016-01-11 11:08 ` Suzuki K. Poulose
2016-01-11 11:08 ` Suzuki K. Poulose
2016-01-11 11:24 ` Mark Rutland
2016-01-11 11:24 ` Mark Rutland
2016-01-11 18:12 ` Suzuki K. Poulose
2016-01-11 18:12 ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 06/11] arm-cci: Get the status of a counter Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 07/11] arm-cci: Add routines to save/restore all counters Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-11 10:50 ` Mark Rutland
2016-01-11 10:50 ` Mark Rutland
2016-01-11 10:58 ` Suzuki K. Poulose
2016-01-11 10:58 ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 08/11] arm-cci: Provide hook for writing to PMU counters Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-11 10:54 ` Mark Rutland
2016-01-11 10:54 ` Mark Rutland
2016-01-11 12:14 ` Suzuki K. Poulose
2016-01-11 12:14 ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 09/11] arm-cci: CCI-500: Work around PMU counter writes Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 10/11] arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
2016-01-04 11:54 ` [PATCH v5 11/11] arm-cci: CoreLink CCI-550 PMU driver Suzuki K. Poulose
2016-01-04 11:54 ` Suzuki K. Poulose
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