From: Thierry Reding <thierry.reding@gmail.com>
To: Rhyland Klein <rklein@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Alexandre Courbot <gnurou@gmail.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Date: Tue, 12 Apr 2016 17:23:36 +0200 [thread overview]
Message-ID: <20160412152336.GF25160@ulmo.ba.sec> (raw)
In-Reply-To: <1458590333-8898-1-git-send-email-rklein@nvidia.com>
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On Mon, Mar 21, 2016 at 03:58:52PM -0400, Rhyland Klein wrote:
> Use a new Tegra210 version of the pll_register_pllre function to
> allow setting the proper settings for the m and n div fields.
>
> Additionally define PLL_RE_OUT1 on Tegra210.
It'd be nice to specify what that additional clock is used for. No need
to repost for that, I can add it when applying.
Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Peter De Schrijver
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Prashant Gaikwad
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Alexandre Courbot
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Date: Tue, 12 Apr 2016 17:23:36 +0200 [thread overview]
Message-ID: <20160412152336.GF25160@ulmo.ba.sec> (raw)
In-Reply-To: <1458590333-8898-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
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On Mon, Mar 21, 2016 at 03:58:52PM -0400, Rhyland Klein wrote:
> Use a new Tegra210 version of the pll_register_pllre function to
> allow setting the proper settings for the m and n div fields.
>
> Additionally define PLL_RE_OUT1 on Tegra210.
It'd be nice to specify what that additional clock is used for. No need
to repost for that, I can add it when applying.
Thierry
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next prev parent reply other threads:[~2016-04-12 15:23 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-21 19:58 [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1 Rhyland Klein
2016-03-21 19:58 ` Rhyland Klein
2016-03-21 19:58 ` [PATCH 2/2] clk: tegra: Initialize UTMIPLL when enabling PLLU Rhyland Klein
2016-04-15 23:49 ` Stephen Boyd
2016-04-08 15:19 ` [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1 Rhyland Klein
2016-04-08 15:19 ` Rhyland Klein
2016-04-12 15:23 ` Thierry Reding [this message]
2016-04-12 15:23 ` Thierry Reding
2016-04-15 15:29 ` Rhyland Klein
2016-04-15 15:29 ` Rhyland Klein
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