From: Rhyland Klein <rklein@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Stephen Warren <swarren@wwwdotorg.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Alexandre Courbot <gnurou@gmail.com>, <linux-clk@vger.kernel.org>,
<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Date: Fri, 15 Apr 2016 11:29:22 -0400 [thread overview]
Message-ID: <571108D2.2040501@nvidia.com> (raw)
In-Reply-To: <20160412152336.GF25160@ulmo.ba.sec>
On 4/12/2016 11:23 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Mar 21, 2016 at 03:58:52PM -0400, Rhyland Klein wrote:
>> Use a new Tegra210 version of the pll_register_pllre function to
>> allow setting the proper settings for the m and n div fields.
>>
>> Additionally define PLL_RE_OUT1 on Tegra210.
>
> It'd be nice to specify what that additional clock is used for. No need
> to repost for that, I can add it when applying.
>
Its not currently directly used on the A44 platform I was testing with,
but from what I understand, it is connected to the Tegra210 debug
interfaces and so its probably good to have it defined in case it is
needed for some debugging.
-rhyland
--
nvpublic
WARNING: multiple messages have this Message-ID (diff)
From: Rhyland Klein <rklein@nvidia.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
Alexandre Courbot <gnurou@gmail.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1
Date: Fri, 15 Apr 2016 11:29:22 -0400 [thread overview]
Message-ID: <571108D2.2040501@nvidia.com> (raw)
In-Reply-To: <20160412152336.GF25160@ulmo.ba.sec>
On 4/12/2016 11:23 AM, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Mar 21, 2016 at 03:58:52PM -0400, Rhyland Klein wrote:
>> Use a new Tegra210 version of the pll_register_pllre function to
>> allow setting the proper settings for the m and n div fields.
>>
>> Additionally define PLL_RE_OUT1 on Tegra210.
>
> It'd be nice to specify what that additional clock is used for. No need
> to repost for that, I can add it when applying.
>
Its not currently directly used on the A44 platform I was testing with,
but from what I understand, it is connected to the Tegra210 debug
interfaces and so its probably good to have it defined in case it is
needed for some debugging.
-rhyland
--
nvpublic
next prev parent reply other threads:[~2016-04-15 15:29 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-21 19:58 [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1 Rhyland Klein
2016-03-21 19:58 ` Rhyland Klein
2016-03-21 19:58 ` [PATCH 2/2] clk: tegra: Initialize UTMIPLL when enabling PLLU Rhyland Klein
2016-04-15 23:49 ` Stephen Boyd
2016-04-08 15:19 ` [PATCH 1/2] clk: tegra: Fix pllre Tegra210 and add pll_re_out1 Rhyland Klein
2016-04-08 15:19 ` Rhyland Klein
2016-04-12 15:23 ` Thierry Reding
2016-04-12 15:23 ` Thierry Reding
2016-04-15 15:29 ` Rhyland Klein [this message]
2016-04-15 15:29 ` Rhyland Klein
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